Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 | Date : Wed Jul 8 02:57:54 2026 | Host : fedora running 64-bit unknown | Command : report_timing_summary -delay_type max -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/vivado_reports_withdsp/timing_summary_full.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 38 input ports with no input delay specified. (HIGH) UART_RX UART_TX dip_sw[0] dip_sw[10] dip_sw[11] dip_sw[12] dip_sw[13] dip_sw[14] dip_sw[15] dip_sw[16] dip_sw[17] dip_sw[18] dip_sw[19] dip_sw[1] dip_sw[20] dip_sw[21] dip_sw[22] dip_sw[23] dip_sw[24] dip_sw[25] dip_sw[26] dip_sw[27] dip_sw[28] dip_sw[29] dip_sw[2] dip_sw[30] dip_sw[31] dip_sw[3] dip_sw[4] dip_sw[5] dip_sw[6] dip_sw[7] dip_sw[8] dip_sw[9] touch_btn[0] touch_btn[1] touch_btn[2] touch_btn[3] There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 40 ports with no output delay specified. (HIGH) UART_RX UART_TX dpy0[0] dpy0[1] dpy0[2] dpy0[3] dpy0[4] dpy0[5] dpy0[6] dpy0[7] dpy1[0] dpy1[1] dpy1[2] dpy1[3] dpy1[4] dpy1[5] dpy1[6] dpy1[7] leds[0] leds[10] leds[11] leds[12] leds[13] leds[14] leds[15] leds[1] leds[2] leds[3] leds[4] leds[5] leds[6] leds[7] leds[8] leds[9] video_de video_hsync video_red[0] video_red[1] video_red[2] video_vsync There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.424 0.000 0 115919 7.000 0.000 0 41847 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk {0.000 10.000} 20.000 50.000 clkfbout_clk_pll {0.000 10.000} 20.000 50.000 cpu_clk {0.000 15.161} 30.323 32.979 mlkem_clk_clk_pll {0.000 20.000} 40.000 25.000 sys_clk {0.000 10.000} 20.000 50.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk 7.000 0.000 0 1 clkfbout_clk_pll 17.845 0.000 0 3 cpu_clk 1.137 0.000 0 17197 13.911 0.000 0 6486 mlkem_clk_clk_pll 12.906 0.000 0 49560 18.750 0.000 0 25777 sys_clk 0.424 0.000 0 22846 8.750 0.000 0 9580 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- sys_clk mlkem_clk_clk_pll 16.401 0.000 0 108 mlkem_clk_clk_pll sys_clk 16.929 0.000 0 59 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- **async_default** cpu_clk cpu_clk 26.418 0.000 0 67 **async_default** mlkem_clk_clk_pll mlkem_clk_clk_pll 28.755 0.000 0 25322 **async_default** sys_clk mlkem_clk_clk_pll 8.522 0.000 0 4 **async_default** mlkem_clk_clk_pll sys_clk 16.719 0.000 0 2 **async_default** sys_clk sys_clk 5.353 0.000 0 886 ------------------------------------------------------------------------------------------------ | User Ignored Path Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) sys_clk cpu_clk (none) cpu_clk sys_clk ------------------------------------------------------------------------------------------------ | Unconstrained Path Table | ------------------------ ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) clkfbout_clk_pll (none) sys_clk (none) sys_clk ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk To Clock: clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { clk } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_pll To Clock: clkfbout_clk_pll Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_pll Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y19 pll_clk.u_clk_pll/inst/clkf_buf/I Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT --------------------------------------------------------------------------------------------------- From Clock: cpu_clk To Clock: cpu_clk Setup : 0 Failing Endpoints, Worst Slack 1.137ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.137ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.134ns (logic 7.449ns (25.568%) route 21.685ns (74.432%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.807 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 1.102 24.909 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 SLICE_X36Y20 LUT6 (Prop_lut6_I5_O) 0.124 25.033 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/O net (fo=1, routed) 0.905 25.938 u_cpu/id_stage/ds_to_es_bus_r[181]_i_9_n_0 SLICE_X36Y25 LUT6 (Prop_lut6_I1_O) 0.124 26.062 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.733 26.795 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.919 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 26.919 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.973 28.467 u_cpu/exe_stage/cpu_clk SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/C clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.081 28.056 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 28.056 arrival time -26.919 ------------------------------------------------------------------- slack 1.137 Slack (MET) : 1.177ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.090ns (logic 7.677ns (26.391%) route 21.413ns (73.609%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.999 24.832 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y29 LUT6 (Prop_lut6_I3_O) 0.326 25.158 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/O net (fo=1, routed) 0.808 25.966 u_cpu/id_stage/ds_to_es_bus_r[178]_i_8_n_0 SLICE_X36Y27 LUT6 (Prop_lut6_I0_O) 0.124 26.090 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O net (fo=1, routed) 0.661 26.751 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.875 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O net (fo=1, routed) 0.000 26.875 u_cpu/exe_stage/ds_to_es_bus[128] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.973 28.467 u_cpu/exe_stage/cpu_clk SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/C clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.077 28.052 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- required time 28.052 arrival time -26.875 ------------------------------------------------------------------- slack 1.177 Slack (MET) : 1.295ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.920ns (logic 7.677ns (26.546%) route 21.243ns (73.454%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.427 23.040 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 LUT6 (Prop_lut6_I2_O) 0.124 23.164 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O net (fo=32, routed) 1.340 24.504 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 SLICE_X43Y25 LUT2 (Prop_lut2_I1_O) 0.150 24.654 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O net (fo=1, routed) 0.801 25.454 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 SLICE_X39Y25 LUT6 (Prop_lut6_I2_O) 0.326 25.780 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O net (fo=1, routed) 0.801 26.581 u_cpu/id_stage/ds_to_es_bus_r_reg[184] SLICE_X38Y27 LUT6 (Prop_lut6_I3_O) 0.124 26.705 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O net (fo=1, routed) 0.000 26.705 u_cpu/exe_stage/ds_to_es_bus[134] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.967 28.461 u_cpu/exe_stage/cpu_clk SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/C clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- required time 28.000 arrival time -26.705 ------------------------------------------------------------------- slack 1.295 Slack (MET) : 1.353ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.912ns (logic 7.677ns (26.553%) route 21.235ns (73.447%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.826 24.658 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X34Y28 LUT4 (Prop_lut4_I0_O) 0.326 24.984 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/O net (fo=1, routed) 0.646 25.631 u_cpu/id_stage/ds_to_es_bus_r[176]_i_8_n_0 SLICE_X34Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.755 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/O net (fo=1, routed) 0.819 26.574 u_cpu/id_stage/ds_to_es_bus_r[176]_i_3_n_0 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.698 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O net (fo=1, routed) 0.000 26.698 u_cpu/exe_stage/ds_to_es_bus[126] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.968 28.462 u_cpu/exe_stage/cpu_clk SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/C clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.081 28.051 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- required time 28.051 arrival time -26.698 ------------------------------------------------------------------- slack 1.353 Slack (MET) : 1.368ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.849ns (logic 7.449ns (25.820%) route 21.400ns (74.179%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.702 23.314 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 LUT6 (Prop_lut6_I0_O) 0.124 23.438 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 1.412 24.851 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X40Y22 LUT5 (Prop_lut5_I0_O) 0.124 24.975 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O net (fo=1, routed) 0.795 25.770 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 SLICE_X37Y24 LUT5 (Prop_lut5_I0_O) 0.124 25.894 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O net (fo=1, routed) 0.617 26.511 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 SLICE_X35Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.635 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O net (fo=1, routed) 0.000 26.635 u_cpu/exe_stage/ds_to_es_bus[125] SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.972 28.466 u_cpu/exe_stage/cpu_clk SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/C clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- required time 28.003 arrival time -26.635 ------------------------------------------------------------------- slack 1.368 Slack (MET) : 1.427ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.841ns (logic 7.677ns (26.618%) route 21.164ns (73.382%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.868 23.481 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X31Y26 LUT5 (Prop_lut5_I2_O) 0.150 23.631 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.824 24.455 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X33Y28 LUT6 (Prop_lut6_I0_O) 0.326 24.781 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O net (fo=1, routed) 0.845 25.625 u_cpu/id_stage/ds_to_es_bus_r_reg[190] SLICE_X33Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.749 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.754 26.503 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X36Y27 LUT5 (Prop_lut5_I1_O) 0.124 26.627 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 26.627 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X36Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.971 28.465 u_cpu/exe_stage/cpu_clk SLICE_X36Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/C clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y27 FDRE (Setup_fdre_C_D) 0.081 28.054 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 28.054 arrival time -26.627 ------------------------------------------------------------------- slack 1.427 Slack (MET) : 1.449ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.813ns (logic 7.677ns (26.645%) route 21.136ns (73.355%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.933 24.766 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y27 LUT6 (Prop_lut6_I0_O) 0.326 25.092 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/O net (fo=1, routed) 0.616 25.708 u_cpu/id_stage/ds_to_es_bus_r[174]_i_7_n_0 SLICE_X37Y25 LUT5 (Prop_lut5_I0_O) 0.124 25.832 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/O net (fo=1, routed) 0.642 26.474 u_cpu/id_stage/ds_to_es_bus_r[174]_i_3_n_0 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.598 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O net (fo=1, routed) 0.000 26.598 u_cpu/exe_stage/ds_to_es_bus[124] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.968 28.462 u_cpu/exe_stage/cpu_clk SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/C clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.077 28.047 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- required time 28.047 arrival time -26.598 ------------------------------------------------------------------- slack 1.449 Slack (MET) : 1.471ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.743ns (logic 7.677ns (26.709%) route 21.066ns (73.291%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.700 24.533 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y28 LUT4 (Prop_lut4_I2_O) 0.326 24.859 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/O net (fo=1, routed) 0.634 25.494 u_cpu/id_stage/ds_to_es_bus_r[187]_i_12_n_0 SLICE_X37Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.618 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O net (fo=1, routed) 0.787 26.405 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 SLICE_X38Y27 LUT6 (Prop_lut6_I4_O) 0.124 26.529 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 26.529 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.967 28.461 u_cpu/exe_stage/cpu_clk SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/C clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 28.000 arrival time -26.529 ------------------------------------------------------------------- slack 1.471 Slack (MET) : 1.527ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.688ns (logic 7.449ns (25.965%) route 21.239ns (74.035%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.062ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.430 23.043 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 LUT6 (Prop_lut6_I3_O) 0.124 23.167 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O net (fo=32, routed) 1.573 24.740 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 SLICE_X43Y25 LUT4 (Prop_lut4_I2_O) 0.124 24.864 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O net (fo=1, routed) 0.723 25.588 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 SLICE_X39Y25 LUT6 (Prop_lut6_I1_O) 0.124 25.712 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O net (fo=1, routed) 0.638 26.350 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 SLICE_X34Y25 LUT6 (Prop_lut6_I4_O) 0.124 26.474 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 26.474 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.970 28.464 u_cpu/exe_stage/cpu_clk SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/C clock pessimism -0.418 28.046 clock uncertainty -0.074 27.972 SLICE_X34Y25 FDRE (Setup_fdre_C_D) 0.029 28.001 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 28.001 arrival time -26.474 ------------------------------------------------------------------- slack 1.527 Slack (MET) : 1.551ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.666ns (logic 7.449ns (25.985%) route 21.217ns (74.015%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.571 23.184 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y21 LUT6 (Prop_lut6_I2_O) 0.124 23.308 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 1.092 24.400 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_0 SLICE_X38Y25 LUT2 (Prop_lut2_I1_O) 0.124 24.524 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/O net (fo=1, routed) 0.984 25.508 u_cpu/u_csr/ds_to_es_bus_r[165]_i_13_n_0 SLICE_X35Y26 LUT6 (Prop_lut6_I5_O) 0.124 25.632 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O net (fo=1, routed) 0.695 26.328 u_cpu/id_stage/ds_to_es_bus_r_reg[165] SLICE_X34Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.452 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 26.452 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.972 28.466 u_cpu/exe_stage/cpu_clk SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/C clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X34Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 28.003 arrival time -26.452 ------------------------------------------------------------------- slack 1.551 Slack (MET) : 1.609ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.609ns (logic 7.449ns (26.037%) route 21.160ns (73.963%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=7 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.571 23.184 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y21 LUT6 (Prop_lut6_I2_O) 0.124 23.308 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 1.211 24.519 u_cpu/id_stage/fs_to_ds_bus_r_reg[46]_1 SLICE_X43Y31 LUT4 (Prop_lut4_I2_O) 0.124 24.643 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_11/O net (fo=1, routed) 0.524 25.168 u_cpu/id_stage/ds_to_es_bus_r[185]_i_11_n_0 SLICE_X41Y30 LUT5 (Prop_lut5_I4_O) 0.124 25.292 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_5/O net (fo=1, routed) 0.979 26.271 u_cpu/id_stage/ds_to_es_bus_r[185]_i_5_n_0 SLICE_X37Y28 LUT6 (Prop_lut6_I4_O) 0.124 26.395 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O net (fo=1, routed) 0.000 26.395 u_cpu/exe_stage/ds_to_es_bus[135] SLICE_X37Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.973 28.467 u_cpu/exe_stage/cpu_clk SLICE_X37Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/C clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X37Y28 FDRE (Setup_fdre_C_D) 0.029 28.004 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] ------------------------------------------------------------------- required time 28.004 arrival time -26.395 ------------------------------------------------------------------- slack 1.609 Slack (MET) : 1.609ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.655ns (logic 7.449ns (25.995%) route 21.206ns (74.005%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.529 23.141 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X29Y23 LUT6 (Prop_lut6_I2_O) 0.124 23.265 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.733 23.998 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X32Y25 LUT6 (Prop_lut6_I1_O) 0.124 24.122 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O net (fo=29, routed) 1.300 25.422 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_2 SLICE_X40Y22 LUT5 (Prop_lut5_I3_O) 0.124 25.546 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O net (fo=1, routed) 0.771 26.317 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 SLICE_X36Y27 LUT6 (Prop_lut6_I3_O) 0.124 26.441 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O net (fo=1, routed) 0.000 26.441 u_cpu/exe_stage/ds_to_es_bus[127] SLICE_X36Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.971 28.465 u_cpu/exe_stage/cpu_clk SLICE_X36Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/C clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y27 FDRE (Setup_fdre_C_D) 0.077 28.050 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] ------------------------------------------------------------------- required time 28.050 arrival time -26.441 ------------------------------------------------------------------- slack 1.609 Slack (MET) : 1.614ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.604ns (logic 7.681ns (26.853%) route 20.923ns (73.147%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.062ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.529 23.141 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X29Y23 LUT6 (Prop_lut6_I2_O) 0.124 23.265 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.685 23.950 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X27Y23 LUT6 (Prop_lut6_I0_O) 0.124 24.074 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 0.708 24.782 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 SLICE_X26Y25 LUT2 (Prop_lut2_I1_O) 0.153 24.935 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O net (fo=1, routed) 1.127 26.062 u_cpu/id_stage/ds_to_es_bus_r_reg[171] SLICE_X34Y25 LUT6 (Prop_lut6_I2_O) 0.327 26.389 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O net (fo=1, routed) 0.000 26.389 u_cpu/exe_stage/ds_to_es_bus[121] SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.970 28.464 u_cpu/exe_stage/cpu_clk SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/C clock pessimism -0.418 28.046 clock uncertainty -0.074 27.972 SLICE_X34Y25 FDRE (Setup_fdre_C_D) 0.031 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] ------------------------------------------------------------------- required time 28.003 arrival time -26.389 ------------------------------------------------------------------- slack 1.614 Slack (MET) : 1.660ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.553ns (logic 7.449ns (26.088%) route 21.104ns (73.912%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.702 23.314 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 LUT6 (Prop_lut6_I0_O) 0.124 23.438 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 0.856 24.294 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X38Y18 LUT4 (Prop_lut4_I0_O) 0.124 24.418 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_12/O net (fo=1, routed) 0.631 25.049 u_cpu/id_stage/ds_to_es_bus_r[180]_i_12_n_0 SLICE_X38Y21 LUT6 (Prop_lut6_I5_O) 0.124 25.173 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_3/O net (fo=1, routed) 1.041 26.214 u_cpu/id_stage/ds_to_es_bus_r[180]_i_3_n_0 SLICE_X38Y27 LUT6 (Prop_lut6_I2_O) 0.124 26.338 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/O net (fo=1, routed) 0.000 26.338 u_cpu/exe_stage/ds_to_es_bus[130] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.967 28.461 u_cpu/exe_stage/cpu_clk SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/C clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.029 27.998 u_cpu/exe_stage/ds_to_es_bus_r_reg[180] ------------------------------------------------------------------- required time 27.998 arrival time -26.338 ------------------------------------------------------------------- slack 1.660 Slack (MET) : 1.670ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.541ns (logic 7.652ns (26.811%) route 20.889ns (73.189%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=7 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.807 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 0.545 24.352 u_cpu/u_csr/ds_to_es_bus_r[166]_i_4_0 SLICE_X32Y24 LUT2 (Prop_lut2_I1_O) 0.119 24.471 r u_cpu/u_csr/ds_to_es_bus_r[166]_i_8/O net (fo=1, routed) 0.978 25.449 u_cpu/u_csr/ds_to_es_bus_r[166]_i_8_n_0 SLICE_X36Y23 LUT6 (Prop_lut6_I0_O) 0.332 25.781 r u_cpu/u_csr/ds_to_es_bus_r[166]_i_4/O net (fo=1, routed) 0.422 26.202 u_cpu/id_stage/ds_to_es_bus_r_reg[166] SLICE_X38Y23 LUT6 (Prop_lut6_I3_O) 0.124 26.326 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_1/O net (fo=1, routed) 0.000 26.326 u_cpu/exe_stage/ds_to_es_bus[116] SLICE_X38Y23 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.966 28.460 u_cpu/exe_stage/cpu_clk SLICE_X38Y23 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/C clock pessimism -0.418 28.042 clock uncertainty -0.074 27.968 SLICE_X38Y23 FDRE (Setup_fdre_C_D) 0.029 27.997 u_cpu/exe_stage/ds_to_es_bus_r_reg[166] ------------------------------------------------------------------- required time 27.997 arrival time -26.326 ------------------------------------------------------------------- slack 1.670 Slack (MET) : 1.673ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.595ns (logic 7.449ns (26.050%) route 21.146ns (73.950%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=6 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.702 23.314 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 LUT6 (Prop_lut6_I0_O) 0.124 23.438 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 0.987 24.426 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X39Y20 LUT6 (Prop_lut6_I3_O) 0.124 24.550 r u_cpu/id_stage/ds_to_es_bus_r[183]_i_13/O net (fo=1, routed) 0.557 25.107 u_cpu/id_stage/ds_to_es_bus_r[183]_i_13_n_0 SLICE_X38Y22 LUT6 (Prop_lut6_I5_O) 0.124 25.231 r u_cpu/id_stage/ds_to_es_bus_r[183]_i_3/O net (fo=1, routed) 1.026 26.257 u_cpu/id_stage/ds_to_es_bus_r[183]_i_3_n_0 SLICE_X36Y28 LUT6 (Prop_lut6_I2_O) 0.124 26.381 r u_cpu/id_stage/ds_to_es_bus_r[183]_i_1/O net (fo=1, routed) 0.000 26.381 u_cpu/exe_stage/ds_to_es_bus[133] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.973 28.467 u_cpu/exe_stage/cpu_clk SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/C clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.079 28.054 u_cpu/exe_stage/ds_to_es_bus_r_reg[183] ------------------------------------------------------------------- required time 28.054 arrival time -26.381 ------------------------------------------------------------------- slack 1.673 Slack (MET) : 1.687ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.533ns (logic 7.449ns (26.107%) route 21.084ns (73.893%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=6 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.529 23.141 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X29Y23 LUT6 (Prop_lut6_I2_O) 0.124 23.265 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.685 23.950 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X27Y23 LUT6 (Prop_lut6_I0_O) 0.124 24.074 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 1.053 25.128 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 SLICE_X32Y23 LUT6 (Prop_lut6_I0_O) 0.124 25.252 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_2/O net (fo=1, routed) 0.943 26.194 u_cpu/id_stage/ds_to_es_bus_r[173]_i_2_n_0 SLICE_X34Y26 LUT6 (Prop_lut6_I1_O) 0.124 26.318 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_1/O net (fo=1, routed) 0.000 26.318 u_cpu/exe_stage/ds_to_es_bus[123] SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.972 28.466 u_cpu/exe_stage/cpu_clk SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/C clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X34Y26 FDRE (Setup_fdre_C_D) 0.031 28.005 u_cpu/exe_stage/ds_to_es_bus_r_reg[173] ------------------------------------------------------------------- required time 28.005 arrival time -26.318 ------------------------------------------------------------------- slack 1.687 Slack (MET) : 1.695ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.521ns (logic 7.677ns (26.917%) route 20.844ns (73.083%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=7 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.063ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.860ns = ( 28.463 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.860 24.693 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y29 LUT4 (Prop_lut4_I2_O) 0.326 25.019 r u_cpu/id_stage/ds_to_es_bus_r[191]_i_8/O net (fo=1, routed) 0.473 25.492 u_cpu/id_stage/ds_to_es_bus_r[191]_i_8_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.616 r u_cpu/id_stage/ds_to_es_bus_r[191]_i_2/O net (fo=1, routed) 0.567 26.183 u_cpu/id_stage/ds_to_es_bus_r[191]_i_2_n_0 SLICE_X38Y28 LUT6 (Prop_lut6_I1_O) 0.124 26.307 r u_cpu/id_stage/ds_to_es_bus_r[191]_i_1/O net (fo=1, routed) 0.000 26.307 u_cpu/exe_stage/ds_to_es_bus[141] SLICE_X38Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.969 28.463 u_cpu/exe_stage/cpu_clk SLICE_X38Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/C clock pessimism -0.418 28.045 clock uncertainty -0.074 27.971 SLICE_X38Y28 FDRE (Setup_fdre_C_D) 0.031 28.002 u_cpu/exe_stage/ds_to_es_bus_r_reg[191] ------------------------------------------------------------------- required time 28.002 arrival time -26.307 ------------------------------------------------------------------- slack 1.695 Slack (MET) : 1.719ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.546ns (logic 7.449ns (26.095%) route 21.097ns (73.905%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=7 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.807 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 0.809 24.616 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 SLICE_X36Y26 LUT4 (Prop_lut4_I2_O) 0.124 24.740 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_8/O net (fo=1, routed) 0.749 25.489 u_cpu/id_stage/ds_to_es_bus_r[163]_i_8_n_0 SLICE_X36Y20 LUT6 (Prop_lut6_I0_O) 0.124 25.613 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_4/O net (fo=1, routed) 0.594 26.207 u_cpu/id_stage/ds_to_es_bus_r[163]_i_4_n_0 SLICE_X36Y22 LUT6 (Prop_lut6_I3_O) 0.124 26.331 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_1/O net (fo=1, routed) 0.000 26.331 u_cpu/exe_stage/ds_to_es_bus[113] SLICE_X36Y22 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.971 28.465 u_cpu/exe_stage/cpu_clk SLICE_X36Y22 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/C clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y22 FDRE (Setup_fdre_C_D) 0.077 28.050 u_cpu/exe_stage/ds_to_es_bus_r_reg[163] ------------------------------------------------------------------- required time 28.050 arrival time -26.331 ------------------------------------------------------------------- slack 1.719 Slack (MET) : 1.727ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.495ns (logic 7.677ns (26.942%) route 20.818ns (73.058%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.853ns = ( 28.470 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.957 24.790 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X35Y29 LUT6 (Prop_lut6_I3_O) 0.326 25.116 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_11/O net (fo=1, routed) 0.423 25.539 u_cpu/id_stage/ds_to_es_bus_r[188]_i_11_n_0 SLICE_X34Y27 LUT6 (Prop_lut6_I0_O) 0.124 25.663 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_5/O net (fo=1, routed) 0.493 26.156 u_cpu/id_stage/ds_to_es_bus_r[188]_i_5_n_0 SLICE_X34Y29 LUT6 (Prop_lut6_I4_O) 0.124 26.280 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_1/O net (fo=1, routed) 0.000 26.280 u_cpu/exe_stage/ds_to_es_bus[138] SLICE_X34Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.976 28.470 u_cpu/exe_stage/cpu_clk SLICE_X34Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/C clock pessimism -0.418 28.052 clock uncertainty -0.074 27.978 SLICE_X34Y29 FDRE (Setup_fdre_C_D) 0.029 28.007 u_cpu/exe_stage/ds_to_es_bus_r_reg[188] ------------------------------------------------------------------- required time 28.007 arrival time -26.280 ------------------------------------------------------------------- slack 1.727 Slack (MET) : 1.778ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.489ns (logic 7.449ns (26.147%) route 21.040ns (73.853%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=6 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.855ns = ( 28.468 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.529 23.141 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X29Y23 LUT6 (Prop_lut6_I2_O) 0.124 23.265 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.733 23.998 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X32Y25 LUT6 (Prop_lut6_I1_O) 0.124 24.122 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O net (fo=29, routed) 1.221 25.343 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_2 SLICE_X38Y20 LUT6 (Prop_lut6_I3_O) 0.124 25.467 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_5/O net (fo=1, routed) 0.683 26.151 u_cpu/id_stage/ds_to_es_bus_r[168]_i_5_n_0 SLICE_X36Y19 LUT6 (Prop_lut6_I4_O) 0.124 26.275 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O net (fo=1, routed) 0.000 26.275 u_cpu/exe_stage/ds_to_es_bus[118] SLICE_X36Y19 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.974 28.468 u_cpu/exe_stage/cpu_clk SLICE_X36Y19 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/C clock pessimism -0.418 28.050 clock uncertainty -0.074 27.976 SLICE_X36Y19 FDRE (Setup_fdre_C_D) 0.077 28.053 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] ------------------------------------------------------------------- required time 28.053 arrival time -26.275 ------------------------------------------------------------------- slack 1.778 Slack (MET) : 1.784ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.434ns (logic 7.449ns (26.198%) route 20.985ns (73.802%)) Logic Levels: 32 (CARRY4=5 LUT3=2 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.062ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.529 23.141 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X29Y23 LUT6 (Prop_lut6_I2_O) 0.124 23.265 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.733 23.998 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X32Y25 LUT6 (Prop_lut6_I1_O) 0.124 24.122 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O net (fo=29, routed) 0.959 25.081 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_2 SLICE_X34Y20 LUT3 (Prop_lut3_I0_O) 0.124 25.205 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_4/O net (fo=1, routed) 0.890 26.095 u_cpu/id_stage/ds_to_es_bus_r[170]_i_4_n_0 SLICE_X34Y25 LUT6 (Prop_lut6_I3_O) 0.124 26.219 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O net (fo=1, routed) 0.000 26.219 u_cpu/exe_stage/ds_to_es_bus[120] SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.970 28.464 u_cpu/exe_stage/cpu_clk SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/C clock pessimism -0.418 28.046 clock uncertainty -0.074 27.972 SLICE_X34Y25 FDRE (Setup_fdre_C_D) 0.031 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] ------------------------------------------------------------------- required time 28.003 arrival time -26.219 ------------------------------------------------------------------- slack 1.784 Slack (MET) : 1.795ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.426ns (logic 7.449ns (26.205%) route 20.977ns (73.795%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=7 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.571 23.184 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y21 LUT6 (Prop_lut6_I2_O) 0.124 23.308 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 1.158 24.466 u_cpu/id_stage/fs_to_ds_bus_r_reg[46]_1 SLICE_X41Y31 LUT4 (Prop_lut4_I0_O) 0.124 24.590 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_12/O net (fo=1, routed) 0.631 25.221 u_cpu/id_stage/ds_to_es_bus_r[186]_i_12_n_0 SLICE_X39Y26 LUT5 (Prop_lut5_I0_O) 0.124 25.345 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_5/O net (fo=1, routed) 0.742 26.087 u_cpu/id_stage/ds_to_es_bus_r[186]_i_5_n_0 SLICE_X34Y26 LUT6 (Prop_lut6_I4_O) 0.124 26.211 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O net (fo=1, routed) 0.000 26.211 u_cpu/exe_stage/ds_to_es_bus[136] SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.972 28.466 u_cpu/exe_stage/cpu_clk SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/C clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X34Y26 FDRE (Setup_fdre_C_D) 0.032 28.006 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] ------------------------------------------------------------------- required time 28.006 arrival time -26.211 ------------------------------------------------------------------- slack 1.795 Slack (MET) : 1.806ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.409ns (logic 7.449ns (26.221%) route 20.960ns (73.779%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.063ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.860ns = ( 28.463 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.807 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 0.673 24.480 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 SLICE_X35Y23 LUT6 (Prop_lut6_I0_O) 0.124 24.604 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_8/O net (fo=1, routed) 1.180 25.784 u_cpu/id_stage/ds_to_es_bus_r[179]_i_8_n_0 SLICE_X38Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.908 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_3/O net (fo=1, routed) 0.162 26.070 u_cpu/id_stage/ds_to_es_bus_r[179]_i_3_n_0 SLICE_X38Y28 LUT5 (Prop_lut5_I2_O) 0.124 26.194 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_1/O net (fo=1, routed) 0.000 26.194 u_cpu/exe_stage/ds_to_es_bus[129] SLICE_X38Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.969 28.463 u_cpu/exe_stage/cpu_clk SLICE_X38Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/C clock pessimism -0.418 28.045 clock uncertainty -0.074 27.971 SLICE_X38Y28 FDRE (Setup_fdre_C_D) 0.029 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[179] ------------------------------------------------------------------- required time 28.000 arrival time -26.194 ------------------------------------------------------------------- slack 1.806 Slack (MET) : 1.812ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.454ns (logic 7.449ns (26.179%) route 21.005ns (73.821%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=7 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.713 23.326 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 LUT6 (Prop_lut6_I4_O) 0.124 23.450 f u_cpu/id_stage/ds_to_es_bus_r[166]_i_12/O net (fo=9, routed) 0.990 24.439 u_cpu/id_stage/ds_to_es_bus_r[166]_i_12_n_0 SLICE_X36Y21 LUT4 (Prop_lut4_I2_O) 0.124 24.563 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_9/O net (fo=1, routed) 0.632 25.196 u_cpu/id_stage/ds_to_es_bus_r[169]_i_9_n_0 SLICE_X36Y23 LUT5 (Prop_lut5_I4_O) 0.124 25.320 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_5/O net (fo=1, routed) 0.796 26.116 u_cpu/id_stage/ds_to_es_bus_r[169]_i_5_n_0 SLICE_X36Y22 LUT6 (Prop_lut6_I4_O) 0.124 26.240 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_1/O net (fo=1, routed) 0.000 26.240 u_cpu/exe_stage/ds_to_es_bus[119] SLICE_X36Y22 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.971 28.465 u_cpu/exe_stage/cpu_clk SLICE_X36Y22 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/C clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y22 FDRE (Setup_fdre_C_D) 0.079 28.052 u_cpu/exe_stage/ds_to_es_bus_r_reg[169] ------------------------------------------------------------------- required time 28.052 arrival time -26.240 ------------------------------------------------------------------- slack 1.812 Slack (MET) : 1.813ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.402ns (logic 7.449ns (26.227%) route 20.953ns (73.773%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.702 23.315 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X31Y20 LUT6 (Prop_lut6_I1_O) 0.124 23.439 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O net (fo=32, routed) 1.157 24.595 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 SLICE_X34Y28 LUT4 (Prop_lut4_I0_O) 0.124 24.719 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_8/O net (fo=1, routed) 0.656 25.375 u_cpu/id_stage/ds_to_es_bus_r[193]_i_8_n_0 SLICE_X35Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.499 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O net (fo=1, routed) 0.565 26.064 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 SLICE_X38Y27 LUT6 (Prop_lut6_I1_O) 0.124 26.188 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O net (fo=1, routed) 0.000 26.188 u_cpu/exe_stage/ds_to_es_bus[143] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.967 28.461 u_cpu/exe_stage/cpu_clk SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/C clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.032 28.001 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] ------------------------------------------------------------------- required time 28.001 arrival time -26.188 ------------------------------------------------------------------- slack 1.813 Slack (MET) : 1.829ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.439ns (logic 7.449ns (26.193%) route 20.990ns (73.807%)) Logic Levels: 32 (CARRY4=5 LUT3=2 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.529 23.141 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X29Y23 LUT6 (Prop_lut6_I2_O) 0.124 23.265 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.059 24.325 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X31Y21 LUT3 (Prop_lut3_I1_O) 0.124 24.449 f u_cpu/id_stage/ds_to_es_bus_r[164]_i_17/O net (fo=3, routed) 0.867 25.316 u_cpu/id_stage/ds_to_es_bus_r[164]_i_17_n_0 SLICE_X36Y23 LUT6 (Prop_lut6_I3_O) 0.124 25.440 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_5/O net (fo=1, routed) 0.660 26.101 u_cpu/id_stage/ds_to_es_bus_r[164]_i_5_n_0 SLICE_X36Y22 LUT6 (Prop_lut6_I4_O) 0.124 26.225 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O net (fo=1, routed) 0.000 26.225 u_cpu/exe_stage/ds_to_es_bus[114] SLICE_X36Y22 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.971 28.465 u_cpu/exe_stage/cpu_clk SLICE_X36Y22 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/C clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y22 FDRE (Setup_fdre_C_D) 0.081 28.054 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] ------------------------------------------------------------------- required time 28.054 arrival time -26.225 ------------------------------------------------------------------- slack 1.829 Slack (MET) : 1.830ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.389ns (logic 7.679ns (27.049%) route 20.710ns (72.951%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.529 23.141 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X29Y23 LUT6 (Prop_lut6_I2_O) 0.124 23.265 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.406 23.671 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X27Y23 LUT6 (Prop_lut6_I0_O) 0.124 23.795 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O net (fo=22, routed) 1.142 24.937 u_cpu/u_csr/ds_to_es_bus_r_reg[172] SLICE_X33Y26 LUT2 (Prop_lut2_I1_O) 0.152 25.089 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O net (fo=1, routed) 0.760 25.849 u_cpu/id_stage/ds_to_es_bus_r_reg[172] SLICE_X34Y26 LUT6 (Prop_lut6_I2_O) 0.326 26.175 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O net (fo=1, routed) 0.000 26.175 u_cpu/exe_stage/ds_to_es_bus[122] SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.972 28.466 u_cpu/exe_stage/cpu_clk SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/C clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X34Y26 FDRE (Setup_fdre_C_D) 0.031 28.005 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] ------------------------------------------------------------------- required time 28.005 arrival time -26.175 ------------------------------------------------------------------- slack 1.830 Slack (MET) : 1.896ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.324ns (logic 7.521ns (26.554%) route 20.803ns (73.446%)) Logic Levels: 31 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.592 22.758 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X29Y20 LUT5 (Prop_lut5_I2_O) 0.124 22.882 f u_cpu/id_stage/ds_to_es_bus_r[183]_i_15/O net (fo=8, routed) 0.740 23.622 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_1 SLICE_X34Y22 LUT2 (Prop_lut2_I1_O) 0.118 23.740 f u_cpu/id_stage/ds_to_es_bus_r[183]_i_12/O net (fo=6, routed) 1.050 24.790 u_cpu/id_stage/ds_to_es_bus_r[183]_i_12_n_0 SLICE_X38Y21 LUT6 (Prop_lut6_I3_O) 0.326 25.116 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_3/O net (fo=1, routed) 0.869 25.985 u_cpu/id_stage/ds_to_es_bus_r[182]_i_3_n_0 SLICE_X35Y26 LUT6 (Prop_lut6_I2_O) 0.124 26.109 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_1/O net (fo=1, routed) 0.000 26.109 u_cpu/exe_stage/ds_to_es_bus[132] SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.972 28.466 u_cpu/exe_stage/cpu_clk SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/C clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.031 28.005 u_cpu/exe_stage/ds_to_es_bus_r_reg[182] ------------------------------------------------------------------- required time 28.005 arrival time -26.109 ------------------------------------------------------------------- slack 1.896 Slack (MET) : 1.899ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.322ns (logic 7.449ns (26.301%) route 20.873ns (73.699%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.853ns = ( 28.470 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.427 23.040 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 LUT6 (Prop_lut6_I2_O) 0.124 23.164 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O net (fo=32, routed) 1.034 24.198 u_cpu/id_stage/fs_to_ds_bus_r_reg[46]_0 SLICE_X39Y25 LUT4 (Prop_lut4_I2_O) 0.124 24.322 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_13/O net (fo=1, routed) 0.835 25.157 u_cpu/id_stage/ds_to_es_bus_r[189]_i_13_n_0 SLICE_X38Y24 LUT6 (Prop_lut6_I5_O) 0.124 25.281 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_4/O net (fo=1, routed) 0.702 25.983 u_cpu/id_stage/ds_to_es_bus_r[189]_i_4_n_0 SLICE_X30Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.107 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O net (fo=1, routed) 0.000 26.107 u_cpu/exe_stage/ds_to_es_bus[139] SLICE_X30Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.976 28.470 u_cpu/exe_stage/cpu_clk SLICE_X30Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/C clock pessimism -0.418 28.052 clock uncertainty -0.074 27.978 SLICE_X30Y28 FDRE (Setup_fdre_C_D) 0.029 28.007 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] ------------------------------------------------------------------- required time 28.007 arrival time -26.108 ------------------------------------------------------------------- slack 1.899 Slack (MET) : 1.961ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.261ns (logic 7.449ns (26.358%) route 20.812ns (73.642%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.852ns = ( 28.471 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.713 23.326 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 LUT6 (Prop_lut6_I4_O) 0.124 23.450 f u_cpu/id_stage/ds_to_es_bus_r[166]_i_12/O net (fo=9, routed) 0.814 24.263 u_cpu/id_stage/ds_to_es_bus_r[166]_i_12_n_0 SLICE_X32Y24 LUT4 (Prop_lut4_I0_O) 0.124 24.387 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_9/O net (fo=1, routed) 0.949 25.337 u_cpu/id_stage/ds_to_es_bus_r[162]_i_9_n_0 SLICE_X32Y21 LUT6 (Prop_lut6_I2_O) 0.124 25.461 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_4/O net (fo=1, routed) 0.462 25.923 u_cpu/id_stage/ds_to_es_bus_r[162]_i_4_n_0 SLICE_X31Y19 LUT6 (Prop_lut6_I2_O) 0.124 26.047 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_1/O net (fo=1, routed) 0.000 26.047 u_cpu/exe_stage/ds_to_es_bus[112] SLICE_X31Y19 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.977 28.471 u_cpu/exe_stage/cpu_clk SLICE_X31Y19 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/C clock pessimism -0.418 28.053 clock uncertainty -0.074 27.979 SLICE_X31Y19 FDRE (Setup_fdre_C_D) 0.029 28.008 u_cpu/exe_stage/ds_to_es_bus_r_reg[162] ------------------------------------------------------------------- required time 28.008 arrival time -26.047 ------------------------------------------------------------------- slack 1.961 Slack (MET) : 2.191ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.029ns (logic 7.325ns (26.134%) route 20.704ns (73.866%)) Logic Levels: 31 (CARRY4=5 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.881 23.047 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X28Y19 LUT6 (Prop_lut6_I5_O) 0.124 23.171 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_10/O net (fo=26, routed) 0.687 23.858 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_3 SLICE_X30Y23 LUT6 (Prop_lut6_I0_O) 0.124 23.982 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_11/O net (fo=1, routed) 0.697 24.679 u_cpu/id_stage/ds_to_es_bus_r[192]_i_11_n_0 SLICE_X37Y23 LUT6 (Prop_lut6_I5_O) 0.124 24.803 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_4/O net (fo=1, routed) 0.887 25.690 u_cpu/id_stage/ds_to_es_bus_r[192]_i_4_n_0 SLICE_X37Y28 LUT6 (Prop_lut6_I3_O) 0.124 25.814 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_1/O net (fo=1, routed) 0.000 25.814 u_cpu/exe_stage/ds_to_es_bus[142] SLICE_X37Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.973 28.467 u_cpu/exe_stage/cpu_clk SLICE_X37Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/C clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X37Y28 FDRE (Setup_fdre_C_D) 0.031 28.006 u_cpu/exe_stage/ds_to_es_bus_r_reg[192] ------------------------------------------------------------------- required time 28.006 arrival time -25.815 ------------------------------------------------------------------- slack 2.191 Slack (MET) : 2.599ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[4][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.592ns (logic 6.322ns (22.913%) route 21.270ns (77.087%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns = ( 28.391 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 1.153 23.344 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X48Y2 LUT6 (Prop_lut6_I0_O) 0.124 23.469 r u_cpu/id_stage/btb_counter[4][1]_i_4/O net (fo=2, routed) 0.639 24.108 u_cpu/btb/btb_counter_reg[4][1]_0 SLICE_X47Y3 LUT3 (Prop_lut3_I1_O) 0.150 24.258 r u_cpu/btb/btb_counter[4][0]_i_2/O net (fo=1, routed) 0.793 25.051 u_cpu/btb/btb_counter[4][0]_i_2_n_0 SLICE_X48Y2 LUT6 (Prop_lut6_I0_O) 0.326 25.377 r u_cpu/btb/btb_counter[4][0]_i_1/O net (fo=1, routed) 0.000 25.377 u_cpu/btb/btb_counter[4][0]_i_1_n_0 SLICE_X48Y2 FDRE r u_cpu/btb/btb_counter_reg[4][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.897 28.391 u_cpu/btb/cpu_clk SLICE_X48Y2 FDRE r u_cpu/btb/btb_counter_reg[4][0]/C clock pessimism -0.418 27.973 clock uncertainty -0.074 27.899 SLICE_X48Y2 FDRE (Setup_fdre_C_D) 0.077 27.976 u_cpu/btb/btb_counter_reg[4][0] ------------------------------------------------------------------- required time 27.976 arrival time -25.377 ------------------------------------------------------------------- slack 2.599 Slack (MET) : 2.682ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[6][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.463ns (logic 6.328ns (23.042%) route 21.135ns (76.958%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns = ( 28.391 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.979 23.171 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X45Y2 LUT6 (Prop_lut6_I0_O) 0.124 23.295 r u_cpu/id_stage/btb_counter[6][1]_i_4/O net (fo=2, routed) 0.659 23.954 u_cpu/btb/btb_counter_reg[6][1]_0 SLICE_X45Y2 LUT3 (Prop_lut3_I1_O) 0.150 24.104 r u_cpu/btb/btb_counter[6][1]_i_2/O net (fo=1, routed) 0.812 24.916 u_cpu/btb/btb_counter[6][1]_i_2_n_0 SLICE_X45Y2 LUT6 (Prop_lut6_I0_O) 0.332 25.248 r u_cpu/btb/btb_counter[6][1]_i_1/O net (fo=1, routed) 0.000 25.248 u_cpu/btb/btb_counter[6][1]_i_1_n_0 SLICE_X45Y2 FDRE r u_cpu/btb/btb_counter_reg[6][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.897 28.391 u_cpu/btb/cpu_clk SLICE_X45Y2 FDRE r u_cpu/btb/btb_counter_reg[6][1]/C clock pessimism -0.418 27.973 clock uncertainty -0.074 27.899 SLICE_X45Y2 FDRE (Setup_fdre_C_D) 0.031 27.930 u_cpu/btb/btb_counter_reg[6][1] ------------------------------------------------------------------- required time 27.930 arrival time -25.248 ------------------------------------------------------------------- slack 2.682 Slack (MET) : 2.912ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[4][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.280ns (logic 6.344ns (23.255%) route 20.936ns (76.745%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns = ( 28.391 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 1.153 23.344 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X48Y2 LUT6 (Prop_lut6_I0_O) 0.124 23.469 r u_cpu/id_stage/btb_counter[4][1]_i_4/O net (fo=2, routed) 0.745 24.214 u_cpu/btb/btb_counter_reg[4][1]_0 SLICE_X48Y1 LUT3 (Prop_lut3_I1_O) 0.150 24.364 r u_cpu/btb/btb_counter[4][1]_i_2/O net (fo=1, routed) 0.354 24.717 u_cpu/btb/btb_counter[4][1]_i_2_n_0 SLICE_X48Y1 LUT6 (Prop_lut6_I0_O) 0.348 25.065 r u_cpu/btb/btb_counter[4][1]_i_1/O net (fo=1, routed) 0.000 25.065 u_cpu/btb/btb_counter[4][1]_i_1_n_0 SLICE_X48Y1 FDRE r u_cpu/btb/btb_counter_reg[4][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.897 28.391 u_cpu/btb/cpu_clk SLICE_X48Y1 FDRE r u_cpu/btb/btb_counter_reg[4][1]/C clock pessimism -0.418 27.973 clock uncertainty -0.074 27.899 SLICE_X48Y1 FDRE (Setup_fdre_C_D) 0.079 27.978 u_cpu/btb/btb_counter_reg[4][1] ------------------------------------------------------------------- required time 27.978 arrival time -25.065 ------------------------------------------------------------------- slack 2.912 Slack (MET) : 2.989ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[5][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.155ns (logic 6.326ns (23.296%) route 20.829ns (76.704%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.933ns = ( 28.390 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.992 23.183 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X43Y4 LUT6 (Prop_lut6_I0_O) 0.124 23.307 r u_cpu/id_stage/btb_counter[5][1]_i_4/O net (fo=2, routed) 0.747 24.054 u_cpu/btb/btb_counter_reg[5][1]_0 SLICE_X47Y5 LUT3 (Prop_lut3_I1_O) 0.153 24.207 r u_cpu/btb/btb_counter[5][0]_i_2/O net (fo=1, routed) 0.407 24.614 u_cpu/btb/btb_counter[5][0]_i_2_n_0 SLICE_X47Y5 LUT6 (Prop_lut6_I0_O) 0.327 24.941 r u_cpu/btb/btb_counter[5][0]_i_1/O net (fo=1, routed) 0.000 24.941 u_cpu/btb/btb_counter[5][0]_i_1_n_0 SLICE_X47Y5 FDRE r u_cpu/btb/btb_counter_reg[5][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.896 28.390 u_cpu/btb/cpu_clk SLICE_X47Y5 FDRE r u_cpu/btb/btb_counter_reg[5][0]/C clock pessimism -0.418 27.972 clock uncertainty -0.074 27.898 SLICE_X47Y5 FDRE (Setup_fdre_C_D) 0.032 27.930 u_cpu/btb/btb_counter_reg[5][0] ------------------------------------------------------------------- required time 27.930 arrival time -24.941 ------------------------------------------------------------------- slack 2.989 Slack (MET) : 3.024ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[1][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.116ns (logic 6.094ns (22.474%) route 21.022ns (77.526%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.934ns = ( 28.389 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 1.117 23.308 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X49Y6 LUT6 (Prop_lut6_I0_O) 0.124 23.432 r u_cpu/id_stage/btb_counter[1][1]_i_4/O net (fo=2, routed) 0.587 24.020 u_cpu/btb/btb_counter_reg[1][1]_0 SLICE_X51Y3 LUT3 (Prop_lut3_I1_O) 0.124 24.144 r u_cpu/btb/btb_counter[1][0]_i_2/O net (fo=1, routed) 0.634 24.778 u_cpu/btb/btb_counter[1][0]_i_2_n_0 SLICE_X51Y2 LUT6 (Prop_lut6_I0_O) 0.124 24.902 r u_cpu/btb/btb_counter[1][0]_i_1/O net (fo=1, routed) 0.000 24.902 u_cpu/btb/btb_counter[1][0]_i_1_n_0 SLICE_X51Y2 FDRE r u_cpu/btb/btb_counter_reg[1][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.895 28.389 u_cpu/btb/cpu_clk SLICE_X51Y2 FDRE r u_cpu/btb/btb_counter_reg[1][0]/C clock pessimism -0.418 27.971 clock uncertainty -0.074 27.897 SLICE_X51Y2 FDRE (Setup_fdre_C_D) 0.029 27.926 u_cpu/btb/btb_counter_reg[1][0] ------------------------------------------------------------------- required time 27.926 arrival time -24.902 ------------------------------------------------------------------- slack 3.024 Slack (MET) : 3.052ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[1][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.090ns (logic 6.094ns (22.495%) route 20.996ns (77.505%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.934ns = ( 28.389 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 1.117 23.308 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X49Y6 LUT6 (Prop_lut6_I0_O) 0.124 23.432 r u_cpu/id_stage/btb_counter[1][1]_i_4/O net (fo=2, routed) 0.623 24.055 u_cpu/btb/btb_counter_reg[1][1]_0 SLICE_X49Y5 LUT3 (Prop_lut3_I1_O) 0.124 24.179 r u_cpu/btb/btb_counter[1][1]_i_2/O net (fo=1, routed) 0.573 24.752 u_cpu/btb/btb_counter[1][1]_i_2_n_0 SLICE_X51Y2 LUT6 (Prop_lut6_I0_O) 0.124 24.876 r u_cpu/btb/btb_counter[1][1]_i_1/O net (fo=1, routed) 0.000 24.876 u_cpu/btb/btb_counter[1][1]_i_1_n_0 SLICE_X51Y2 FDRE r u_cpu/btb/btb_counter_reg[1][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.895 28.389 u_cpu/btb/cpu_clk SLICE_X51Y2 FDRE r u_cpu/btb/btb_counter_reg[1][1]/C clock pessimism -0.418 27.971 clock uncertainty -0.074 27.897 SLICE_X51Y2 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/btb/btb_counter_reg[1][1] ------------------------------------------------------------------- required time 27.928 arrival time -24.876 ------------------------------------------------------------------- slack 3.052 Slack (MET) : 3.078ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[8][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.110ns (logic 6.344ns (23.401%) route 20.766ns (76.599%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.935ns = ( 28.388 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.991 23.182 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X43Y4 LUT6 (Prop_lut6_I0_O) 0.124 23.306 r u_cpu/id_stage/btb_counter[8][1]_i_4/O net (fo=2, routed) 0.671 23.977 u_cpu/btb/btb_counter_reg[8][1]_0 SLICE_X42Y4 LUT3 (Prop_lut3_I1_O) 0.150 24.127 r u_cpu/btb/btb_counter[8][1]_i_2/O net (fo=1, routed) 0.420 24.547 u_cpu/btb/btb_counter[8][1]_i_2_n_0 SLICE_X42Y3 LUT6 (Prop_lut6_I0_O) 0.348 24.895 r u_cpu/btb/btb_counter[8][1]_i_1/O net (fo=1, routed) 0.000 24.895 u_cpu/btb/btb_counter[8][1]_i_1_n_0 SLICE_X42Y3 FDRE r u_cpu/btb/btb_counter_reg[8][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.894 28.388 u_cpu/btb/cpu_clk SLICE_X42Y3 FDRE r u_cpu/btb/btb_counter_reg[8][1]/C clock pessimism -0.418 27.970 clock uncertainty -0.074 27.896 SLICE_X42Y3 FDRE (Setup_fdre_C_D) 0.077 27.973 u_cpu/btb/btb_counter_reg[8][1] ------------------------------------------------------------------- required time 27.973 arrival time -24.895 ------------------------------------------------------------------- slack 3.078 Slack (MET) : 3.080ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[8][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.061ns (logic 6.330ns (23.391%) route 20.731ns (76.609%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.935ns = ( 28.388 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.991 23.182 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X43Y4 LUT6 (Prop_lut6_I0_O) 0.124 23.306 r u_cpu/id_stage/btb_counter[8][1]_i_4/O net (fo=2, routed) 0.790 24.096 u_cpu/btb/btb_counter_reg[8][1]_0 SLICE_X43Y3 LUT3 (Prop_lut3_I1_O) 0.152 24.248 r u_cpu/btb/btb_counter[8][0]_i_2/O net (fo=1, routed) 0.267 24.515 u_cpu/btb/btb_counter[8][0]_i_2_n_0 SLICE_X43Y3 LUT6 (Prop_lut6_I0_O) 0.332 24.847 r u_cpu/btb/btb_counter[8][0]_i_1/O net (fo=1, routed) 0.000 24.847 u_cpu/btb/btb_counter[8][0]_i_1_n_0 SLICE_X43Y3 FDRE r u_cpu/btb/btb_counter_reg[8][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.894 28.388 u_cpu/btb/cpu_clk SLICE_X43Y3 FDRE r u_cpu/btb/btb_counter_reg[8][0]/C clock pessimism -0.418 27.970 clock uncertainty -0.074 27.896 SLICE_X43Y3 FDRE (Setup_fdre_C_D) 0.031 27.927 u_cpu/btb/btb_counter_reg[8][0] ------------------------------------------------------------------- required time 27.927 arrival time -24.847 ------------------------------------------------------------------- slack 3.080 Slack (MET) : 3.102ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[28][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.041ns (logic 6.297ns (23.286%) route 20.744ns (76.714%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.933ns = ( 28.390 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 1.186 23.377 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X47Y3 LUT6 (Prop_lut6_I0_O) 0.124 23.501 r u_cpu/id_stage/btb_counter[28][1]_i_8/O net (fo=2, routed) 0.416 23.918 u_cpu/btb/btb_counter_reg[28][1]_0 SLICE_X47Y4 LUT3 (Prop_lut3_I1_O) 0.119 24.037 r u_cpu/btb/btb_counter[28][1]_i_2/O net (fo=1, routed) 0.458 24.495 u_cpu/btb/btb_counter[28][1]_i_2_n_0 SLICE_X45Y3 LUT6 (Prop_lut6_I0_O) 0.332 24.827 r u_cpu/btb/btb_counter[28][1]_i_1/O net (fo=1, routed) 0.000 24.827 u_cpu/btb/btb_counter[28][1]_i_1_n_0 SLICE_X45Y3 FDRE r u_cpu/btb/btb_counter_reg[28][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.896 28.390 u_cpu/btb/cpu_clk SLICE_X45Y3 FDRE r u_cpu/btb/btb_counter_reg[28][1]/C clock pessimism -0.418 27.972 clock uncertainty -0.074 27.898 SLICE_X45Y3 FDRE (Setup_fdre_C_D) 0.031 27.929 u_cpu/btb/btb_counter_reg[28][1] ------------------------------------------------------------------- required time 27.929 arrival time -24.827 ------------------------------------------------------------------- slack 3.102 Slack (MET) : 3.107ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[0][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.035ns (logic 6.094ns (22.541%) route 20.941ns (77.459%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.933ns = ( 28.390 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 1.096 23.287 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X48Y7 LUT6 (Prop_lut6_I0_O) 0.124 23.411 r u_cpu/id_stage/btb_counter[0][1]_i_4/O net (fo=2, routed) 0.728 24.139 u_cpu/btb/btb_counter_reg[0][1]_0 SLICE_X47Y4 LUT3 (Prop_lut3_I1_O) 0.124 24.263 r u_cpu/btb/btb_counter[0][1]_i_2/O net (fo=1, routed) 0.433 24.696 u_cpu/btb/btb_counter[0][1]_i_2_n_0 SLICE_X47Y4 LUT6 (Prop_lut6_I0_O) 0.124 24.820 r u_cpu/btb/btb_counter[0][1]_i_1/O net (fo=1, routed) 0.000 24.820 u_cpu/btb/btb_counter[0][1]_i_1_n_0 SLICE_X47Y4 FDRE r u_cpu/btb/btb_counter_reg[0][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.896 28.390 u_cpu/btb/cpu_clk SLICE_X47Y4 FDRE r u_cpu/btb/btb_counter_reg[0][1]/C clock pessimism -0.418 27.972 clock uncertainty -0.074 27.898 SLICE_X47Y4 FDRE (Setup_fdre_C_D) 0.029 27.927 u_cpu/btb/btb_counter_reg[0][1] ------------------------------------------------------------------- required time 27.927 arrival time -24.820 ------------------------------------------------------------------- slack 3.107 Slack (MET) : 3.172ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[0][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.970ns (logic 6.094ns (22.596%) route 20.876ns (77.404%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.933ns = ( 28.390 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 1.096 23.287 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X48Y7 LUT6 (Prop_lut6_I0_O) 0.124 23.411 r u_cpu/id_stage/btb_counter[0][1]_i_4/O net (fo=2, routed) 0.462 23.874 u_cpu/btb/btb_counter_reg[0][1]_0 SLICE_X49Y7 LUT3 (Prop_lut3_I1_O) 0.124 23.998 r u_cpu/btb/btb_counter[0][0]_i_2/O net (fo=1, routed) 0.633 24.631 u_cpu/btb/btb_counter[0][0]_i_2_n_0 SLICE_X49Y6 LUT6 (Prop_lut6_I0_O) 0.124 24.755 r u_cpu/btb/btb_counter[0][0]_i_1/O net (fo=1, routed) 0.000 24.755 u_cpu/btb/btb_counter[0][0]_i_1_n_0 SLICE_X49Y6 FDRE r u_cpu/btb/btb_counter_reg[0][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.896 28.390 u_cpu/btb/cpu_clk SLICE_X49Y6 FDRE r u_cpu/btb/btb_counter_reg[0][0]/C clock pessimism -0.418 27.972 clock uncertainty -0.074 27.898 SLICE_X49Y6 FDRE (Setup_fdre_C_D) 0.029 27.927 u_cpu/btb/btb_counter_reg[0][0] ------------------------------------------------------------------- required time 27.927 arrival time -24.755 ------------------------------------------------------------------- slack 3.172 Slack (MET) : 3.215ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[24][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.928ns (logic 6.094ns (22.631%) route 20.834ns (77.369%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns = ( 28.391 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 1.142 23.333 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X48Y0 LUT6 (Prop_lut6_I0_O) 0.124 23.457 r u_cpu/id_stage/btb_counter[24][1]_i_4/O net (fo=2, routed) 0.575 24.032 u_cpu/btb/btb_counter_reg[24][1]_0 SLICE_X47Y0 LUT3 (Prop_lut3_I1_O) 0.124 24.156 r u_cpu/btb/btb_counter[24][0]_i_2/O net (fo=1, routed) 0.433 24.589 u_cpu/btb/btb_counter[24][0]_i_2_n_0 SLICE_X47Y0 LUT6 (Prop_lut6_I0_O) 0.124 24.713 r u_cpu/btb/btb_counter[24][0]_i_1/O net (fo=1, routed) 0.000 24.713 u_cpu/btb/btb_counter[24][0]_i_1_n_0 SLICE_X47Y0 FDRE r u_cpu/btb/btb_counter_reg[24][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.897 28.391 u_cpu/btb/cpu_clk SLICE_X47Y0 FDRE r u_cpu/btb/btb_counter_reg[24][0]/C clock pessimism -0.418 27.973 clock uncertainty -0.074 27.899 SLICE_X47Y0 FDRE (Setup_fdre_C_D) 0.029 27.928 u_cpu/btb/btb_counter_reg[24][0] ------------------------------------------------------------------- required time 27.928 arrival time -24.713 ------------------------------------------------------------------- slack 3.215 Slack (MET) : 3.215ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[26][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.928ns (logic 6.322ns (23.477%) route 20.606ns (76.523%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.933ns = ( 28.390 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 1.122 23.313 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X49Y6 LUT6 (Prop_lut6_I0_O) 0.124 23.437 r u_cpu/id_stage/btb_counter[26][1]_i_4/O net (fo=2, routed) 0.646 24.083 u_cpu/btb/btb_counter_reg[26][1]_0 SLICE_X49Y5 LUT3 (Prop_lut3_I1_O) 0.150 24.233 r u_cpu/btb/btb_counter[26][1]_i_2/O net (fo=1, routed) 0.154 24.388 u_cpu/btb/btb_counter[26][1]_i_2_n_0 SLICE_X49Y5 LUT6 (Prop_lut6_I0_O) 0.326 24.714 r u_cpu/btb/btb_counter[26][1]_i_1/O net (fo=1, routed) 0.000 24.714 u_cpu/btb/btb_counter[26][1]_i_1_n_0 SLICE_X49Y5 FDRE r u_cpu/btb/btb_counter_reg[26][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.896 28.390 u_cpu/btb/cpu_clk SLICE_X49Y5 FDRE r u_cpu/btb/btb_counter_reg[26][1]/C clock pessimism -0.418 27.972 clock uncertainty -0.074 27.898 SLICE_X49Y5 FDRE (Setup_fdre_C_D) 0.031 27.929 u_cpu/btb/btb_counter_reg[26][1] ------------------------------------------------------------------- required time 27.929 arrival time -24.714 ------------------------------------------------------------------- slack 3.215 Slack (MET) : 3.215ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[31][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.927ns (logic 6.094ns (22.631%) route 20.833ns (77.369%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.934ns = ( 28.389 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.990 23.181 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X48Y7 LUT6 (Prop_lut6_I5_O) 0.124 23.305 r u_cpu/id_stage/btb_counter[31][1]_i_7/O net (fo=2, routed) 0.305 23.610 u_cpu/btb/btb_counter_reg[31][1]_0 SLICE_X49Y7 LUT3 (Prop_lut3_I1_O) 0.124 23.734 r u_cpu/btb/btb_counter[31][1]_i_2/O net (fo=1, routed) 0.855 24.589 u_cpu/btb/btb_counter[31][1]_i_2_n_0 SLICE_X49Y7 LUT6 (Prop_lut6_I0_O) 0.124 24.713 r u_cpu/btb/btb_counter[31][1]_i_1/O net (fo=1, routed) 0.000 24.713 u_cpu/btb/btb_counter[31][1]_i_1_n_0 SLICE_X49Y7 FDRE r u_cpu/btb/btb_counter_reg[31][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.895 28.389 u_cpu/btb/cpu_clk SLICE_X49Y7 FDRE r u_cpu/btb/btb_counter_reg[31][1]/C clock pessimism -0.418 27.971 clock uncertainty -0.074 27.897 SLICE_X49Y7 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/btb/btb_counter_reg[31][1] ------------------------------------------------------------------- required time 27.928 arrival time -24.713 ------------------------------------------------------------------- slack 3.215 Slack (MET) : 3.248ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[5][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.944ns (logic 6.311ns (23.423%) route 20.633ns (76.577%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.933ns = ( 28.390 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.992 23.183 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X43Y4 LUT6 (Prop_lut6_I0_O) 0.124 23.307 r u_cpu/id_stage/btb_counter[5][1]_i_4/O net (fo=2, routed) 0.671 23.978 u_cpu/btb/btb_counter_reg[5][1]_0 SLICE_X44Y3 LUT3 (Prop_lut3_I1_O) 0.117 24.095 r u_cpu/btb/btb_counter[5][1]_i_2/O net (fo=1, routed) 0.286 24.381 u_cpu/btb/btb_counter[5][1]_i_2_n_0 SLICE_X44Y3 LUT6 (Prop_lut6_I0_O) 0.348 24.729 r u_cpu/btb/btb_counter[5][1]_i_1/O net (fo=1, routed) 0.000 24.729 u_cpu/btb/btb_counter[5][1]_i_1_n_0 SLICE_X44Y3 FDRE r u_cpu/btb/btb_counter_reg[5][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.896 28.390 u_cpu/btb/cpu_clk SLICE_X44Y3 FDRE r u_cpu/btb/btb_counter_reg[5][1]/C clock pessimism -0.418 27.972 clock uncertainty -0.074 27.898 SLICE_X44Y3 FDRE (Setup_fdre_C_D) 0.079 27.977 u_cpu/btb/btb_counter_reg[5][1] ------------------------------------------------------------------- required time 27.977 arrival time -24.729 ------------------------------------------------------------------- slack 3.248 Slack (MET) : 3.258ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[17][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.885ns (logic 6.094ns (22.667%) route 20.791ns (77.333%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns = ( 28.391 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.876 23.068 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X41Y2 LUT6 (Prop_lut6_I0_O) 0.124 23.192 r u_cpu/id_stage/btb_counter[17][1]_i_4/O net (fo=2, routed) 0.797 23.989 u_cpu/btb/btb_counter_reg[17][1]_0 SLICE_X45Y2 LUT3 (Prop_lut3_I1_O) 0.124 24.113 r u_cpu/btb/btb_counter[17][1]_i_2/O net (fo=1, routed) 0.433 24.546 u_cpu/btb/btb_counter[17][1]_i_2_n_0 SLICE_X45Y2 LUT6 (Prop_lut6_I0_O) 0.124 24.670 r u_cpu/btb/btb_counter[17][1]_i_1/O net (fo=1, routed) 0.000 24.670 u_cpu/btb/btb_counter[17][1]_i_1_n_0 SLICE_X45Y2 FDRE r u_cpu/btb/btb_counter_reg[17][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.897 28.391 u_cpu/btb/cpu_clk SLICE_X45Y2 FDRE r u_cpu/btb/btb_counter_reg[17][1]/C clock pessimism -0.418 27.973 clock uncertainty -0.074 27.899 SLICE_X45Y2 FDRE (Setup_fdre_C_D) 0.029 27.928 u_cpu/btb/btb_counter_reg[17][1] ------------------------------------------------------------------- required time 27.928 arrival time -24.670 ------------------------------------------------------------------- slack 3.258 Slack (MET) : 3.288ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[28][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.854ns (logic 6.094ns (22.693%) route 20.760ns (77.307%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.933ns = ( 28.390 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 1.186 23.377 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X47Y3 LUT6 (Prop_lut6_I0_O) 0.124 23.501 r u_cpu/id_stage/btb_counter[28][1]_i_8/O net (fo=2, routed) 0.463 23.964 u_cpu/btb/btb_counter_reg[28][1]_0 SLICE_X47Y3 LUT3 (Prop_lut3_I1_O) 0.124 24.088 r u_cpu/btb/btb_counter[28][0]_i_2/O net (fo=1, routed) 0.427 24.515 u_cpu/btb/btb_counter[28][0]_i_2_n_0 SLICE_X45Y3 LUT6 (Prop_lut6_I0_O) 0.124 24.639 r u_cpu/btb/btb_counter[28][0]_i_1/O net (fo=1, routed) 0.000 24.639 u_cpu/btb/btb_counter[28][0]_i_1_n_0 SLICE_X45Y3 FDRE r u_cpu/btb/btb_counter_reg[28][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.896 28.390 u_cpu/btb/cpu_clk SLICE_X45Y3 FDRE r u_cpu/btb/btb_counter_reg[28][0]/C clock pessimism -0.418 27.972 clock uncertainty -0.074 27.898 SLICE_X45Y3 FDRE (Setup_fdre_C_D) 0.029 27.927 u_cpu/btb/btb_counter_reg[28][0] ------------------------------------------------------------------- required time 27.927 arrival time -24.639 ------------------------------------------------------------------- slack 3.288 Slack (MET) : 3.299ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_counter_reg[6][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.846ns (logic 6.297ns (23.456%) route 20.549ns (76.544%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns = ( 28.391 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.127 -2.215 u_cpu/addr_trans/cpu_clk SLICE_X20Y38 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 1.007 10.977 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y19 LUT6 (Prop_lut6_I5_O) 0.124 11.101 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 11.101 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X20Y19 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.614 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.614 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X20Y20 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.843 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.464 12.307 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X21Y18 LUT6 (Prop_lut6_I0_O) 0.310 12.617 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.946 13.562 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X23Y20 LUT3 (Prop_lut3_I2_O) 0.124 13.686 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.678 14.365 u_cpu/dcache/main_state_reg[0]_2 SLICE_X25Y18 LUT6 (Prop_lut6_I3_O) 0.124 14.489 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.453 14.942 u_cpu/mem_stage/data_data_ok SLICE_X27Y18 LUT6 (Prop_lut6_I2_O) 0.124 15.066 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.505 15.571 u_cpu/mem_stage/ms_allowin SLICE_X27Y17 LUT6 (Prop_lut6_I2_O) 0.124 15.695 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.591 16.285 u_cpu/exe_stage/p_13_in SLICE_X22Y17 LUT5 (Prop_lut5_I0_O) 0.124 16.409 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.455 16.864 u_cpu/exe_stage/dcacop_op_en SLICE_X20Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.988 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.672 17.660 u_cpu/exe_stage/main_idle2lookup SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 17.784 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.445 18.229 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X21Y17 LUT5 (Prop_lut5_I4_O) 0.124 18.353 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.855 19.208 u_cpu/exe_stage/data_addr_ok SLICE_X26Y16 LUT6 (Prop_lut6_I2_O) 0.124 19.332 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.486 19.818 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X28Y15 LUT6 (Prop_lut6_I2_O) 0.124 19.942 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.651 20.593 u_cpu/id_stage/btb_operate_en SLICE_X32Y12 LUT2 (Prop_lut2_I1_O) 0.124 20.717 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14/O net (fo=31, routed) 0.644 21.361 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_14_n_0 SLICE_X36Y11 LUT6 (Prop_lut6_I0_O) 0.124 21.485 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 0.583 22.067 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X38Y9 LUT4 (Prop_lut4_I1_O) 0.124 22.191 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.979 23.171 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X45Y2 LUT6 (Prop_lut6_I0_O) 0.124 23.295 r u_cpu/id_stage/btb_counter[6][1]_i_4/O net (fo=2, routed) 0.619 23.914 u_cpu/btb/btb_counter_reg[6][1]_0 SLICE_X47Y0 LUT3 (Prop_lut3_I1_O) 0.119 24.033 r u_cpu/btb/btb_counter[6][0]_i_2/O net (fo=1, routed) 0.267 24.299 u_cpu/btb/btb_counter[6][0]_i_2_n_0 SLICE_X47Y0 LUT6 (Prop_lut6_I0_O) 0.332 24.631 r u_cpu/btb/btb_counter[6][0]_i_1/O net (fo=1, routed) 0.000 24.631 u_cpu/btb/btb_counter[6][0]_i_1_n_0 SLICE_X47Y0 FDRE r u_cpu/btb/btb_counter_reg[6][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.897 28.391 u_cpu/btb/cpu_clk SLICE_X47Y0 FDRE r u_cpu/btb/btb_counter_reg[6][0]/C clock pessimism -0.418 27.973 clock uncertainty -0.074 27.899 SLICE_X47Y0 FDRE (Setup_fdre_C_D) 0.031 27.930 u_cpu/btb/btb_counter_reg[6][0] ------------------------------------------------------------------- required time 27.930 arrival time -24.631 ------------------------------------------------------------------- slack 3.299 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: cpu_clk Waveform(ns): { 0.000 15.161 } Period(ns): 30.323 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y9 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y9 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y5 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y5 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y7 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y7 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y4 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y4 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y8 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y8 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y6 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y6 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y5 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y5 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y4 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y4 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y7 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y7 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y6 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y6 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkout1_buf/I Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.323 29.074 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X6Y63 pll_clk.u_rst_cpu/delay_reg[0]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X6Y63 pll_clk.u_rst_cpu/delay_reg[1]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X18Y64 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X18Y64 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X18Y64 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X18Y64 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X18Y64 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X18Y64 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y29 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r1_0_31_0_0/DP/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y29 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r1_0_31_0_0/SP/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y68 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y68 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- From Clock: mlkem_clk_clk_pll To Clock: mlkem_clk_clk_pll Setup : 0 Failing Endpoints, Worst Slack 12.906ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 12.906ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.488ns (logic 1.164ns (4.394%) route 25.324ns (95.606%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X153Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/C clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400] ------------------------------------------------------------------- required time 36.872 arrival time -23.966 ------------------------------------------------------------------- slack 12.906 Slack (MET) : 12.906ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.488ns (logic 1.164ns (4.394%) route 25.324ns (95.606%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X153Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/C clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592] ------------------------------------------------------------------- required time 36.872 arrival time -23.966 ------------------------------------------------------------------- slack 12.906 Slack (MET) : 12.985ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.751ns (logic 1.556ns (5.817%) route 25.195ns (94.183%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.245 21.384 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X123Y140 LUT4 (Prop_lut4_I3_O) 0.118 21.502 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[602]_i_3/O net (fo=1, routed) 1.525 23.027 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[602] SLICE_X132Y158 LUT6 (Prop_lut6_I0_O) 0.326 23.353 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[602]_i_2/O net (fo=1, routed) 0.757 24.111 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[341] SLICE_X134Y155 LUT3 (Prop_lut3_I1_O) 0.118 24.229 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[602]_i_1/O net (fo=1, routed) 0.000 24.229 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[602] SLICE_X134Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.557 37.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X134Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602]/C clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X134Y155 FDCE (Setup_fdce_C_D) 0.075 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602] ------------------------------------------------------------------- required time 37.213 arrival time -24.229 ------------------------------------------------------------------- slack 12.985 Slack (MET) : 12.994ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.404ns (logic 1.164ns (4.408%) route 25.240ns (95.592%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.279 23.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.627 37.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X153Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/C clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X153Y128 FDCE (Setup_fdce_C_CE) -0.413 36.875 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527] ------------------------------------------------------------------- required time 36.875 arrival time -23.881 ------------------------------------------------------------------- slack 12.994 Slack (MET) : 13.047ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.784ns (logic 1.624ns (6.063%) route 25.160ns (93.937%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.167ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.255ns = ( 37.745 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.176 20.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X119Y148 LUT4 (Prop_lut4_I3_O) 0.152 20.467 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[795]_i_3/O net (fo=1, routed) 1.499 21.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[795] SLICE_X120Y158 LUT6 (Prop_lut6_I0_O) 0.326 22.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[795]_i_2/O net (fo=1, routed) 1.818 24.110 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[534] SLICE_X131Y145 LUT3 (Prop_lut3_I1_O) 0.152 24.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[795]_i_1/O net (fo=1, routed) 0.000 24.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[795] SLICE_X131Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.573 37.745 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X131Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795]/C clock pessimism -0.435 37.310 clock uncertainty -0.077 37.234 SLICE_X131Y145 FDCE (Setup_fdce_C_D) 0.075 37.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795] ------------------------------------------------------------------- required time 37.309 arrival time -24.262 ------------------------------------------------------------------- slack 13.047 Slack (MET) : 13.154ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.538ns (logic 1.562ns (5.886%) route 24.976ns (94.114%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.901 21.041 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X130Y146 LUT4 (Prop_lut4_I3_O) 0.118 21.159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[629]_i_3/O net (fo=1, routed) 1.198 22.357 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[629] SLICE_X134Y157 LUT6 (Prop_lut6_I0_O) 0.326 22.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[629]_i_2/O net (fo=1, routed) 1.209 23.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[368] SLICE_X134Y155 LUT3 (Prop_lut3_I1_O) 0.124 24.016 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[629]_i_1/O net (fo=1, routed) 0.000 24.016 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[629] SLICE_X134Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.557 37.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X134Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629]/C clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X134Y155 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629] ------------------------------------------------------------------- required time 37.169 arrival time -24.016 ------------------------------------------------------------------- slack 13.154 Slack (MET) : 13.175ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.605ns (logic 1.612ns (6.059%) route 24.993ns (93.941%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.271ns = ( 37.729 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.059 21.198 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X136Y146 LUT4 (Prop_lut4_I3_O) 0.117 21.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[731]_i_3/O net (fo=1, routed) 1.245 22.560 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[731] SLICE_X138Y157 LUT6 (Prop_lut6_I0_O) 0.348 22.908 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[731]_i_2/O net (fo=1, routed) 1.021 23.930 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[470] SLICE_X132Y150 LUT3 (Prop_lut3_I1_O) 0.153 24.083 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[731]_i_1/O net (fo=1, routed) 0.000 24.083 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[731] SLICE_X132Y150 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.558 37.729 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X132Y150 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731]/C clock pessimism -0.514 37.216 clock uncertainty -0.077 37.139 SLICE_X132Y150 FDCE (Setup_fdce_C_D) 0.118 37.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731] ------------------------------------------------------------------- required time 37.257 arrival time -24.083 ------------------------------------------------------------------- slack 13.175 Slack (MET) : 13.193ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.240ns (logic 1.164ns (4.436%) route 25.076ns (95.564%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.627 37.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X150Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/C clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402] ------------------------------------------------------------------- required time 36.911 arrival time -23.717 ------------------------------------------------------------------- slack 13.193 Slack (MET) : 13.193ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.240ns (logic 1.164ns (4.436%) route 25.076ns (95.564%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.627 37.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X150Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/C clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466] ------------------------------------------------------------------- required time 36.911 arrival time -23.717 ------------------------------------------------------------------- slack 13.193 Slack (MET) : 13.240ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.153ns (logic 1.164ns (4.451%) route 24.989ns (95.549%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.028 23.630 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X151Y124 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.622 37.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X151Y124 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/C clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X151Y124 FDCE (Setup_fdce_C_CE) -0.413 36.870 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383] ------------------------------------------------------------------- required time 36.870 arrival time -23.630 ------------------------------------------------------------------- slack 13.240 Slack (MET) : 13.246ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.531ns (logic 1.366ns (5.149%) route 25.165ns (94.851%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.264ns = ( 37.736 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.901 21.041 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X130Y146 LUT4 (Prop_lut4_I3_O) 0.124 21.165 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[296]_i_3/O net (fo=1, routed) 1.879 23.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[296] SLICE_X123Y131 LUT6 (Prop_lut6_I0_O) 0.124 23.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[296]_i_2/O net (fo=1, routed) 0.717 23.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[35] SLICE_X123Y133 LUT3 (Prop_lut3_I1_O) 0.124 24.008 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[296]_i_1/O net (fo=1, routed) 0.000 24.008 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[296] SLICE_X123Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.564 37.736 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X123Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296]/C clock pessimism -0.435 37.301 clock uncertainty -0.077 37.225 SLICE_X123Y133 FDCE (Setup_fdce_C_D) 0.029 37.254 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296] ------------------------------------------------------------------- required time 37.254 arrival time -24.008 ------------------------------------------------------------------- slack 13.246 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.633 37.805 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X141Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142]/C clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.633 37.805 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X141Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144]/C clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.633 37.805 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X141Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173]/C clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.292ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.141ns (logic 1.164ns (4.453%) route 24.977ns (95.547%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.016 23.618 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.626 37.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X146Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472]/C clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X146Y128 FDCE (Setup_fdce_C_CE) -0.377 36.910 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472] ------------------------------------------------------------------- required time 36.910 arrival time -23.618 ------------------------------------------------------------------- slack 13.292 Slack (MET) : 13.292ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.141ns (logic 1.164ns (4.453%) route 24.977ns (95.547%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.016 23.618 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.626 37.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X146Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478]/C clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X146Y128 FDCE (Setup_fdce_C_CE) -0.377 36.910 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478] ------------------------------------------------------------------- required time 36.910 arrival time -23.618 ------------------------------------------------------------------- slack 13.292 Slack (MET) : 13.301ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.131ns (logic 1.164ns (4.455%) route 24.967ns (95.545%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.203ns = ( 37.797 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.006 23.608 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X152Y127 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.625 37.797 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X152Y127 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384]/C clock pessimism -0.435 37.362 clock uncertainty -0.077 37.286 SLICE_X152Y127 FDCE (Setup_fdce_C_CE) -0.377 36.909 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384] ------------------------------------------------------------------- required time 36.909 arrival time -23.608 ------------------------------------------------------------------- slack 13.301 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.557 37.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628]/C clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.557 37.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631]/C clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.557 37.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725]/C clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.557 37.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728]/C clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.317ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.018ns (logic 1.164ns (4.474%) route 24.854ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.263ns = ( 37.737 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.894 23.495 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X133Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.565 37.737 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X133Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568]/C clock pessimism -0.435 37.302 clock uncertainty -0.077 37.226 SLICE_X133Y117 FDCE (Setup_fdce_C_CE) -0.413 36.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568] ------------------------------------------------------------------- required time 36.813 arrival time -23.495 ------------------------------------------------------------------- slack 13.317 Slack (MET) : 13.317ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.018ns (logic 1.164ns (4.474%) route 24.854ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.263ns = ( 37.737 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.894 23.495 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X133Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.565 37.737 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X133Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574]/C clock pessimism -0.435 37.302 clock uncertainty -0.077 37.226 SLICE_X133Y117 FDCE (Setup_fdce_C_CE) -0.413 36.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574] ------------------------------------------------------------------- required time 36.813 arrival time -23.495 ------------------------------------------------------------------- slack 13.317 Slack (MET) : 13.319ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.482ns (logic 1.594ns (6.019%) route 24.888ns (93.981%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.209ns = ( 37.791 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.909 21.049 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X125Y147 LUT4 (Prop_lut4_I3_O) 0.150 21.199 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[675]_i_3/O net (fo=1, routed) 1.702 22.901 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[675] SLICE_X141Y156 LUT6 (Prop_lut6_I0_O) 0.326 23.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[675]_i_2/O net (fo=1, routed) 0.609 23.835 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[414] SLICE_X142Y156 LUT3 (Prop_lut3_I1_O) 0.124 23.959 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[675]_i_1/O net (fo=1, routed) 0.000 23.959 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[675] SLICE_X142Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.620 37.791 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X142Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675]/C clock pessimism -0.514 37.278 clock uncertainty -0.077 37.201 SLICE_X142Y156 FDCE (Setup_fdce_C_D) 0.077 37.278 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675] ------------------------------------------------------------------- required time 37.278 arrival time -23.959 ------------------------------------------------------------------- slack 13.319 Slack (MET) : 13.335ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.094ns (logic 1.164ns (4.461%) route 24.930ns (95.539%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.970 23.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X146Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347]/C clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y126 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347] ------------------------------------------------------------------- required time 36.907 arrival time -23.572 ------------------------------------------------------------------- slack 13.335 Slack (MET) : 13.375ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.019ns (logic 1.164ns (4.474%) route 24.855ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.895 23.497 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X143Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X143Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336]/C clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X143Y128 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336] ------------------------------------------------------------------- required time 36.872 arrival time -23.497 ------------------------------------------------------------------- slack 13.375 Slack (MET) : 13.383ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.512ns (logic 1.562ns (5.892%) route 24.950ns (94.108%)) Logic Levels: 5 (LUT3=1 LUT4=1 LUT5=1 LUT6=2) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.193ns = ( 37.807 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.287 21.427 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X132Y142 LUT4 (Prop_lut4_I3_O) 0.116 21.543 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1112]_i_4/O net (fo=1, routed) 0.954 22.497 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[1112] SLICE_X138Y142 LUT6 (Prop_lut6_I0_O) 0.328 22.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[1112]_i_3/O net (fo=1, routed) 1.041 23.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[851] SLICE_X142Y142 LUT5 (Prop_lut5_I3_O) 0.124 23.990 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1112]_i_1/O net (fo=1, routed) 0.000 23.990 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[1112] SLICE_X142Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.635 37.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X142Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112]/C clock pessimism -0.435 37.372 clock uncertainty -0.077 37.296 SLICE_X142Y142 FDCE (Setup_fdce_C_D) 0.077 37.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112] ------------------------------------------------------------------- required time 37.373 arrival time -23.990 ------------------------------------------------------------------- slack 13.383 Slack (MET) : 13.417ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.979ns (logic 1.164ns (4.481%) route 24.815ns (95.519%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.855 23.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X145Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.626 37.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X145Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414]/C clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X145Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414] ------------------------------------------------------------------- required time 36.874 arrival time -23.456 ------------------------------------------------------------------- slack 13.417 Slack (MET) : 13.417ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.979ns (logic 1.164ns (4.481%) route 24.815ns (95.519%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.855 23.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X145Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.626 37.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X145Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576]/C clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X145Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576] ------------------------------------------------------------------- required time 36.874 arrival time -23.456 ------------------------------------------------------------------- slack 13.417 Slack (MET) : 13.419ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.010ns (logic 1.164ns (4.475%) route 24.846ns (95.525%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.885 23.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X148Y124 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.622 37.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X148Y124 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513]/C clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X148Y124 FDCE (Setup_fdce_C_CE) -0.377 36.906 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513] ------------------------------------------------------------------- required time 36.906 arrival time -23.487 ------------------------------------------------------------------- slack 13.419 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287]/C clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415]/C clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543]/C clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572]/C clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.444ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.985ns (logic 1.164ns (4.480%) route 24.821ns (95.520%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.860 23.462 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X140Y127 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.622 37.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X140Y127 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439]/C clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X140Y127 FDCE (Setup_fdce_C_CE) -0.377 36.906 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439] ------------------------------------------------------------------- required time 36.906 arrival time -23.462 ------------------------------------------------------------------- slack 13.444 Slack (MET) : 13.445ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.951ns (logic 1.164ns (4.485%) route 24.787ns (95.515%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.827 23.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X147Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.626 37.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X147Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416]/C clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X147Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416] ------------------------------------------------------------------- required time 36.874 arrival time -23.429 ------------------------------------------------------------------- slack 13.445 Slack (MET) : 13.445ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.951ns (logic 1.164ns (4.485%) route 24.787ns (95.515%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.827 23.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X147Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.626 37.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X147Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480]/C clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X147Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480] ------------------------------------------------------------------- required time 36.874 arrival time -23.429 ------------------------------------------------------------------- slack 13.445 Slack (MET) : 13.504ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.930ns (logic 1.164ns (4.489%) route 24.766ns (95.511%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.805 23.407 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X144Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.627 37.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X144Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418]/C clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X144Y129 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418] ------------------------------------------------------------------- required time 36.911 arrival time -23.407 ------------------------------------------------------------------- slack 13.504 Slack (MET) : 13.528ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.208ns (logic 1.620ns (6.181%) route 24.588ns (93.819%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.271ns = ( 37.729 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 8.784 19.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X105Y139 LUT4 (Prop_lut4_I3_O) 0.150 20.074 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[598]_i_3/O net (fo=1, routed) 1.791 21.864 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[598] SLICE_X115Y158 LUT6 (Prop_lut6_I0_O) 0.326 22.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[598]_i_2/O net (fo=1, routed) 1.346 23.536 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[337] SLICE_X133Y151 LUT3 (Prop_lut3_I1_O) 0.150 23.686 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[598]_i_1/O net (fo=1, routed) 0.000 23.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[598] SLICE_X133Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.558 37.729 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X133Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598]/C clock pessimism -0.514 37.216 clock uncertainty -0.077 37.139 SLICE_X133Y151 FDCE (Setup_fdce_C_D) 0.075 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598] ------------------------------------------------------------------- required time 37.214 arrival time -23.686 ------------------------------------------------------------------- slack 13.528 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.631 37.803 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206]/C clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.631 37.803 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246]/C clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.631 37.803 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53]/C clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.631 37.803 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57]/C clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.566ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.763ns (logic 1.164ns (4.518%) route 24.599ns (95.482%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.181ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.269ns = ( 37.731 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.639 23.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X138Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.559 37.731 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X138Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413]/C clock pessimism -0.435 37.296 clock uncertainty -0.077 37.220 SLICE_X138Y126 FDCE (Setup_fdce_C_CE) -0.413 36.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413] ------------------------------------------------------------------- required time 36.807 arrival time -23.240 ------------------------------------------------------------------- slack 13.566 Slack (MET) : 13.566ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1471]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.763ns (logic 1.164ns (4.518%) route 24.599ns (95.482%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.181ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.269ns = ( 37.731 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.639 23.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X138Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1471]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.559 37.731 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X138Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1471]/C clock pessimism -0.435 37.296 clock uncertainty -0.077 37.220 SLICE_X138Y126 FDCE (Setup_fdce_C_CE) -0.413 36.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1471] ------------------------------------------------------------------- required time 36.807 arrival time -23.240 ------------------------------------------------------------------- slack 13.566 Slack (MET) : 13.581ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[145]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.761ns (logic 0.761ns (2.954%) route 25.000ns (97.046%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.168ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.256ns = ( 37.744 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 11.960 23.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X137Y110 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[145]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.572 37.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X137Y110 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[145]/C clock pessimism -0.435 37.309 clock uncertainty -0.077 37.233 SLICE_X137Y110 FDCE (Setup_fdce_C_CE) -0.413 36.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[145] ------------------------------------------------------------------- required time 36.820 arrival time -23.238 ------------------------------------------------------------------- slack 13.581 Slack (MET) : 13.581ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[177]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.761ns (logic 0.761ns (2.954%) route 25.000ns (97.046%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.168ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.256ns = ( 37.744 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 11.960 23.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X137Y110 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[177]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.572 37.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X137Y110 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[177]/C clock pessimism -0.435 37.309 clock uncertainty -0.077 37.233 SLICE_X137Y110 FDCE (Setup_fdce_C_CE) -0.413 36.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[177] ------------------------------------------------------------------- required time 36.820 arrival time -23.238 ------------------------------------------------------------------- slack 13.581 Slack (MET) : 13.581ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[209]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.761ns (logic 0.761ns (2.954%) route 25.000ns (97.046%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.168ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.256ns = ( 37.744 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 11.960 23.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X137Y110 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[209]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.572 37.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X137Y110 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[209]/C clock pessimism -0.435 37.309 clock uncertainty -0.077 37.233 SLICE_X137Y110 FDCE (Setup_fdce_C_CE) -0.413 36.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[209] ------------------------------------------------------------------- required time 36.820 arrival time -23.238 ------------------------------------------------------------------- slack 13.581 Slack (MET) : 13.601ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1328]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.830ns (logic 1.164ns (4.506%) route 24.666ns (95.494%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.705 23.307 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X142Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1328]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X142Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1328]/C clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X142Y128 FDCE (Setup_fdce_C_CE) -0.377 36.908 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1328] ------------------------------------------------------------------- required time 36.908 arrival time -23.307 ------------------------------------------------------------------- slack 13.601 Slack (MET) : 13.624ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[614]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.113ns (logic 1.631ns (6.246%) route 24.482ns (93.754%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.271ns = ( 37.729 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X158Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.834 20.973 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X126Y149 LUT4 (Prop_lut4_I3_O) 0.152 21.125 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[614]_i_3/O net (fo=1, routed) 0.798 21.923 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[614] SLICE_X130Y156 LUT6 (Prop_lut6_I0_O) 0.332 22.255 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[614]_i_2/O net (fo=1, routed) 1.181 23.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[353] SLICE_X134Y152 LUT3 (Prop_lut3_I1_O) 0.153 23.590 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[614]_i_1/O net (fo=1, routed) 0.000 23.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[614] SLICE_X134Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[614]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.558 37.729 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X134Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[614]/C clock pessimism -0.514 37.216 clock uncertainty -0.077 37.139 SLICE_X134Y152 FDCE (Setup_fdce_C_D) 0.075 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[614] ------------------------------------------------------------------- required time 37.214 arrival time -23.590 ------------------------------------------------------------------- slack 13.624 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: mlkem_clk_clk_pll Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X2Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X2Y49 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X2Y50 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X2Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X2Y58 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X2Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X2Y59 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X3Y48 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X2Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X2Y49 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X2Y50 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X2Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X2Y58 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X2Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X2Y59 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X3Y48 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout3_buf/I Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X1Y62 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X8Y61 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X7Y71 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X8Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X4Y64 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X8Y66 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X7Y64 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X7Y69 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X1Y65 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X3Y65 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X2Y64 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X2Y60 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X2Y62 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X8Y67 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X7Y70 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X7Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X8Y64 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X1Y64 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X3Y64 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10/CLK Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 40.000 38.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X70Y163 _i_1/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X60Y163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_4/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X62Y163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg[6]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X155Y163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X145Y163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_0/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X121Y164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_1/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X86Y164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_2/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X86Y165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_3/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X81Y165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_4/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X59Y158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_o_r_reg/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X80Y166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wa_d6_reg[0]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_4/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X72Y166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wa_d6_reg[1]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_4/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X60Y163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wa_d6_reg[2]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_4/C Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 40.000 120.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X48Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X48Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: sys_clk To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 0.424ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.424ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.252ns (logic 7.003ns (45.917%) route 8.249ns (54.083%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.455 7.318 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X1Y124 LUT6 (Prop_lut6_I5_O) 0.124 7.442 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O net (fo=1, routed) 1.937 9.379 base_ram_be_n_OBUF[3] K25 OBUF (Prop_obuf_I_O) 3.551 12.930 r base_ram_be_n_OBUF[3]_inst/O net (fo=0) 0.000 12.930 base_ram_be_n[3] K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.930 ------------------------------------------------------------------- slack 0.424 Slack (MET) : 0.569ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.107ns (logic 7.010ns (46.402%) route 8.097ns (53.598%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.640 9.227 ext_ram_data_IOBUF[24]_inst/T AD17 OBUFT (TriStatE_obuft_T_O) 3.558 12.785 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 12.785 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.785 ------------------------------------------------------------------- slack 0.569 Slack (MET) : 0.577ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.190ns (logic 5.298ns (34.876%) route 9.893ns (65.124%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.928 -2.414 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X20Y76 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.861 9.248 ext_ram_data_IOBUF[30]_inst/I AA19 OBUFT (Prop_obuft_I_O) 3.529 12.777 r ext_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.777 ext_ram_data[30] AA19 r ext_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.777 ------------------------------------------------------------------- slack 0.577 Slack (MET) : 0.647ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.120ns (logic 5.412ns (35.791%) route 9.709ns (64.209%)) Logic Levels: 9 (LUT2=1 LUT3=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.928 -2.414 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X20Y76 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.261 3.015 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X18Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.161 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.789 3.950 u_snix_axil_cdma_mux_8ch/ep_rd_c1[0] SLICE_X16Y80 LUT6 (Prop_lut6_I1_O) 0.328 4.278 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O net (fo=1, routed) 0.775 5.054 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_2 SLICE_X13Y80 LUT5 (Prop_lut5_I4_O) 0.124 5.178 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/O net (fo=5, routed) 0.627 5.805 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X8Y81 LUT3 (Prop_lut3_I0_O) 0.124 5.929 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.233 9.162 base_ram_data_IOBUF[0]_inst/I L24 OBUFT (Prop_obuft_I_O) 3.545 12.707 r base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.707 base_ram_data[0] L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.707 ------------------------------------------------------------------- slack 0.647 Slack (MET) : 0.678ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.089ns (logic 5.264ns (34.886%) route 9.825ns (65.114%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.928 -2.414 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X20Y76 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.511 3.265 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 SLICE_X22Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.411 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/O net (fo=1, routed) 0.484 3.895 u_matmul_axi_slave/ep_rd_c1_39[48] SLICE_X23Y81 LUT4 (Prop_lut4_I0_O) 0.328 4.223 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/O net (fo=3, routed) 0.615 4.838 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[13] SLICE_X20Y83 LUT6 (Prop_lut6_I2_O) 0.124 4.962 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/O net (fo=2, routed) 4.193 9.155 ext_ram_data_IOBUF[16]_inst/I AB16 OBUFT (Prop_obuft_I_O) 3.521 12.676 r ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.676 ext_ram_data[16] AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.676 ------------------------------------------------------------------- slack 0.678 Slack (MET) : 0.749ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.019ns (logic 5.313ns (35.377%) route 9.706ns (64.623%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.928 -2.414 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X20Y76 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.674 9.061 base_ram_data_IOBUF[30]_inst/I M24 OBUFT (Prop_obuft_I_O) 3.544 12.605 r base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.605 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.605 ------------------------------------------------------------------- slack 0.749 Slack (MET) : 0.758ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.918ns (logic 7.005ns (46.961%) route 7.912ns (53.039%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[25]_inst/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.596 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.596 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.596 ------------------------------------------------------------------- slack 0.758 Slack (MET) : 0.770ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.906ns (logic 6.994ns (46.921%) route 7.912ns (53.079%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[18]_inst/T AB17 OBUFT (TriStatE_obuft_T_O) 3.542 12.584 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.584 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.584 ------------------------------------------------------------------- slack 0.770 Slack (MET) : 0.803ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.873ns (logic 6.998ns (47.053%) route 7.875ns (52.947%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.612 9.005 base_ram_data_IOBUF[31]_inst/T M22 OBUFT (TriStatE_obuft_T_O) 3.546 12.551 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.551 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.551 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.822ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.853ns (logic 6.983ns (47.014%) route 7.870ns (52.986%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.486 7.348 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] SLICE_X0Y133 LUT6 (Prop_lut6_I5_O) 0.124 7.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O net (fo=1, routed) 1.529 9.000 base_ram_be_n_OBUF[0] L20 OBUF (Prop_obuf_I_O) 3.531 12.532 r base_ram_be_n_OBUF[0]_inst/O net (fo=0) 0.000 12.532 base_ram_be_n[0] L20 r base_ram_be_n[0] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.532 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.823ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.852ns (logic 7.012ns (47.209%) route 7.841ns (52.791%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.384 8.971 ext_ram_data_IOBUF[20]_inst/T AD18 OBUFT (TriStatE_obuft_T_O) 3.560 12.531 r ext_ram_data_IOBUF[20]_inst/OBUFT/O net (fo=1, unset) 0.000 12.531 ext_ram_data[20] AD18 r ext_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.531 ------------------------------------------------------------------- slack 0.823 Slack (MET) : 0.826ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.942ns (logic 5.453ns (36.494%) route 9.489ns (63.506%)) Logic Levels: 9 (LUT2=1 LUT3=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.928 -2.414 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X20Y76 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.261 3.015 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X18Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.161 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.789 3.950 u_snix_axil_cdma_mux_8ch/ep_rd_c1[0] SLICE_X16Y80 LUT6 (Prop_lut6_I1_O) 0.328 4.278 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O net (fo=1, routed) 0.775 5.054 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_2 SLICE_X13Y80 LUT5 (Prop_lut5_I4_O) 0.124 5.178 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/O net (fo=5, routed) 0.627 5.805 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X8Y81 LUT3 (Prop_lut3_I0_O) 0.124 5.929 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.014 8.943 ext_ram_data_IOBUF[0]_inst/I AF24 OBUFT (Prop_obuft_I_O) 3.586 12.529 r ext_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.529 ext_ram_data[0] AF24 r ext_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.529 ------------------------------------------------------------------- slack 0.826 Slack (MET) : 0.826ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[19] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.850ns (logic 7.009ns (47.201%) route 7.840ns (52.799%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.383 8.971 ext_ram_data_IOBUF[19]_inst/T AC18 OBUFT (TriStatE_obuft_T_O) 3.557 12.528 r ext_ram_data_IOBUF[19]_inst/OBUFT/O net (fo=1, unset) 0.000 12.528 ext_ram_data[19] AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.528 ------------------------------------------------------------------- slack 0.826 Slack (MET) : 0.838ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[17] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.838ns (logic 7.007ns (47.226%) route 7.830ns (52.774%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.373 8.961 ext_ram_data_IOBUF[17]_inst/T AC19 OBUFT (TriStatE_obuft_T_O) 3.555 12.516 r ext_ram_data_IOBUF[17]_inst/OBUFT/O net (fo=1, unset) 0.000 12.516 ext_ram_data[17] AC19 r ext_ram_data[17] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.516 ------------------------------------------------------------------- slack 0.838 Slack (MET) : 0.839ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.836ns (logic 6.995ns (47.148%) route 7.841ns (52.852%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.384 8.972 ext_ram_data_IOBUF[22]_inst/T Y15 OBUFT (TriStatE_obuft_T_O) 3.543 12.515 r ext_ram_data_IOBUF[22]_inst/OBUFT/O net (fo=1, unset) 0.000 12.515 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.515 ------------------------------------------------------------------- slack 0.839 Slack (MET) : 0.845ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.830ns (logic 7.016ns (47.309%) route 7.814ns (52.691%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.552 8.945 base_ram_data_IOBUF[1]_inst/T L25 OBUFT (TriStatE_obuft_T_O) 3.564 12.509 r base_ram_data_IOBUF[1]_inst/OBUFT/O net (fo=1, unset) 0.000 12.509 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.509 ------------------------------------------------------------------- slack 0.845 Slack (MET) : 0.846ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[23] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.830ns (logic 6.987ns (47.116%) route 7.843ns (52.884%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.580 8.973 base_ram_data_IOBUF[23]_inst/T N21 OBUFT (TriStatE_obuft_T_O) 3.535 12.508 r base_ram_data_IOBUF[23]_inst/OBUFT/O net (fo=1, unset) 0.000 12.508 base_ram_data[23] N21 r base_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.508 ------------------------------------------------------------------- slack 0.846 Slack (MET) : 0.846ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[3]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.115ns (logic 5.541ns (28.987%) route 13.574ns (71.013%)) Logic Levels: 19 (CARRY4=3 LUT2=4 LUT3=1 LUT4=4 LUT5=2 LUT6=5) Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.029ns = ( 17.971 - 20.000 ) Source Clock Delay (SCD): -2.413ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.929 -2.413 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X19Y76 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y76 FDRE (Prop_fdre_C_Q) 0.456 -1.957 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.575 -1.381 u_matmul_axi_slave/mult_inst[1].u_mult_n_65 SLICE_X19Y76 LUT2 (Prop_lut2_I1_O) 0.124 -1.257 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.257 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X19Y76 CARRY4 (Prop_carry4_S[0]_O[2]) 0.547 -0.710 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_8/O[2] net (fo=2, routed) 0.717 0.007 u_matmul_axi_slave/calc_c_result02_out[2] SLICE_X17Y76 LUT2 (Prop_lut2_I0_O) 0.302 0.309 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10/O net (fo=1, routed) 0.000 0.309 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10_n_0 SLICE_X17Y76 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 0.707 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 0.707 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X17Y77 CARRY4 (Prop_carry4_CI_O[0]) 0.222 0.929 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[0] net (fo=13, routed) 1.043 1.972 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_7 SLICE_X22Y74 LUT4 (Prop_lut4_I3_O) 0.325 2.297 r u_matmul_axi_slave/crc_reg[31]_i_85/O net (fo=7, routed) 0.570 2.867 u_matmul_axi_slave/crc_reg[31]_i_85_n_0 SLICE_X22Y75 LUT5 (Prop_lut5_I4_O) 0.328 3.195 r u_matmul_axi_slave/crc_reg[31]_i_84/O net (fo=10, routed) 1.055 4.250 u_matmul_axi_slave/crc32_word_next_return7[2] SLICE_X22Y76 LUT6 (Prop_lut6_I2_O) 0.124 4.374 r u_matmul_axi_slave/crc_reg[7]_i_36/O net (fo=5, routed) 1.140 5.514 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X26Y77 LUT4 (Prop_lut4_I2_O) 0.150 5.664 r u_matmul_axi_slave/crc_reg[15]_i_33/O net (fo=2, routed) 0.627 6.291 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X25Y78 LUT6 (Prop_lut6_I3_O) 0.326 6.617 r u_matmul_axi_slave/crc_reg[31]_i_57/O net (fo=1, routed) 0.774 7.391 u_matmul_axi_slave/crc_reg[31]_i_57_n_0 SLICE_X26Y80 LUT6 (Prop_lut6_I5_O) 0.124 7.515 r u_matmul_axi_slave/crc_reg[31]_i_37/O net (fo=7, routed) 0.799 8.314 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X27Y77 LUT5 (Prop_lut5_I0_O) 0.118 8.432 r u_matmul_axi_slave/crc_reg[31]_i_21/O net (fo=10, routed) 0.866 9.298 u_matmul_axi_slave/crc32_word_next0_return4[2] SLICE_X27Y76 LUT3 (Prop_lut3_I0_O) 0.356 9.654 r u_matmul_axi_slave/crc_reg[7]_i_9/O net (fo=10, routed) 1.064 10.718 u_matmul_axi_slave/crc32_word_next0_return1[0] SLICE_X28Y76 LUT6 (Prop_lut6_I5_O) 0.327 11.045 r u_matmul_axi_slave/crc_reg[14]_i_10/O net (fo=6, routed) 0.967 12.013 u_matmul_axi_slave/crc_reg[14]_i_10_n_0 SLICE_X28Y71 LUT2 (Prop_lut2_I1_O) 0.119 12.132 r u_matmul_axi_slave/crc_reg[31]_i_11/O net (fo=4, routed) 1.029 13.161 u_matmul_axi_slave/crc_reg[31]_i_11_n_0 SLICE_X28Y73 LUT4 (Prop_lut4_I1_O) 0.360 13.521 r u_matmul_axi_slave/crc_reg[28]_i_4/O net (fo=1, routed) 0.641 14.162 u_matmul_axi_slave/crc_reg[28]_i_4_n_0 SLICE_X27Y71 LUT6 (Prop_lut6_I0_O) 0.326 14.488 r u_matmul_axi_slave/crc_reg[28]_i_2/O net (fo=8, routed) 0.857 15.345 u_matmul_axi_slave/crc32_word_next1_return1[5] SLICE_X25Y72 LUT2 (Prop_lut2_I0_O) 0.154 15.499 r u_matmul_axi_slave/crc_reg[29]_i_2/O net (fo=7, routed) 0.849 16.348 u_matmul_axi_slave/crc_reg[29]_i_2_n_0 SLICE_X27Y72 LUT4 (Prop_lut4_I2_O) 0.355 16.703 r u_matmul_axi_slave/crc_reg[3]_i_1/O net (fo=1, routed) 0.000 16.703 u_matmul_axi_slave/crc32_word_next1_return[3] SLICE_X27Y72 FDSE r u_matmul_axi_slave/crc_reg_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.799 17.971 u_matmul_axi_slave/sys_clk SLICE_X27Y72 FDSE r u_matmul_axi_slave/crc_reg_reg[3]/C clock pessimism -0.426 17.544 clock uncertainty -0.071 17.474 SLICE_X27Y72 FDSE (Setup_fdse_C_D) 0.075 17.549 u_matmul_axi_slave/crc_reg_reg[3] ------------------------------------------------------------------- required time 17.549 arrival time -16.703 ------------------------------------------------------------------- slack 0.846 Slack (MET) : 0.897ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[2] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.778ns (logic 6.987ns (47.280%) route 7.791ns (52.720%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 1.238 6.101 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X0Y93 LUT6 (Prop_lut6_I5_O) 0.124 6.225 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[2]_inst_i_1/O net (fo=1, routed) 2.697 8.922 base_ram_be_n_OBUF[2] L23 OBUF (Prop_obuf_I_O) 3.535 12.457 r base_ram_be_n_OBUF[2]_inst/O net (fo=0) 0.000 12.457 base_ram_be_n[2] L23 r base_ram_be_n[2] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.457 ------------------------------------------------------------------- slack 0.897 Slack (MET) : 0.902ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.773ns (logic 6.996ns (47.354%) route 7.778ns (52.646%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.515 8.908 base_ram_data_IOBUF[21]_inst/T M20 OBUFT (TriStatE_obuft_T_O) 3.544 12.452 r base_ram_data_IOBUF[21]_inst/OBUFT/O net (fo=1, unset) 0.000 12.452 base_ram_data[21] M20 r base_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.452 ------------------------------------------------------------------- slack 0.902 Slack (MET) : 0.914ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.762ns (logic 7.022ns (47.567%) route 7.740ns (52.433%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.477 8.870 base_ram_data_IOBUF[3]_inst/T M25 OBUFT (TriStatE_obuft_T_O) 3.570 12.440 r base_ram_data_IOBUF[3]_inst/OBUFT/O net (fo=1, unset) 0.000 12.440 base_ram_data[3] M25 r base_ram_data[3] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.440 ------------------------------------------------------------------- slack 0.914 Slack (MET) : 0.923ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[17] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.753ns (logic 6.998ns (47.433%) route 7.755ns (52.567%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.493 8.886 base_ram_data_IOBUF[17]_inst/T M21 OBUFT (TriStatE_obuft_T_O) 3.546 12.431 r base_ram_data_IOBUF[17]_inst/OBUFT/O net (fo=1, unset) 0.000 12.431 base_ram_data[17] M21 r base_ram_data[17] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.431 ------------------------------------------------------------------- slack 0.923 Slack (MET) : 0.926ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.750ns (logic 6.983ns (47.340%) route 7.767ns (52.660%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.249 7.111 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X1Y127 LUT6 (Prop_lut6_I5_O) 0.124 7.235 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O net (fo=1, routed) 1.663 8.898 base_ram_be_n_OBUF[1] L22 OBUF (Prop_obuf_I_O) 3.531 12.428 r base_ram_be_n_OBUF[1]_inst/O net (fo=0) 0.000 12.428 base_ram_be_n[1] L22 r base_ram_be_n[1] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.428 ------------------------------------------------------------------- slack 0.926 Slack (MET) : 0.967ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[22]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 18.947ns (logic 5.315ns (28.051%) route 13.632ns (71.949%)) Logic Levels: 19 (CARRY4=3 LUT2=3 LUT3=2 LUT4=2 LUT5=4 LUT6=5) Clock Path Skew: -0.046ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.032ns = ( 17.968 - 20.000 ) Source Clock Delay (SCD): -2.413ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.929 -2.413 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X19Y76 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y76 FDRE (Prop_fdre_C_Q) 0.456 -1.957 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.575 -1.381 u_matmul_axi_slave/mult_inst[1].u_mult_n_65 SLICE_X19Y76 LUT2 (Prop_lut2_I1_O) 0.124 -1.257 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.257 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X19Y76 CARRY4 (Prop_carry4_S[0]_O[2]) 0.547 -0.710 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_8/O[2] net (fo=2, routed) 0.717 0.007 u_matmul_axi_slave/calc_c_result02_out[2] SLICE_X17Y76 LUT2 (Prop_lut2_I0_O) 0.302 0.309 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10/O net (fo=1, routed) 0.000 0.309 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10_n_0 SLICE_X17Y76 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 0.707 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 0.707 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X17Y77 CARRY4 (Prop_carry4_CI_O[0]) 0.222 0.929 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[0] net (fo=13, routed) 1.043 1.972 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_7 SLICE_X22Y74 LUT4 (Prop_lut4_I3_O) 0.325 2.297 r u_matmul_axi_slave/crc_reg[31]_i_85/O net (fo=7, routed) 0.570 2.867 u_matmul_axi_slave/crc_reg[31]_i_85_n_0 SLICE_X22Y75 LUT5 (Prop_lut5_I4_O) 0.328 3.195 r u_matmul_axi_slave/crc_reg[31]_i_84/O net (fo=10, routed) 1.055 4.250 u_matmul_axi_slave/crc32_word_next_return7[2] SLICE_X22Y76 LUT6 (Prop_lut6_I2_O) 0.124 4.374 r u_matmul_axi_slave/crc_reg[7]_i_36/O net (fo=5, routed) 1.140 5.514 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X26Y77 LUT4 (Prop_lut4_I2_O) 0.150 5.664 r u_matmul_axi_slave/crc_reg[15]_i_33/O net (fo=2, routed) 0.627 6.291 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X25Y78 LUT6 (Prop_lut6_I3_O) 0.326 6.617 r u_matmul_axi_slave/crc_reg[31]_i_57/O net (fo=1, routed) 0.774 7.391 u_matmul_axi_slave/crc_reg[31]_i_57_n_0 SLICE_X26Y80 LUT6 (Prop_lut6_I5_O) 0.124 7.515 r u_matmul_axi_slave/crc_reg[31]_i_37/O net (fo=7, routed) 0.799 8.314 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X27Y77 LUT5 (Prop_lut5_I0_O) 0.118 8.432 r u_matmul_axi_slave/crc_reg[31]_i_21/O net (fo=10, routed) 0.866 9.298 u_matmul_axi_slave/crc32_word_next0_return4[2] SLICE_X27Y76 LUT3 (Prop_lut3_I0_O) 0.356 9.654 r u_matmul_axi_slave/crc_reg[7]_i_9/O net (fo=10, routed) 1.265 10.919 u_matmul_axi_slave/crc32_word_next0_return1[0] SLICE_X28Y74 LUT2 (Prop_lut2_I1_O) 0.327 11.246 r u_matmul_axi_slave/crc_reg[22]_i_10/O net (fo=1, routed) 0.798 12.044 u_matmul_axi_slave/crc32_word_next0_return0[11] SLICE_X28Y74 LUT6 (Prop_lut6_I1_O) 0.124 12.168 r u_matmul_axi_slave/crc_reg[22]_i_6/O net (fo=6, routed) 0.838 13.006 u_matmul_axi_slave/crc32_word_next1_return7[4] SLICE_X30Y73 LUT5 (Prop_lut5_I2_O) 0.124 13.130 r u_matmul_axi_slave/crc_reg[16]_i_4/O net (fo=10, routed) 0.859 13.990 u_matmul_axi_slave/crc32_word_next1_return4[2] SLICE_X25Y73 LUT5 (Prop_lut5_I4_O) 0.153 14.143 r u_matmul_axi_slave/crc_reg[27]_i_2/O net (fo=9, routed) 0.689 14.832 u_matmul_axi_slave/crc32_word_next1_return1[3] SLICE_X25Y72 LUT3 (Prop_lut3_I0_O) 0.355 15.187 r u_matmul_axi_slave/crc_reg[26]_i_2/O net (fo=5, routed) 1.016 16.203 u_matmul_axi_slave/crc_reg[26]_i_2_n_0 SLICE_X26Y74 LUT6 (Prop_lut6_I5_O) 0.332 16.535 r u_matmul_axi_slave/crc_reg[22]_i_1/O net (fo=1, routed) 0.000 16.535 u_matmul_axi_slave/crc32_word_next1_return[22] SLICE_X26Y74 FDSE r u_matmul_axi_slave/crc_reg_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.796 17.968 u_matmul_axi_slave/sys_clk SLICE_X26Y74 FDSE r u_matmul_axi_slave/crc_reg_reg[22]/C clock pessimism -0.426 17.541 clock uncertainty -0.071 17.471 SLICE_X26Y74 FDSE (Setup_fdse_C_D) 0.031 17.502 u_matmul_axi_slave/crc_reg_reg[22] ------------------------------------------------------------------- required time 17.502 arrival time -16.535 ------------------------------------------------------------------- slack 0.967 Slack (MET) : 0.969ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[2]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 18.850ns (logic 5.083ns (26.965%) route 13.767ns (73.035%)) Logic Levels: 19 (CARRY4=3 LUT2=5 LUT3=1 LUT4=3 LUT5=2 LUT6=5) Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.029ns = ( 17.971 - 20.000 ) Source Clock Delay (SCD): -2.413ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.929 -2.413 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X19Y76 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y76 FDRE (Prop_fdre_C_Q) 0.456 -1.957 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.575 -1.381 u_matmul_axi_slave/mult_inst[1].u_mult_n_65 SLICE_X19Y76 LUT2 (Prop_lut2_I1_O) 0.124 -1.257 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.257 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X19Y76 CARRY4 (Prop_carry4_S[0]_O[2]) 0.547 -0.710 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_8/O[2] net (fo=2, routed) 0.717 0.007 u_matmul_axi_slave/calc_c_result02_out[2] SLICE_X17Y76 LUT2 (Prop_lut2_I0_O) 0.302 0.309 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10/O net (fo=1, routed) 0.000 0.309 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10_n_0 SLICE_X17Y76 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 0.707 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 0.707 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X17Y77 CARRY4 (Prop_carry4_CI_O[0]) 0.222 0.929 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[0] net (fo=13, routed) 1.043 1.972 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_7 SLICE_X22Y74 LUT4 (Prop_lut4_I3_O) 0.325 2.297 r u_matmul_axi_slave/crc_reg[31]_i_85/O net (fo=7, routed) 0.570 2.867 u_matmul_axi_slave/crc_reg[31]_i_85_n_0 SLICE_X22Y75 LUT5 (Prop_lut5_I4_O) 0.328 3.195 r u_matmul_axi_slave/crc_reg[31]_i_84/O net (fo=10, routed) 1.055 4.250 u_matmul_axi_slave/crc32_word_next_return7[2] SLICE_X22Y76 LUT6 (Prop_lut6_I2_O) 0.124 4.374 r u_matmul_axi_slave/crc_reg[7]_i_36/O net (fo=5, routed) 1.140 5.514 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X26Y77 LUT4 (Prop_lut4_I2_O) 0.150 5.664 r u_matmul_axi_slave/crc_reg[15]_i_33/O net (fo=2, routed) 0.627 6.291 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X25Y78 LUT6 (Prop_lut6_I3_O) 0.326 6.617 r u_matmul_axi_slave/crc_reg[31]_i_57/O net (fo=1, routed) 0.774 7.391 u_matmul_axi_slave/crc_reg[31]_i_57_n_0 SLICE_X26Y80 LUT6 (Prop_lut6_I5_O) 0.124 7.515 r u_matmul_axi_slave/crc_reg[31]_i_37/O net (fo=7, routed) 0.799 8.314 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X27Y77 LUT5 (Prop_lut5_I0_O) 0.118 8.432 r u_matmul_axi_slave/crc_reg[31]_i_21/O net (fo=10, routed) 0.866 9.298 u_matmul_axi_slave/crc32_word_next0_return4[2] SLICE_X27Y76 LUT3 (Prop_lut3_I0_O) 0.356 9.654 r u_matmul_axi_slave/crc_reg[7]_i_9/O net (fo=10, routed) 1.265 10.919 u_matmul_axi_slave/crc32_word_next0_return1[0] SLICE_X28Y74 LUT2 (Prop_lut2_I1_O) 0.327 11.246 r u_matmul_axi_slave/crc_reg[22]_i_10/O net (fo=1, routed) 0.798 12.044 u_matmul_axi_slave/crc32_word_next0_return0[11] SLICE_X28Y74 LUT6 (Prop_lut6_I1_O) 0.124 12.168 r u_matmul_axi_slave/crc_reg[22]_i_6/O net (fo=6, routed) 0.838 13.006 u_matmul_axi_slave/crc32_word_next1_return7[4] SLICE_X30Y73 LUT2 (Prop_lut2_I0_O) 0.152 13.158 r u_matmul_axi_slave/crc_reg[27]_i_6/O net (fo=1, routed) 0.982 14.140 u_matmul_axi_slave/crc32_word_next1_return6[11] SLICE_X24Y73 LUT6 (Prop_lut6_I1_O) 0.332 14.472 r u_matmul_axi_slave/crc_reg[27]_i_3/O net (fo=8, routed) 0.337 14.809 u_matmul_axi_slave/crc32_word_next1_return1[4] SLICE_X24Y71 LUT2 (Prop_lut2_I1_O) 0.124 14.933 r u_matmul_axi_slave/crc_reg[28]_i_3/O net (fo=7, routed) 1.001 15.935 u_matmul_axi_slave/crc_reg[28]_i_3_n_0 SLICE_X27Y72 LUT4 (Prop_lut4_I2_O) 0.124 16.059 r u_matmul_axi_slave/crc_reg[2]_i_1/O net (fo=1, routed) 0.379 16.438 u_matmul_axi_slave/crc32_word_next1_return[2] SLICE_X27Y72 FDSE r u_matmul_axi_slave/crc_reg_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.799 17.971 u_matmul_axi_slave/sys_clk SLICE_X27Y72 FDSE r u_matmul_axi_slave/crc_reg_reg[2]/C clock pessimism -0.426 17.544 clock uncertainty -0.071 17.474 SLICE_X27Y72 FDSE (Setup_fdse_C_D) -0.067 17.407 u_matmul_axi_slave/crc_reg_reg[2] ------------------------------------------------------------------- required time 17.407 arrival time -16.438 ------------------------------------------------------------------- slack 0.969 Slack (MET) : 0.980ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[23] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.696ns (logic 6.994ns (47.595%) route 7.701ns (52.405%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.244 8.832 ext_ram_data_IOBUF[23]_inst/T AA15 OBUFT (TriStatE_obuft_T_O) 3.542 12.374 r ext_ram_data_IOBUF[23]_inst/OBUFT/O net (fo=1, unset) 0.000 12.374 ext_ram_data[23] AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.374 ------------------------------------------------------------------- slack 0.980 Slack (MET) : 0.985ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[28] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.691ns (logic 6.988ns (47.567%) route 7.703ns (52.433%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.440 8.833 base_ram_data_IOBUF[28]_inst/T N22 OBUFT (TriStatE_obuft_T_O) 3.536 12.369 r base_ram_data_IOBUF[28]_inst/OBUFT/O net (fo=1, unset) 0.000 12.369 base_ram_data[28] N22 r base_ram_data[28] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.369 ------------------------------------------------------------------- slack 0.985 Slack (MET) : 0.987ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.689ns (logic 6.998ns (47.642%) route 7.691ns (52.358%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.234 8.821 ext_ram_data_IOBUF[21]_inst/T AC16 OBUFT (TriStatE_obuft_T_O) 3.546 12.368 r ext_ram_data_IOBUF[21]_inst/OBUFT/O net (fo=1, unset) 0.000 12.368 ext_ram_data[21] AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.368 ------------------------------------------------------------------- slack 0.987 Slack (MET) : 1.001ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[27] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.675ns (logic 6.975ns (47.527%) route 7.700ns (52.473%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.438 8.831 base_ram_data_IOBUF[27]_inst/T P20 OBUFT (TriStatE_obuft_T_O) 3.523 12.353 r base_ram_data_IOBUF[27]_inst/OBUFT/O net (fo=1, unset) 0.000 12.353 base_ram_data[27] P20 r base_ram_data[27] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.353 ------------------------------------------------------------------- slack 1.001 Slack (MET) : 1.004ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[27]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 18.911ns (logic 5.513ns (29.152%) route 13.398ns (70.848%)) Logic Levels: 19 (CARRY4=3 LUT2=4 LUT3=1 LUT4=4 LUT5=2 LUT6=5) Clock Path Skew: -0.046ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.032ns = ( 17.968 - 20.000 ) Source Clock Delay (SCD): -2.413ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.929 -2.413 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X19Y76 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y76 FDRE (Prop_fdre_C_Q) 0.456 -1.957 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.575 -1.381 u_matmul_axi_slave/mult_inst[1].u_mult_n_65 SLICE_X19Y76 LUT2 (Prop_lut2_I1_O) 0.124 -1.257 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.257 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X19Y76 CARRY4 (Prop_carry4_S[0]_O[2]) 0.547 -0.710 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_8/O[2] net (fo=2, routed) 0.717 0.007 u_matmul_axi_slave/calc_c_result02_out[2] SLICE_X17Y76 LUT2 (Prop_lut2_I0_O) 0.302 0.309 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10/O net (fo=1, routed) 0.000 0.309 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10_n_0 SLICE_X17Y76 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 0.707 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 0.707 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X17Y77 CARRY4 (Prop_carry4_CI_O[0]) 0.222 0.929 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[0] net (fo=13, routed) 1.043 1.972 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_7 SLICE_X22Y74 LUT4 (Prop_lut4_I3_O) 0.325 2.297 r u_matmul_axi_slave/crc_reg[31]_i_85/O net (fo=7, routed) 0.570 2.867 u_matmul_axi_slave/crc_reg[31]_i_85_n_0 SLICE_X22Y75 LUT5 (Prop_lut5_I4_O) 0.328 3.195 r u_matmul_axi_slave/crc_reg[31]_i_84/O net (fo=10, routed) 1.055 4.250 u_matmul_axi_slave/crc32_word_next_return7[2] SLICE_X22Y76 LUT6 (Prop_lut6_I2_O) 0.124 4.374 r u_matmul_axi_slave/crc_reg[7]_i_36/O net (fo=5, routed) 1.140 5.514 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X26Y77 LUT4 (Prop_lut4_I2_O) 0.150 5.664 r u_matmul_axi_slave/crc_reg[15]_i_33/O net (fo=2, routed) 0.627 6.291 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X25Y78 LUT6 (Prop_lut6_I3_O) 0.326 6.617 r u_matmul_axi_slave/crc_reg[31]_i_57/O net (fo=1, routed) 0.774 7.391 u_matmul_axi_slave/crc_reg[31]_i_57_n_0 SLICE_X26Y80 LUT6 (Prop_lut6_I5_O) 0.124 7.515 r u_matmul_axi_slave/crc_reg[31]_i_37/O net (fo=7, routed) 0.799 8.314 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X27Y77 LUT5 (Prop_lut5_I0_O) 0.118 8.432 r u_matmul_axi_slave/crc_reg[31]_i_21/O net (fo=10, routed) 0.866 9.298 u_matmul_axi_slave/crc32_word_next0_return4[2] SLICE_X27Y76 LUT3 (Prop_lut3_I0_O) 0.356 9.654 r u_matmul_axi_slave/crc_reg[7]_i_9/O net (fo=10, routed) 1.064 10.718 u_matmul_axi_slave/crc32_word_next0_return1[0] SLICE_X28Y76 LUT6 (Prop_lut6_I5_O) 0.327 11.045 r u_matmul_axi_slave/crc_reg[14]_i_10/O net (fo=6, routed) 0.967 12.013 u_matmul_axi_slave/crc_reg[14]_i_10_n_0 SLICE_X28Y71 LUT2 (Prop_lut2_I1_O) 0.119 12.132 r u_matmul_axi_slave/crc_reg[31]_i_11/O net (fo=4, routed) 1.029 13.161 u_matmul_axi_slave/crc_reg[31]_i_11_n_0 SLICE_X28Y73 LUT4 (Prop_lut4_I1_O) 0.360 13.521 r u_matmul_axi_slave/crc_reg[28]_i_4/O net (fo=1, routed) 0.641 14.162 u_matmul_axi_slave/crc_reg[28]_i_4_n_0 SLICE_X27Y71 LUT6 (Prop_lut6_I0_O) 0.326 14.488 r u_matmul_axi_slave/crc_reg[28]_i_2/O net (fo=8, routed) 0.857 15.345 u_matmul_axi_slave/crc32_word_next1_return1[5] SLICE_X25Y72 LUT2 (Prop_lut2_I0_O) 0.154 15.499 r u_matmul_axi_slave/crc_reg[29]_i_2/O net (fo=7, routed) 0.672 16.171 u_matmul_axi_slave/crc_reg[29]_i_2_n_0 SLICE_X26Y74 LUT4 (Prop_lut4_I3_O) 0.327 16.498 r u_matmul_axi_slave/crc_reg[27]_i_1/O net (fo=1, routed) 0.000 16.498 u_matmul_axi_slave/crc32_word_next1_return0[25] SLICE_X26Y74 FDSE r u_matmul_axi_slave/crc_reg_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.796 17.968 u_matmul_axi_slave/sys_clk SLICE_X26Y74 FDSE r u_matmul_axi_slave/crc_reg_reg[27]/C clock pessimism -0.426 17.541 clock uncertainty -0.071 17.471 SLICE_X26Y74 FDSE (Setup_fdse_C_D) 0.032 17.503 u_matmul_axi_slave/crc_reg_reg[27] ------------------------------------------------------------------- required time 17.503 arrival time -16.498 ------------------------------------------------------------------- slack 1.004 Slack (MET) : 1.021ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_be_n[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.655ns (logic 7.002ns (47.783%) route 7.652ns (52.217%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 1.611 6.473 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X0Y98 LUT6 (Prop_lut6_I5_O) 0.124 6.597 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ext_ram_be_n_OBUF[1]_inst_i_1/O net (fo=1, routed) 2.186 8.783 ext_ram_be_n_OBUF[1] R25 OBUF (Prop_obuf_I_O) 3.550 12.333 r ext_ram_be_n_OBUF[1]_inst/O net (fo=0) 0.000 12.333 ext_ram_be_n[1] R25 r ext_ram_be_n[1] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.333 ------------------------------------------------------------------- slack 1.021 Slack (MET) : 1.026ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[26]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 18.813ns (logic 5.315ns (28.252%) route 13.498ns (71.748%)) Logic Levels: 19 (CARRY4=3 LUT2=3 LUT3=2 LUT4=3 LUT5=4 LUT6=4) Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.029ns = ( 17.971 - 20.000 ) Source Clock Delay (SCD): -2.413ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.929 -2.413 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X19Y76 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y76 FDRE (Prop_fdre_C_Q) 0.456 -1.957 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.575 -1.381 u_matmul_axi_slave/mult_inst[1].u_mult_n_65 SLICE_X19Y76 LUT2 (Prop_lut2_I1_O) 0.124 -1.257 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.257 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X19Y76 CARRY4 (Prop_carry4_S[0]_O[2]) 0.547 -0.710 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_8/O[2] net (fo=2, routed) 0.717 0.007 u_matmul_axi_slave/calc_c_result02_out[2] SLICE_X17Y76 LUT2 (Prop_lut2_I0_O) 0.302 0.309 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10/O net (fo=1, routed) 0.000 0.309 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10_n_0 SLICE_X17Y76 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 0.707 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 0.707 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X17Y77 CARRY4 (Prop_carry4_CI_O[0]) 0.222 0.929 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[0] net (fo=13, routed) 1.043 1.972 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_7 SLICE_X22Y74 LUT4 (Prop_lut4_I3_O) 0.325 2.297 r u_matmul_axi_slave/crc_reg[31]_i_85/O net (fo=7, routed) 0.570 2.867 u_matmul_axi_slave/crc_reg[31]_i_85_n_0 SLICE_X22Y75 LUT5 (Prop_lut5_I4_O) 0.328 3.195 r u_matmul_axi_slave/crc_reg[31]_i_84/O net (fo=10, routed) 1.055 4.250 u_matmul_axi_slave/crc32_word_next_return7[2] SLICE_X22Y76 LUT6 (Prop_lut6_I2_O) 0.124 4.374 r u_matmul_axi_slave/crc_reg[7]_i_36/O net (fo=5, routed) 1.140 5.514 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X26Y77 LUT4 (Prop_lut4_I2_O) 0.150 5.664 r u_matmul_axi_slave/crc_reg[15]_i_33/O net (fo=2, routed) 0.627 6.291 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X25Y78 LUT6 (Prop_lut6_I3_O) 0.326 6.617 r u_matmul_axi_slave/crc_reg[31]_i_57/O net (fo=1, routed) 0.774 7.391 u_matmul_axi_slave/crc_reg[31]_i_57_n_0 SLICE_X26Y80 LUT6 (Prop_lut6_I5_O) 0.124 7.515 r u_matmul_axi_slave/crc_reg[31]_i_37/O net (fo=7, routed) 0.799 8.314 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X27Y77 LUT5 (Prop_lut5_I0_O) 0.118 8.432 r u_matmul_axi_slave/crc_reg[31]_i_21/O net (fo=10, routed) 0.866 9.298 u_matmul_axi_slave/crc32_word_next0_return4[2] SLICE_X27Y76 LUT3 (Prop_lut3_I0_O) 0.356 9.654 r u_matmul_axi_slave/crc_reg[7]_i_9/O net (fo=10, routed) 1.265 10.919 u_matmul_axi_slave/crc32_word_next0_return1[0] SLICE_X28Y74 LUT2 (Prop_lut2_I1_O) 0.327 11.246 r u_matmul_axi_slave/crc_reg[22]_i_10/O net (fo=1, routed) 0.798 12.044 u_matmul_axi_slave/crc32_word_next0_return0[11] SLICE_X28Y74 LUT6 (Prop_lut6_I1_O) 0.124 12.168 r u_matmul_axi_slave/crc_reg[22]_i_6/O net (fo=6, routed) 0.838 13.006 u_matmul_axi_slave/crc32_word_next1_return7[4] SLICE_X30Y73 LUT5 (Prop_lut5_I2_O) 0.124 13.130 r u_matmul_axi_slave/crc_reg[16]_i_4/O net (fo=10, routed) 0.859 13.990 u_matmul_axi_slave/crc32_word_next1_return4[2] SLICE_X25Y73 LUT5 (Prop_lut5_I4_O) 0.153 14.143 r u_matmul_axi_slave/crc_reg[27]_i_2/O net (fo=9, routed) 0.689 14.832 u_matmul_axi_slave/crc32_word_next1_return1[3] SLICE_X25Y72 LUT3 (Prop_lut3_I0_O) 0.355 15.187 r u_matmul_axi_slave/crc_reg[26]_i_2/O net (fo=5, routed) 0.313 15.500 u_matmul_axi_slave/crc_reg[26]_i_2_n_0 SLICE_X25Y72 LUT4 (Prop_lut4_I3_O) 0.332 15.832 r u_matmul_axi_slave/crc_reg[26]_i_1/O net (fo=1, routed) 0.569 16.400 u_matmul_axi_slave/crc32_word_next1_return0[24] SLICE_X25Y72 FDSE r u_matmul_axi_slave/crc_reg_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.799 17.971 u_matmul_axi_slave/sys_clk SLICE_X25Y72 FDSE r u_matmul_axi_slave/crc_reg_reg[26]/C clock pessimism -0.426 17.544 clock uncertainty -0.071 17.474 SLICE_X25Y72 FDSE (Setup_fdse_C_D) -0.047 17.427 u_matmul_axi_slave/crc_reg_reg[26] ------------------------------------------------------------------- required time 17.427 arrival time -16.400 ------------------------------------------------------------------- slack 1.026 Slack (MET) : 1.034ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.734ns (logic 5.209ns (35.355%) route 9.525ns (64.645%)) Logic Levels: 9 (LUT2=1 LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.928 -2.414 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X20Y76 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.153 2.907 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRC1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.124 3.031 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMC_D1/O net (fo=1, routed) 0.628 3.659 u_matmul_axi_slave/ep_rd_c1_39[65] SLICE_X16Y79 LUT4 (Prop_lut4_I0_O) 0.124 3.783 r u_matmul_axi_slave/ram_reg_i_71/O net (fo=1, routed) 0.666 4.450 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_4 SLICE_X16Y79 LUT5 (Prop_lut5_I3_O) 0.124 4.574 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_63/O net (fo=6, routed) 0.919 5.493 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_0 SLICE_X2Y81 LUT3 (Prop_lut3_I0_O) 0.124 5.617 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O net (fo=2, routed) 3.135 8.752 ext_ram_data_IOBUF[1]_inst/I AE23 OBUFT (Prop_obuft_I_O) 3.568 12.320 r ext_ram_data_IOBUF[1]_inst/OBUFT/O net (fo=1, unset) 0.000 12.320 ext_ram_data[1] AE23 r ext_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.320 ------------------------------------------------------------------- slack 1.034 Slack (MET) : 1.044ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.631ns (logic 7.004ns (47.871%) route 7.627ns (52.129%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.365 8.758 base_ram_data_IOBUF[22]_inst/T N24 OBUFT (TriStatE_obuft_T_O) 3.552 12.310 r base_ram_data_IOBUF[22]_inst/OBUFT/O net (fo=1, unset) 0.000 12.310 base_ram_data[22] N24 r base_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.310 ------------------------------------------------------------------- slack 1.044 Slack (MET) : 1.062ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_we_n (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.614ns (logic 6.996ns (47.869%) route 7.618ns (52.131%)) Logic Levels: 14 (CARRY4=6 LUT2=1 LUT4=1 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.990 5.852 u_axi_ram/u_axi_sram_sp/ax_req_q_burst_reg[0]_0 SLICE_X0Y57 LUT2 (Prop_lut2_I0_O) 0.124 5.976 r u_axi_ram/u_axi_sram_sp/ext_ram_we_n_OBUF_inst_i_1/O net (fo=1, routed) 2.772 8.749 ext_ram_we_n_OBUF AD19 OBUF (Prop_obuf_I_O) 3.544 12.292 r ext_ram_we_n_OBUF_inst/O net (fo=0) 0.000 12.292 ext_ram_we_n AD19 r ext_ram_we_n (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.292 ------------------------------------------------------------------- slack 1.062 Slack (MET) : 1.081ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[19] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.595ns (logic 6.970ns (47.754%) route 7.625ns (52.246%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.363 8.755 base_ram_data_IOBUF[19]_inst/T P19 OBUFT (TriStatE_obuft_T_O) 3.518 12.273 r base_ram_data_IOBUF[19]_inst/OBUFT/O net (fo=1, unset) 0.000 12.273 base_ram_data[19] P19 r base_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.273 ------------------------------------------------------------------- slack 1.081 Slack (MET) : 1.095ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_addr[15] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.581ns (logic 6.885ns (47.217%) route 7.696ns (52.783%)) Logic Levels: 13 (CARRY4=6 LUT4=2 LUT5=1 LUT6=3 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[3]) 0.315 1.646 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3] net (fo=3, routed) 0.811 2.458 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29] SLICE_X0Y69 LUT4 (Prop_lut4_I3_O) 0.307 2.765 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_5/O net (fo=1, routed) 0.000 2.765 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_5_n_0 SLICE_X0Y69 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.335 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.757 4.092 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.405 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[15]_inst_i_2/O net (fo=2, routed) 0.785 5.190 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[15]_inst_i_2_n_0 SLICE_X3Y63 LUT6 (Prop_lut6_I1_O) 0.124 5.314 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[15]_inst_i_1/O net (fo=2, routed) 3.381 8.695 ext_ram_addr_OBUF[15] AF17 OBUF (Prop_obuf_I_O) 3.564 12.259 r ext_ram_addr_OBUF[15]_inst/O net (fo=0) 0.000 12.259 ext_ram_addr[15] AF17 r ext_ram_addr[15] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.259 ------------------------------------------------------------------- slack 1.095 Slack (MET) : 1.095ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[27] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.580ns (logic 7.013ns (48.096%) route 7.568ns (51.904%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.111 8.698 ext_ram_data_IOBUF[27]_inst/T AB21 OBUFT (TriStatE_obuft_T_O) 3.561 12.259 r ext_ram_data_IOBUF[27]_inst/OBUFT/O net (fo=1, unset) 0.000 12.259 ext_ram_data[27] AB21 r ext_ram_data[27] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.259 ------------------------------------------------------------------- slack 1.095 Slack (MET) : 1.109ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ch_mode_reg[3][0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_addr[7] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.666ns (logic 5.196ns (35.428%) route 9.470ns (64.572%)) Logic Levels: 7 (LUT3=1 LUT4=1 LUT6=4 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.854ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.422ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.920 -2.422 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X27Y75 FDRE r u_snix_axil_cdma_mux_8ch/ch_mode_reg[3][0]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y75 FDRE (Prop_fdre_C_Q) 0.456 -1.966 r u_snix_axil_cdma_mux_8ch/ch_mode_reg[3][0]/Q net (fo=3, routed) 1.000 -0.966 u_snix_axil_cdma_mux_8ch/ch_mode_reg[3][31]_0[0] SLICE_X27Y75 LUT6 (Prop_lut6_I2_O) 0.124 -0.842 r u_snix_axil_cdma_mux_8ch/base_ram_be_n_OBUF[3]_inst_i_9/O net (fo=44, routed) 0.845 0.003 u_snix_axil_cdma_mux_8ch/base_ram_be_n_OBUF[3]_inst_i_9_n_0 SLICE_X25Y75 LUT4 (Prop_lut4_I1_O) 0.152 0.155 r u_snix_axil_cdma_mux_8ch/ram_reg_0_3_12_17_i_8__0/O net (fo=47, routed) 1.100 1.254 u_snix_axil_cdma_mux_8ch/u_core_engine/r_len_reg[3] SLICE_X38Y71 LUT6 (Prop_lut6_I5_O) 0.332 1.586 r u_snix_axil_cdma_mux_8ch/u_core_engine/ar_addr_reg[9]_i_2/O net (fo=4, routed) 0.930 2.516 u_Axi_CDC/arFifo/dma_m_araddr[9] SLICE_X29Y69 LUT3 (Prop_lut3_I2_O) 0.150 2.666 r u_Axi_CDC/arFifo/ax_req_q_addr[9]_i_2/O net (fo=3, routed) 1.145 3.811 u_Axi_CDC/arFifo/ram_araddr[7] SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.326 4.137 r u_Axi_CDC/arFifo/base_ram_addr_OBUF[7]_inst_i_3/O net (fo=1, routed) 0.985 5.123 u_axi_ram/u_axi_sram_sp/ext_ram_addr[7] SLICE_X5Y69 LUT6 (Prop_lut6_I2_O) 0.124 5.247 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[7]_inst_i_1/O net (fo=2, routed) 3.466 8.713 ext_ram_addr_OBUF[7] AA18 OBUF (Prop_obuf_I_O) 3.532 12.245 r ext_ram_addr_OBUF[7]_inst/O net (fo=0) 0.000 12.245 ext_ram_addr[7] AA18 r ext_ram_addr[7] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.245 ------------------------------------------------------------------- slack 1.109 Slack (MET) : 1.128ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[25]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 18.786ns (logic 5.513ns (29.346%) route 13.273ns (70.654%)) Logic Levels: 19 (CARRY4=3 LUT2=4 LUT3=2 LUT4=3 LUT5=2 LUT6=5) Clock Path Skew: -0.046ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.032ns = ( 17.968 - 20.000 ) Source Clock Delay (SCD): -2.413ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.929 -2.413 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X19Y76 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y76 FDRE (Prop_fdre_C_Q) 0.456 -1.957 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.575 -1.381 u_matmul_axi_slave/mult_inst[1].u_mult_n_65 SLICE_X19Y76 LUT2 (Prop_lut2_I1_O) 0.124 -1.257 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.257 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X19Y76 CARRY4 (Prop_carry4_S[0]_O[2]) 0.547 -0.710 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_8/O[2] net (fo=2, routed) 0.717 0.007 u_matmul_axi_slave/calc_c_result02_out[2] SLICE_X17Y76 LUT2 (Prop_lut2_I0_O) 0.302 0.309 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10/O net (fo=1, routed) 0.000 0.309 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10_n_0 SLICE_X17Y76 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 0.707 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 0.707 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X17Y77 CARRY4 (Prop_carry4_CI_O[0]) 0.222 0.929 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[0] net (fo=13, routed) 1.043 1.972 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_7 SLICE_X22Y74 LUT4 (Prop_lut4_I3_O) 0.325 2.297 r u_matmul_axi_slave/crc_reg[31]_i_85/O net (fo=7, routed) 0.570 2.867 u_matmul_axi_slave/crc_reg[31]_i_85_n_0 SLICE_X22Y75 LUT5 (Prop_lut5_I4_O) 0.328 3.195 r u_matmul_axi_slave/crc_reg[31]_i_84/O net (fo=10, routed) 1.055 4.250 u_matmul_axi_slave/crc32_word_next_return7[2] SLICE_X22Y76 LUT6 (Prop_lut6_I2_O) 0.124 4.374 r u_matmul_axi_slave/crc_reg[7]_i_36/O net (fo=5, routed) 1.140 5.514 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X26Y77 LUT4 (Prop_lut4_I2_O) 0.150 5.664 r u_matmul_axi_slave/crc_reg[15]_i_33/O net (fo=2, routed) 0.627 6.291 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X25Y78 LUT6 (Prop_lut6_I3_O) 0.326 6.617 r u_matmul_axi_slave/crc_reg[31]_i_57/O net (fo=1, routed) 0.774 7.391 u_matmul_axi_slave/crc_reg[31]_i_57_n_0 SLICE_X26Y80 LUT6 (Prop_lut6_I5_O) 0.124 7.515 r u_matmul_axi_slave/crc_reg[31]_i_37/O net (fo=7, routed) 0.799 8.314 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X27Y77 LUT5 (Prop_lut5_I0_O) 0.118 8.432 r u_matmul_axi_slave/crc_reg[31]_i_21/O net (fo=10, routed) 0.866 9.298 u_matmul_axi_slave/crc32_word_next0_return4[2] SLICE_X27Y76 LUT3 (Prop_lut3_I0_O) 0.356 9.654 r u_matmul_axi_slave/crc_reg[7]_i_9/O net (fo=10, routed) 1.064 10.718 u_matmul_axi_slave/crc32_word_next0_return1[0] SLICE_X28Y76 LUT6 (Prop_lut6_I5_O) 0.327 11.045 r u_matmul_axi_slave/crc_reg[14]_i_10/O net (fo=6, routed) 0.967 12.013 u_matmul_axi_slave/crc_reg[14]_i_10_n_0 SLICE_X28Y71 LUT2 (Prop_lut2_I1_O) 0.119 12.132 r u_matmul_axi_slave/crc_reg[31]_i_11/O net (fo=4, routed) 1.029 13.161 u_matmul_axi_slave/crc_reg[31]_i_11_n_0 SLICE_X28Y73 LUT4 (Prop_lut4_I1_O) 0.360 13.521 r u_matmul_axi_slave/crc_reg[28]_i_4/O net (fo=1, routed) 0.641 14.162 u_matmul_axi_slave/crc_reg[28]_i_4_n_0 SLICE_X27Y71 LUT6 (Prop_lut6_I0_O) 0.326 14.488 r u_matmul_axi_slave/crc_reg[28]_i_2/O net (fo=8, routed) 0.857 15.345 u_matmul_axi_slave/crc32_word_next1_return1[5] SLICE_X25Y72 LUT2 (Prop_lut2_I0_O) 0.154 15.499 r u_matmul_axi_slave/crc_reg[29]_i_2/O net (fo=7, routed) 0.548 16.047 u_matmul_axi_slave/crc_reg[29]_i_2_n_0 SLICE_X24Y74 LUT3 (Prop_lut3_I1_O) 0.327 16.374 r u_matmul_axi_slave/crc_reg[25]_i_1/O net (fo=1, routed) 0.000 16.374 u_matmul_axi_slave/crc32_word_next1_return0[23] SLICE_X24Y74 FDSE r u_matmul_axi_slave/crc_reg_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.796 17.968 u_matmul_axi_slave/sys_clk SLICE_X24Y74 FDSE r u_matmul_axi_slave/crc_reg_reg[25]/C clock pessimism -0.426 17.541 clock uncertainty -0.071 17.471 SLICE_X24Y74 FDSE (Setup_fdse_C_D) 0.031 17.502 u_matmul_axi_slave/crc_reg_reg[25] ------------------------------------------------------------------- required time 17.502 arrival time -16.374 ------------------------------------------------------------------- slack 1.128 Slack (MET) : 1.131ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[6] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.545ns (logic 7.029ns (48.328%) route 7.516ns (51.672%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.059 8.646 ext_ram_data_IOBUF[6]_inst/T AE20 OBUFT (TriStatE_obuft_T_O) 3.577 12.223 r ext_ram_data_IOBUF[6]_inst/OBUFT/O net (fo=1, unset) 0.000 12.223 ext_ram_data[6] AE20 r ext_ram_data[6] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.223 ------------------------------------------------------------------- slack 1.131 Slack (MET) : 1.141ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[26] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.535ns (logic 7.019ns (48.293%) route 7.515ns (51.707%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.058 8.646 ext_ram_data_IOBUF[26]_inst/T AD20 OBUFT (TriStatE_obuft_T_O) 3.567 12.213 r ext_ram_data_IOBUF[26]_inst/OBUFT/O net (fo=1, unset) 0.000 12.213 ext_ram_data[26] AD20 r ext_ram_data[26] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.213 ------------------------------------------------------------------- slack 1.141 Slack (MET) : 1.145ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[29] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.531ns (logic 7.003ns (48.192%) route 7.528ns (51.808%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.266 8.659 base_ram_data_IOBUF[29]_inst/T N23 OBUFT (TriStatE_obuft_T_O) 3.551 12.209 r base_ram_data_IOBUF[29]_inst/OBUFT/O net (fo=1, unset) 0.000 12.209 base_ram_data[29] N23 r base_ram_data[29] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.209 ------------------------------------------------------------------- slack 1.145 Slack (MET) : 1.146ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.530ns (logic 6.979ns (48.034%) route 7.550ns (51.966%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.288 8.681 base_ram_data_IOBUF[16]_inst/T P21 OBUFT (TriStatE_obuft_T_O) 3.527 12.208 r base_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.208 base_ram_data[16] P21 r base_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.208 ------------------------------------------------------------------- slack 1.146 Slack (MET) : 1.195ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[17]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 18.721ns (logic 5.513ns (29.448%) route 13.208ns (70.552%)) Logic Levels: 19 (CARRY4=3 LUT2=4 LUT3=1 LUT4=3 LUT5=2 LUT6=6) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) Source Clock Delay (SCD): -2.413ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.929 -2.413 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X19Y76 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y76 FDRE (Prop_fdre_C_Q) 0.456 -1.957 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.575 -1.381 u_matmul_axi_slave/mult_inst[1].u_mult_n_65 SLICE_X19Y76 LUT2 (Prop_lut2_I1_O) 0.124 -1.257 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.257 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X19Y76 CARRY4 (Prop_carry4_S[0]_O[2]) 0.547 -0.710 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_8/O[2] net (fo=2, routed) 0.717 0.007 u_matmul_axi_slave/calc_c_result02_out[2] SLICE_X17Y76 LUT2 (Prop_lut2_I0_O) 0.302 0.309 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10/O net (fo=1, routed) 0.000 0.309 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10_n_0 SLICE_X17Y76 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 0.707 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 0.707 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X17Y77 CARRY4 (Prop_carry4_CI_O[0]) 0.222 0.929 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[0] net (fo=13, routed) 1.043 1.972 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_7 SLICE_X22Y74 LUT4 (Prop_lut4_I3_O) 0.325 2.297 r u_matmul_axi_slave/crc_reg[31]_i_85/O net (fo=7, routed) 0.570 2.867 u_matmul_axi_slave/crc_reg[31]_i_85_n_0 SLICE_X22Y75 LUT5 (Prop_lut5_I4_O) 0.328 3.195 r u_matmul_axi_slave/crc_reg[31]_i_84/O net (fo=10, routed) 1.055 4.250 u_matmul_axi_slave/crc32_word_next_return7[2] SLICE_X22Y76 LUT6 (Prop_lut6_I2_O) 0.124 4.374 r u_matmul_axi_slave/crc_reg[7]_i_36/O net (fo=5, routed) 1.140 5.514 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X26Y77 LUT4 (Prop_lut4_I2_O) 0.150 5.664 r u_matmul_axi_slave/crc_reg[15]_i_33/O net (fo=2, routed) 0.627 6.291 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X25Y78 LUT6 (Prop_lut6_I3_O) 0.326 6.617 r u_matmul_axi_slave/crc_reg[31]_i_57/O net (fo=1, routed) 0.774 7.391 u_matmul_axi_slave/crc_reg[31]_i_57_n_0 SLICE_X26Y80 LUT6 (Prop_lut6_I5_O) 0.124 7.515 r u_matmul_axi_slave/crc_reg[31]_i_37/O net (fo=7, routed) 0.799 8.314 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X27Y77 LUT5 (Prop_lut5_I0_O) 0.118 8.432 r u_matmul_axi_slave/crc_reg[31]_i_21/O net (fo=10, routed) 0.866 9.298 u_matmul_axi_slave/crc32_word_next0_return4[2] SLICE_X27Y76 LUT3 (Prop_lut3_I0_O) 0.356 9.654 r u_matmul_axi_slave/crc_reg[7]_i_9/O net (fo=10, routed) 1.064 10.718 u_matmul_axi_slave/crc32_word_next0_return1[0] SLICE_X28Y76 LUT6 (Prop_lut6_I5_O) 0.327 11.045 r u_matmul_axi_slave/crc_reg[14]_i_10/O net (fo=6, routed) 0.967 12.013 u_matmul_axi_slave/crc_reg[14]_i_10_n_0 SLICE_X28Y71 LUT2 (Prop_lut2_I1_O) 0.119 12.132 r u_matmul_axi_slave/crc_reg[31]_i_11/O net (fo=4, routed) 1.029 13.161 u_matmul_axi_slave/crc_reg[31]_i_11_n_0 SLICE_X28Y73 LUT4 (Prop_lut4_I1_O) 0.360 13.521 r u_matmul_axi_slave/crc_reg[28]_i_4/O net (fo=1, routed) 0.641 14.162 u_matmul_axi_slave/crc_reg[28]_i_4_n_0 SLICE_X27Y71 LUT6 (Prop_lut6_I0_O) 0.326 14.488 r u_matmul_axi_slave/crc_reg[28]_i_2/O net (fo=8, routed) 0.857 15.345 u_matmul_axi_slave/crc32_word_next1_return1[5] SLICE_X25Y72 LUT2 (Prop_lut2_I0_O) 0.154 15.499 r u_matmul_axi_slave/crc_reg[29]_i_2/O net (fo=7, routed) 0.483 15.982 u_matmul_axi_slave/crc_reg[29]_i_2_n_0 SLICE_X27Y73 LUT6 (Prop_lut6_I4_O) 0.327 16.309 r u_matmul_axi_slave/crc_reg[17]_i_1/O net (fo=1, routed) 0.000 16.309 u_matmul_axi_slave/crc32_word_next1_return[17] SLICE_X27Y73 FDSE r u_matmul_axi_slave/crc_reg_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.798 17.970 u_matmul_axi_slave/sys_clk SLICE_X27Y73 FDSE r u_matmul_axi_slave/crc_reg_reg[17]/C clock pessimism -0.426 17.543 clock uncertainty -0.071 17.473 SLICE_X27Y73 FDSE (Setup_fdse_C_D) 0.031 17.504 u_matmul_axi_slave/crc_reg_reg[17] ------------------------------------------------------------------- required time 17.504 arrival time -16.309 ------------------------------------------------------------------- slack 1.195 Slack (MET) : 1.196ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[29]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 18.718ns (logic 5.513ns (29.452%) route 13.205ns (70.548%)) Logic Levels: 19 (CARRY4=3 LUT2=4 LUT3=1 LUT4=4 LUT5=2 LUT6=5) Clock Path Skew: -0.046ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.032ns = ( 17.968 - 20.000 ) Source Clock Delay (SCD): -2.413ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.929 -2.413 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X19Y76 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y76 FDRE (Prop_fdre_C_Q) 0.456 -1.957 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.575 -1.381 u_matmul_axi_slave/mult_inst[1].u_mult_n_65 SLICE_X19Y76 LUT2 (Prop_lut2_I1_O) 0.124 -1.257 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.257 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X19Y76 CARRY4 (Prop_carry4_S[0]_O[2]) 0.547 -0.710 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_8/O[2] net (fo=2, routed) 0.717 0.007 u_matmul_axi_slave/calc_c_result02_out[2] SLICE_X17Y76 LUT2 (Prop_lut2_I0_O) 0.302 0.309 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10/O net (fo=1, routed) 0.000 0.309 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_10_n_0 SLICE_X17Y76 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 0.707 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 0.707 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X17Y77 CARRY4 (Prop_carry4_CI_O[0]) 0.222 0.929 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[0] net (fo=13, routed) 1.043 1.972 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_7 SLICE_X22Y74 LUT4 (Prop_lut4_I3_O) 0.325 2.297 r u_matmul_axi_slave/crc_reg[31]_i_85/O net (fo=7, routed) 0.570 2.867 u_matmul_axi_slave/crc_reg[31]_i_85_n_0 SLICE_X22Y75 LUT5 (Prop_lut5_I4_O) 0.328 3.195 r u_matmul_axi_slave/crc_reg[31]_i_84/O net (fo=10, routed) 1.055 4.250 u_matmul_axi_slave/crc32_word_next_return7[2] SLICE_X22Y76 LUT6 (Prop_lut6_I2_O) 0.124 4.374 r u_matmul_axi_slave/crc_reg[7]_i_36/O net (fo=5, routed) 1.140 5.514 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X26Y77 LUT4 (Prop_lut4_I2_O) 0.150 5.664 r u_matmul_axi_slave/crc_reg[15]_i_33/O net (fo=2, routed) 0.627 6.291 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X25Y78 LUT6 (Prop_lut6_I3_O) 0.326 6.617 r u_matmul_axi_slave/crc_reg[31]_i_57/O net (fo=1, routed) 0.774 7.391 u_matmul_axi_slave/crc_reg[31]_i_57_n_0 SLICE_X26Y80 LUT6 (Prop_lut6_I5_O) 0.124 7.515 r u_matmul_axi_slave/crc_reg[31]_i_37/O net (fo=7, routed) 0.799 8.314 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X27Y77 LUT5 (Prop_lut5_I0_O) 0.118 8.432 r u_matmul_axi_slave/crc_reg[31]_i_21/O net (fo=10, routed) 0.866 9.298 u_matmul_axi_slave/crc32_word_next0_return4[2] SLICE_X27Y76 LUT3 (Prop_lut3_I0_O) 0.356 9.654 r u_matmul_axi_slave/crc_reg[7]_i_9/O net (fo=10, routed) 1.064 10.718 u_matmul_axi_slave/crc32_word_next0_return1[0] SLICE_X28Y76 LUT6 (Prop_lut6_I5_O) 0.327 11.045 r u_matmul_axi_slave/crc_reg[14]_i_10/O net (fo=6, routed) 0.967 12.013 u_matmul_axi_slave/crc_reg[14]_i_10_n_0 SLICE_X28Y71 LUT2 (Prop_lut2_I1_O) 0.119 12.132 r u_matmul_axi_slave/crc_reg[31]_i_11/O net (fo=4, routed) 1.029 13.161 u_matmul_axi_slave/crc_reg[31]_i_11_n_0 SLICE_X28Y73 LUT4 (Prop_lut4_I1_O) 0.360 13.521 r u_matmul_axi_slave/crc_reg[28]_i_4/O net (fo=1, routed) 0.641 14.162 u_matmul_axi_slave/crc_reg[28]_i_4_n_0 SLICE_X27Y71 LUT6 (Prop_lut6_I0_O) 0.326 14.488 r u_matmul_axi_slave/crc_reg[28]_i_2/O net (fo=8, routed) 0.857 15.345 u_matmul_axi_slave/crc32_word_next1_return1[5] SLICE_X25Y72 LUT2 (Prop_lut2_I0_O) 0.154 15.499 r u_matmul_axi_slave/crc_reg[29]_i_2/O net (fo=7, routed) 0.480 15.979 u_matmul_axi_slave/crc_reg[29]_i_2_n_0 SLICE_X24Y74 LUT4 (Prop_lut4_I3_O) 0.327 16.306 r u_matmul_axi_slave/crc_reg[29]_i_1/O net (fo=1, routed) 0.000 16.306 u_matmul_axi_slave/crc32_word_next1_return0[27] SLICE_X24Y74 FDSE r u_matmul_axi_slave/crc_reg_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.796 17.968 u_matmul_axi_slave/sys_clk SLICE_X24Y74 FDSE r u_matmul_axi_slave/crc_reg_reg[29]/C clock pessimism -0.426 17.541 clock uncertainty -0.071 17.471 SLICE_X24Y74 FDSE (Setup_fdse_C_D) 0.031 17.502 u_matmul_axi_slave/crc_reg_reg[29] ------------------------------------------------------------------- required time 17.502 arrival time -16.306 ------------------------------------------------------------------- slack 1.196 Slack (MET) : 1.212ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.463ns (logic 7.001ns (48.403%) route 7.463ns (51.597%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.200 8.593 base_ram_data_IOBUF[18]_inst/T P23 OBUFT (TriStatE_obuft_T_O) 3.549 12.142 r base_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.142 base_ram_data[18] P23 r base_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.142 ------------------------------------------------------------------- slack 1.212 Slack (MET) : 1.215ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_addr[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.460ns (logic 7.155ns (49.483%) route 7.305ns (50.517%)) Logic Levels: 15 (CARRY4=6 LUT4=1 LUT5=2 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.888 4.424 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X4Y64 LUT6 (Prop_lut6_I5_O) 0.313 4.737 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_6/O net (fo=1, routed) 0.566 5.303 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_6_n_0 SLICE_X4Y62 LUT6 (Prop_lut6_I2_O) 0.124 5.427 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_5/O net (fo=1, routed) 0.300 5.728 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_5_n_0 SLICE_X3Y62 LUT5 (Prop_lut5_I0_O) 0.124 5.852 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_2/O net (fo=2, routed) 0.295 6.146 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_2_n_0 SLICE_X1Y62 LUT6 (Prop_lut6_I1_O) 0.124 6.270 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_1/O net (fo=2, routed) 2.289 8.559 ext_ram_addr_OBUF[3] AD25 OBUF (Prop_obuf_I_O) 3.579 12.139 r ext_ram_addr_OBUF[3]_inst/O net (fo=0) 0.000 12.139 ext_ram_addr[3] AD25 r ext_ram_addr[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.139 ------------------------------------------------------------------- slack 1.215 Slack (MET) : 1.218ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_ce_n (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.458ns (logic 7.260ns (50.214%) route 7.198ns (49.786%)) Logic Levels: 14 (CARRY4=6 LUT2=1 LUT4=1 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X4Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.891 5.753 u_axi_ram/u_axi_sram_sp/ax_req_q_burst_reg[0]_0 SLICE_X0Y65 LUT2 (Prop_lut2_I0_O) 0.150 5.903 r u_axi_ram/u_axi_sram_sp/ext_ram_ce_n_OBUF_inst_i_1/O net (fo=1, routed) 2.451 8.355 ext_ram_ce_n_OBUF AD23 OBUF (Prop_obuf_I_O) 3.782 12.137 r ext_ram_ce_n_OBUF_inst/O net (fo=0) 0.000 12.137 ext_ram_ce_n AD23 r ext_ram_ce_n (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.137 ------------------------------------------------------------------- slack 1.218 Slack (MET) : 1.218ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[4] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.549ns (logic 5.320ns (36.563%) route 9.230ns (63.437%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.928 -2.414 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X20Y76 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.288 3.042 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/ADDRA1 SLICE_X18Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.188 r u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA/O net (fo=1, routed) 0.596 3.784 u_matmul_axi_slave/ep_rd_c0_40[36] SLICE_X18Y82 LUT4 (Prop_lut4_I2_O) 0.328 4.112 r u_matmul_axi_slave/ram_reg_i_55/O net (fo=3, routed) 0.885 4.997 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_10 SLICE_X9Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.121 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[4]_inst_i_1/O net (fo=2, routed) 3.438 8.559 ext_ram_data_IOBUF[4]_inst/I AF22 OBUFT (Prop_obuft_I_O) 3.577 12.136 r ext_ram_data_IOBUF[4]_inst/OBUFT/O net (fo=1, unset) 0.000 12.136 ext_ram_data[4] AF22 r ext_ram_data[4] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.136 ------------------------------------------------------------------- slack 1.218 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sys_clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a DSP48E1/CLK n/a 3.884 20.000 16.116 DSP48_X1Y35 u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg/CLK Min Period n/a DSP48E1/CLK n/a 3.884 20.000 16.116 DSP48_X0Y35 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg/CLK Min Period n/a DSP48E1/CLK n/a 3.884 20.000 16.116 DSP48_X1Y37 u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg/CLK Min Period n/a DSP48E1/CLK n/a 3.884 20.000 16.116 DSP48_X1Y39 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg/CLK Min Period n/a DSP48E1/CLK n/a 3.687 20.000 16.313 DSP48_X0Y39 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Min Period n/a DSP48E1/CLK n/a 3.687 20.000 16.313 DSP48_X1Y33 u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Min Period n/a DSP48E1/CLK n/a 3.687 20.000 16.313 DSP48_X0Y33 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg__0/CLK Min Period n/a DSP48E1/CLK n/a 3.687 20.000 16.313 DSP48_X0Y37 u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0/CLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y34 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y35 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X4Y13 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X3Y13 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X3Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X3Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X3Y11 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X3Y11 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y6 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X3Y34 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X3Y35 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X3Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X3Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y108 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__18/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X25Y95 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__19/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X45Y111 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__2/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X43Y98 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__20/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X19Y95 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[0]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X16Y76 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[0]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X22Y96 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[10]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y93 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[10]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X19Y95 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[11]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X13Y90 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[11]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y94 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[12]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X12Y84 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[12]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X22Y96 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[13]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y93 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[13]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X19Y98 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[14]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X13Y91 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[14]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X22Y96 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[15]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X13Y91 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[15]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X22Y96 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[16]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y91 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[16]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X18Y94 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[1]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X13Y81 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[1]__0/C Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y70 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y70 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y84 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y84 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X16Y70 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X16Y70 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- From Clock: sys_clk To Clock: mlkem_clk_clk_pll Setup : 0 Failing Endpoints, Worst Slack 16.401ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 16.401ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.889ns (logic 1.344ns (46.523%) route 1.545ns (53.477%)) Logic Levels: 0 Clock Path Skew: -0.205ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.507ns = ( 17.493 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.835 17.493 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X48Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y80 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.837 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/O net (fo=1, routed) 1.545 20.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[12] SLICE_X53Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X53Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/C clock pessimism -0.601 37.289 clock uncertainty -0.197 37.092 SLICE_X53Y96 FDRE (Setup_fdre_C_D) -0.309 36.783 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12] ------------------------------------------------------------------- required time 36.783 arrival time -20.382 ------------------------------------------------------------------- slack 16.401 Slack (MET) : 16.543ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.744ns (logic 1.344ns (48.979%) route 1.400ns (51.021%)) Logic Levels: 0 Clock Path Skew: -0.204ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.507ns = ( 17.493 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.835 17.493 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X42Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X42Y81 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.837 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/O net (fo=1, routed) 1.400 20.237 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[48] SLICE_X49Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X49Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X49Y95 FDRE (Setup_fdre_C_D) -0.313 36.780 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48] ------------------------------------------------------------------- required time 36.780 arrival time -20.237 ------------------------------------------------------------------- slack 16.543 Slack (MET) : 16.664ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.681ns (logic 1.344ns (50.131%) route 1.337ns (49.869%)) Logic Levels: 0 Clock Path Skew: -0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 37.885 - 40.000 ) Source Clock Delay (SCD): -2.507ns = ( 17.493 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.835 17.493 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X46Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y80 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.837 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/O net (fo=1, routed) 1.337 20.174 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[42] SLICE_X62Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.713 37.885 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X62Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/C clock pessimism -0.601 37.284 clock uncertainty -0.197 37.087 SLICE_X62Y95 FDRE (Setup_fdre_C_D) -0.249 36.838 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42] ------------------------------------------------------------------- required time 36.838 arrival time -20.174 ------------------------------------------------------------------- slack 16.664 Slack (MET) : 16.701ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.581ns (logic 1.344ns (52.065%) route 1.237ns (47.935%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.120ns = ( 37.880 - 40.000 ) Source Clock Delay (SCD): -2.498ns = ( 17.502 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.844 17.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X46Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y88 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.846 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA/O net (fo=1, routed) 1.237 20.084 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[12] SLICE_X69Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.708 37.880 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X69Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[12]/C clock pessimism -0.601 37.279 clock uncertainty -0.197 37.082 SLICE_X69Y92 FDRE (Setup_fdre_C_D) -0.297 36.785 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[12] ------------------------------------------------------------------- required time 36.785 arrival time -20.084 ------------------------------------------------------------------- slack 16.701 Slack (MET) : 16.710ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.624ns (logic 1.344ns (51.211%) route 1.280ns (48.789%)) Logic Levels: 0 Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 37.884 - 40.000 ) Source Clock Delay (SCD): -2.500ns = ( 17.500 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.842 17.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/WCLK SLICE_X44Y85 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y85 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/O net (fo=1, routed) 1.280 20.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[36] SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.712 37.884 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/C clock pessimism -0.601 37.283 clock uncertainty -0.197 37.086 SLICE_X63Y92 FDRE (Setup_fdre_C_D) -0.251 36.835 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36] ------------------------------------------------------------------- required time 36.835 arrival time -20.125 ------------------------------------------------------------------- slack 16.710 Slack (MET) : 16.727ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.594ns (logic 1.344ns (51.811%) route 1.250ns (48.189%)) Logic Levels: 0 Clock Path Skew: -0.208ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.504ns = ( 17.496 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.838 17.496 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.840 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 1.250 20.090 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[0] SLICE_X53Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X53Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/C clock pessimism -0.601 37.289 clock uncertainty -0.197 37.092 SLICE_X53Y96 FDRE (Setup_fdre_C_D) -0.275 36.817 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0] ------------------------------------------------------------------- required time 36.817 arrival time -20.090 ------------------------------------------------------------------- slack 16.727 Slack (MET) : 16.745ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.572ns (logic 1.336ns (51.943%) route 1.236ns (48.057%)) Logic Levels: 0 Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 37.884 - 40.000 ) Source Clock Delay (SCD): -2.499ns = ( 17.501 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.843 17.501 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X44Y87 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y87 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.837 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O net (fo=1, routed) 1.236 20.073 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34] SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.712 37.884 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/C clock pessimism -0.601 37.283 clock uncertainty -0.197 37.086 SLICE_X63Y92 FDRE (Setup_fdre_C_D) -0.268 36.818 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34] ------------------------------------------------------------------- required time 36.818 arrival time -20.073 ------------------------------------------------------------------- slack 16.745 Slack (MET) : 16.769ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.527ns (logic 1.344ns (53.179%) route 1.183ns (46.821%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.120ns = ( 37.880 - 40.000 ) Source Clock Delay (SCD): -2.500ns = ( 17.500 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.842 17.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK SLICE_X44Y86 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y86 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/O net (fo=1, routed) 1.183 20.028 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[48] SLICE_X67Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.708 37.880 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X67Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/C clock pessimism -0.601 37.279 clock uncertainty -0.197 37.082 SLICE_X67Y92 FDRE (Setup_fdre_C_D) -0.285 36.797 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48] ------------------------------------------------------------------- required time 36.797 arrival time -20.028 ------------------------------------------------------------------- slack 16.769 Slack (MET) : 16.776ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.548ns (logic 1.336ns (52.427%) route 1.212ns (47.573%)) Logic Levels: 0 Clock Path Skew: -0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 37.885 - 40.000 ) Source Clock Delay (SCD): -2.503ns = ( 17.497 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.839 17.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X46Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y83 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.833 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/O net (fo=1, routed) 1.212 20.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[40] SLICE_X63Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.713 37.885 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X63Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/C clock pessimism -0.601 37.284 clock uncertainty -0.197 37.087 SLICE_X63Y95 FDRE (Setup_fdre_C_D) -0.265 36.822 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40] ------------------------------------------------------------------- required time 36.822 arrival time -20.046 ------------------------------------------------------------------- slack 16.776 Slack (MET) : 16.787ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.554ns (logic 1.343ns (52.578%) route 1.211ns (47.422%)) Logic Levels: 0 Clock Path Skew: -0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 37.885 - 40.000 ) Source Clock Delay (SCD): -2.507ns = ( 17.493 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.835 17.493 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X46Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y80 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.836 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/O net (fo=1, routed) 1.211 20.048 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[44] SLICE_X62Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.713 37.885 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X62Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/C clock pessimism -0.601 37.284 clock uncertainty -0.197 37.087 SLICE_X62Y95 FDRE (Setup_fdre_C_D) -0.252 36.835 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44] ------------------------------------------------------------------- required time 36.835 arrival time -20.048 ------------------------------------------------------------------- slack 16.787 Slack (MET) : 16.790ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.494ns (logic 1.343ns (53.842%) route 1.151ns (46.158%)) Logic Levels: 0 Clock Path Skew: -0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 37.885 - 40.000 ) Source Clock Delay (SCD): -2.503ns = ( 17.497 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.839 17.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X46Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y83 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.840 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/O net (fo=1, routed) 1.151 19.992 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[38] SLICE_X63Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.713 37.885 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X63Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/C clock pessimism -0.601 37.284 clock uncertainty -0.197 37.087 SLICE_X63Y95 FDRE (Setup_fdre_C_D) -0.305 36.782 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38] ------------------------------------------------------------------- required time 36.782 arrival time -19.992 ------------------------------------------------------------------- slack 16.790 Slack (MET) : 16.800ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.475ns (logic 1.343ns (54.253%) route 1.132ns (45.747%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.119ns = ( 37.881 - 40.000 ) Source Clock Delay (SCD): -2.498ns = ( 17.502 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.844 17.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y88 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.845 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/O net (fo=1, routed) 1.132 19.978 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[8] SLICE_X69Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.709 37.881 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X69Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/C clock pessimism -0.601 37.280 clock uncertainty -0.197 37.083 SLICE_X69Y93 FDRE (Setup_fdre_C_D) -0.305 36.778 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8] ------------------------------------------------------------------- required time 36.778 arrival time -19.978 ------------------------------------------------------------------- slack 16.800 Slack (MET) : 16.819ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.672ns (logic 1.314ns (49.184%) route 1.358ns (50.816%)) Logic Levels: 0 Clock Path Skew: -0.208ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.503ns = ( 17.497 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.839 17.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y83 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.811 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/O net (fo=1, routed) 1.358 20.169 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[11] SLICE_X49Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X49Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[11]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X49Y95 FDRE (Setup_fdre_C_D) -0.105 36.988 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[11] ------------------------------------------------------------------- required time 36.988 arrival time -20.169 ------------------------------------------------------------------- slack 16.819 Slack (MET) : 16.824ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.442ns (logic 1.343ns (54.997%) route 1.099ns (45.003%)) Logic Levels: 0 Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 37.884 - 40.000 ) Source Clock Delay (SCD): -2.499ns = ( 17.501 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.843 17.501 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X44Y87 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y87 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/O net (fo=1, routed) 1.099 19.943 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[32] SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.712 37.884 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/C clock pessimism -0.601 37.283 clock uncertainty -0.197 37.086 SLICE_X63Y92 FDRE (Setup_fdre_C_D) -0.319 36.767 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32] ------------------------------------------------------------------- required time 36.767 arrival time -19.943 ------------------------------------------------------------------- slack 16.824 Slack (MET) : 16.831ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.454ns (logic 1.336ns (54.432%) route 1.118ns (45.568%)) Logic Levels: 0 Clock Path Skew: -0.208ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.503ns = ( 17.497 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.839 17.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y83 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.833 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/O net (fo=1, routed) 1.118 19.952 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[10] SLICE_X49Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X49Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X49Y95 FDRE (Setup_fdre_C_D) -0.310 36.783 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10] ------------------------------------------------------------------- required time 36.783 arrival time -19.952 ------------------------------------------------------------------- slack 16.831 Slack (MET) : 16.839ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.454ns (logic 1.343ns (54.720%) route 1.111ns (45.280%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.121ns = ( 37.879 - 40.000 ) Source Clock Delay (SCD): -2.498ns = ( 17.502 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.844 17.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X46Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y88 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.845 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/O net (fo=1, routed) 1.111 19.957 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[14] SLICE_X67Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.707 37.879 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X67Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C clock pessimism -0.601 37.278 clock uncertainty -0.197 37.081 SLICE_X67Y90 FDRE (Setup_fdre_C_D) -0.285 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14] ------------------------------------------------------------------- required time 36.796 arrival time -19.957 ------------------------------------------------------------------- slack 16.839 Slack (MET) : 16.849ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.460ns (logic 1.344ns (54.627%) route 1.116ns (45.373%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.119ns = ( 37.881 - 40.000 ) Source Clock Delay (SCD): -2.498ns = ( 17.502 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.844 17.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y88 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.846 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/O net (fo=1, routed) 1.116 19.963 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[6] SLICE_X69Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.709 37.881 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X69Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/C clock pessimism -0.601 37.280 clock uncertainty -0.197 37.083 SLICE_X69Y93 FDRE (Setup_fdre_C_D) -0.271 36.812 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6] ------------------------------------------------------------------- required time 36.812 arrival time -19.963 ------------------------------------------------------------------- slack 16.849 Slack (MET) : 16.866ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.423ns (logic 1.336ns (55.136%) route 1.087ns (44.864%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.122ns = ( 37.878 - 40.000 ) Source Clock Delay (SCD): -2.497ns = ( 17.503 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.845 17.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y91 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.839 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/O net (fo=1, routed) 1.087 19.926 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[4] SLICE_X71Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.706 37.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X71Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/C clock pessimism -0.601 37.277 clock uncertainty -0.197 37.080 SLICE_X71Y93 FDRE (Setup_fdre_C_D) -0.288 36.792 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4] ------------------------------------------------------------------- required time 36.792 arrival time -19.926 ------------------------------------------------------------------- slack 16.866 Slack (MET) : 16.879ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.454ns (logic 1.336ns (54.448%) route 1.118ns (45.552%)) Logic Levels: 0 Clock Path Skew: -0.203ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.508ns = ( 17.492 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.834 17.492 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X42Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X42Y80 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.828 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/O net (fo=1, routed) 1.118 19.946 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[34] SLICE_X47Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X47Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X47Y94 FDRE (Setup_fdre_C_D) -0.268 36.825 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34] ------------------------------------------------------------------- required time 36.825 arrival time -19.946 ------------------------------------------------------------------- slack 16.879 Slack (MET) : 16.881ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.423ns (logic 1.336ns (55.128%) route 1.087ns (44.872%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.121ns = ( 37.879 - 40.000 ) Source Clock Delay (SCD): -2.498ns = ( 17.502 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.844 17.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y88 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.838 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/O net (fo=1, routed) 1.087 19.926 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[10] SLICE_X67Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.707 37.879 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X67Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/C clock pessimism -0.601 37.278 clock uncertainty -0.197 37.081 SLICE_X67Y90 FDRE (Setup_fdre_C_D) -0.274 36.807 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10] ------------------------------------------------------------------- required time 36.807 arrival time -19.926 ------------------------------------------------------------------- slack 16.881 Slack (MET) : 16.889ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.428ns (logic 1.343ns (55.320%) route 1.085ns (44.680%)) Logic Levels: 0 Clock Path Skew: -0.205ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.507ns = ( 17.493 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.835 17.493 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X48Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y80 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.836 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O net (fo=1, routed) 1.085 19.921 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14] SLICE_X53Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X53Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/C clock pessimism -0.601 37.289 clock uncertainty -0.197 37.092 SLICE_X53Y96 FDRE (Setup_fdre_C_D) -0.282 36.810 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14] ------------------------------------------------------------------- required time 36.810 arrival time -19.921 ------------------------------------------------------------------- slack 16.889 Slack (MET) : 16.910ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.625ns (logic 1.309ns (49.872%) route 1.316ns (50.128%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.120ns = ( 37.880 - 40.000 ) Source Clock Delay (SCD): -2.500ns = ( 17.500 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.842 17.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK SLICE_X44Y86 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y86 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.809 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/O net (fo=1, routed) 1.316 20.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[49] SLICE_X69Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.708 37.880 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X69Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/C clock pessimism -0.601 37.279 clock uncertainty -0.197 37.082 SLICE_X69Y92 FDRE (Setup_fdre_C_D) -0.047 37.035 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49] ------------------------------------------------------------------- required time 37.035 arrival time -20.125 ------------------------------------------------------------------- slack 16.910 Slack (MET) : 16.912ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.611ns (logic 1.309ns (50.138%) route 1.302ns (49.862%)) Logic Levels: 0 Clock Path Skew: -0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 37.885 - 40.000 ) Source Clock Delay (SCD): -2.503ns = ( 17.497 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.839 17.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X46Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y83 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.806 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/O net (fo=1, routed) 1.302 20.108 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[37] SLICE_X63Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.713 37.885 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X63Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/C clock pessimism -0.601 37.284 clock uncertainty -0.197 37.087 SLICE_X63Y95 FDRE (Setup_fdre_C_D) -0.067 37.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37] ------------------------------------------------------------------- required time 37.020 arrival time -20.108 ------------------------------------------------------------------- slack 16.912 Slack (MET) : 16.923ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.643ns (logic 1.309ns (49.531%) route 1.334ns (50.469%)) Logic Levels: 0 Clock Path Skew: -0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 37.885 - 40.000 ) Source Clock Delay (SCD): -2.507ns = ( 17.493 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.835 17.493 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X46Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y80 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.802 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/O net (fo=1, routed) 1.334 20.136 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[43] SLICE_X62Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.713 37.885 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X62Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/C clock pessimism -0.601 37.284 clock uncertainty -0.197 37.087 SLICE_X62Y95 FDRE (Setup_fdre_C_D) -0.028 37.059 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43] ------------------------------------------------------------------- required time 37.059 arrival time -20.136 ------------------------------------------------------------------- slack 16.923 Slack (MET) : 16.926ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.384ns (logic 1.343ns (56.333%) route 1.041ns (43.667%)) Logic Levels: 0 Clock Path Skew: -0.203ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.508ns = ( 17.492 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.834 17.492 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X42Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X42Y80 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.835 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/O net (fo=1, routed) 1.041 19.876 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[32] SLICE_X47Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X47Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X47Y94 FDRE (Setup_fdre_C_D) -0.291 36.802 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32] ------------------------------------------------------------------- required time 36.802 arrival time -19.876 ------------------------------------------------------------------- slack 16.926 Slack (MET) : 16.932ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.395ns (logic 1.336ns (55.793%) route 1.059ns (44.207%)) Logic Levels: 0 Clock Path Skew: -0.208ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.504ns = ( 17.496 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.838 17.496 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.832 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/O net (fo=1, routed) 1.059 19.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[4] SLICE_X53Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X53Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/C clock pessimism -0.601 37.289 clock uncertainty -0.197 37.092 SLICE_X53Y96 FDRE (Setup_fdre_C_D) -0.269 36.823 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4] ------------------------------------------------------------------- required time 36.823 arrival time -19.891 ------------------------------------------------------------------- slack 16.932 Slack (MET) : 16.932ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.546ns (logic 1.317ns (51.721%) route 1.229ns (48.279%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.495ns = ( 17.505 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.847 17.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X52Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y98 RAMD32 (Prop_ramd32_CLK_O) 1.317 18.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 1.229 20.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[27] SLICE_X53Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X53Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X53Y99 FDRE (Setup_fdre_C_D) -0.109 36.984 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27] ------------------------------------------------------------------- required time 36.984 arrival time -20.052 ------------------------------------------------------------------- slack 16.932 Slack (MET) : 16.941ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.577ns (logic 1.309ns (50.793%) route 1.268ns (49.207%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.120ns = ( 37.880 - 40.000 ) Source Clock Delay (SCD): -2.498ns = ( 17.502 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.844 17.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y88 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.811 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 1.268 20.080 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[7] SLICE_X69Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.708 37.880 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X69Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/C clock pessimism -0.601 37.279 clock uncertainty -0.197 37.082 SLICE_X69Y92 FDRE (Setup_fdre_C_D) -0.062 37.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7] ------------------------------------------------------------------- required time 37.020 arrival time -20.080 ------------------------------------------------------------------- slack 16.941 Slack (MET) : 16.945ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.369ns (logic 1.336ns (56.404%) route 1.033ns (43.596%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.495ns = ( 17.505 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.847 17.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X52Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y98 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.841 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 1.033 19.874 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[28] SLICE_X53Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X53Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X53Y98 FDRE (Setup_fdre_C_D) -0.274 36.819 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28] ------------------------------------------------------------------- required time 36.819 arrival time -19.874 ------------------------------------------------------------------- slack 16.945 Slack (MET) : 16.949ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.570ns (logic 1.309ns (50.931%) route 1.261ns (49.069%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.120ns = ( 37.880 - 40.000 ) Source Clock Delay (SCD): -2.498ns = ( 17.502 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.844 17.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X46Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y88 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.811 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/O net (fo=1, routed) 1.261 20.073 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[13] SLICE_X69Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.708 37.880 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X69Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/C clock pessimism -0.601 37.279 clock uncertainty -0.197 37.082 SLICE_X69Y92 FDRE (Setup_fdre_C_D) -0.061 37.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13] ------------------------------------------------------------------- required time 37.021 arrival time -20.073 ------------------------------------------------------------------- slack 16.949 Slack (MET) : 16.955ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.567ns (logic 1.317ns (51.308%) route 1.250ns (48.692%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.120ns = ( 37.880 - 40.000 ) Source Clock Delay (SCD): -2.498ns = ( 17.502 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.844 17.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X46Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y88 RAMD32 (Prop_ramd32_CLK_O) 1.317 18.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/O net (fo=1, routed) 1.250 20.069 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[15] SLICE_X69Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.708 37.880 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X69Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/C clock pessimism -0.601 37.279 clock uncertainty -0.197 37.082 SLICE_X69Y92 FDRE (Setup_fdre_C_D) -0.058 37.024 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15] ------------------------------------------------------------------- required time 37.024 arrival time -20.069 ------------------------------------------------------------------- slack 16.955 Slack (MET) : 16.957ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.388ns (logic 1.344ns (56.275%) route 1.044ns (43.725%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.118ns = ( 37.882 - 40.000 ) Source Clock Delay (SCD): -2.497ns = ( 17.503 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.845 17.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/WCLK SLICE_X56Y96 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y96 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.847 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/O net (fo=1, routed) 1.044 19.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[36] SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.710 37.882 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/C clock pessimism -0.601 37.281 clock uncertainty -0.197 37.084 SLICE_X68Y98 FDRE (Setup_fdre_C_D) -0.235 36.849 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36] ------------------------------------------------------------------- required time 36.849 arrival time -19.892 ------------------------------------------------------------------- slack 16.957 Slack (MET) : 16.965ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.528ns (logic 1.314ns (51.984%) route 1.214ns (48.016%)) Logic Levels: 0 Clock Path Skew: -0.208ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.504ns = ( 17.496 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.838 17.496 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/O net (fo=1, routed) 1.214 20.024 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[5] SLICE_X50Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X50Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/C clock pessimism -0.601 37.289 clock uncertainty -0.197 37.092 SLICE_X50Y96 FDRE (Setup_fdre_C_D) -0.103 36.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5] ------------------------------------------------------------------- required time 36.989 arrival time -20.024 ------------------------------------------------------------------- slack 16.965 Slack (MET) : 16.993ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.538ns (logic 1.314ns (51.775%) route 1.224ns (48.225%)) Logic Levels: 0 Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.496ns = ( 17.504 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 17.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X52Y96 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y96 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.818 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/O net (fo=1, routed) 1.224 20.042 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[35] SLICE_X53Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X53Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X53Y97 FDRE (Setup_fdre_C_D) -0.058 37.035 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35] ------------------------------------------------------------------- required time 37.035 arrival time -20.042 ------------------------------------------------------------------- slack 16.993 Slack (MET) : 17.014ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.275ns (logic 1.343ns (59.031%) route 0.932ns (40.969%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.119ns = ( 37.881 - 40.000 ) Source Clock Delay (SCD): -2.497ns = ( 17.503 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.845 17.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y91 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.846 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/O net (fo=1, routed) 0.932 19.778 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[2] SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.709 37.881 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/C clock pessimism -0.601 37.280 clock uncertainty -0.197 37.083 SLICE_X67Y93 FDRE (Setup_fdre_C_D) -0.291 36.792 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2] ------------------------------------------------------------------- required time 36.792 arrival time -19.778 ------------------------------------------------------------------- slack 17.014 Slack (MET) : 17.018ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.510ns (logic 1.317ns (52.463%) route 1.193ns (47.537%)) Logic Levels: 0 Clock Path Skew: -0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 37.885 - 40.000 ) Source Clock Delay (SCD): -2.503ns = ( 17.497 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.839 17.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X46Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y83 RAMD32 (Prop_ramd32_CLK_O) 1.317 18.814 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/O net (fo=1, routed) 1.193 20.008 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[39] SLICE_X63Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.713 37.885 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X63Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/C clock pessimism -0.601 37.284 clock uncertainty -0.197 37.087 SLICE_X63Y95 FDRE (Setup_fdre_C_D) -0.061 37.026 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39] ------------------------------------------------------------------- required time 37.026 arrival time -20.008 ------------------------------------------------------------------- slack 17.018 Slack (MET) : 17.027ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.511ns (logic 1.309ns (52.130%) route 1.202ns (47.870%)) Logic Levels: 0 Clock Path Skew: -0.205ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.507ns = ( 17.493 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.835 17.493 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X48Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y80 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.802 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/O net (fo=1, routed) 1.202 20.004 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[13] SLICE_X53Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X53Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/C clock pessimism -0.601 37.289 clock uncertainty -0.197 37.092 SLICE_X53Y96 FDRE (Setup_fdre_C_D) -0.061 37.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13] ------------------------------------------------------------------- required time 37.031 arrival time -20.004 ------------------------------------------------------------------- slack 17.027 Slack (MET) : 17.039ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.240ns (logic 1.344ns (59.988%) route 0.896ns (40.012%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.120ns = ( 37.880 - 40.000 ) Source Clock Delay (SCD): -2.497ns = ( 17.503 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.845 17.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y91 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.847 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 0.896 19.744 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[0] SLICE_X69Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.708 37.880 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X69Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/C clock pessimism -0.601 37.279 clock uncertainty -0.197 37.082 SLICE_X69Y92 FDRE (Setup_fdre_C_D) -0.299 36.783 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0] ------------------------------------------------------------------- required time 36.783 arrival time -19.744 ------------------------------------------------------------------- slack 17.039 Slack (MET) : 17.046ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.473ns (logic 1.317ns (53.250%) route 1.156ns (46.750%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.119ns = ( 37.881 - 40.000 ) Source Clock Delay (SCD): -2.498ns = ( 17.502 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.844 17.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y88 RAMD32 (Prop_ramd32_CLK_O) 1.317 18.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/O net (fo=1, routed) 1.156 19.976 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[9] SLICE_X69Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.709 37.881 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X69Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/C clock pessimism -0.601 37.280 clock uncertainty -0.197 37.083 SLICE_X69Y93 FDRE (Setup_fdre_C_D) -0.061 37.022 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9] ------------------------------------------------------------------- required time 37.022 arrival time -19.976 ------------------------------------------------------------------- slack 17.046 Slack (MET) : 17.065ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.240ns (logic 1.343ns (59.952%) route 0.897ns (40.048%)) Logic Levels: 0 Clock Path Skew: -0.208ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.504ns = ( 17.496 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.838 17.496 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.839 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/O net (fo=1, routed) 0.897 19.737 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[2] SLICE_X51Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X51Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/C clock pessimism -0.601 37.289 clock uncertainty -0.197 37.092 SLICE_X51Y94 FDRE (Setup_fdre_C_D) -0.291 36.801 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2] ------------------------------------------------------------------- required time 36.801 arrival time -19.737 ------------------------------------------------------------------- slack 17.065 Slack (MET) : 17.071ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.451ns (logic 1.314ns (53.618%) route 1.137ns (46.382%)) Logic Levels: 0 Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.496ns = ( 17.504 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 17.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X52Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y95 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.818 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 1.137 19.955 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[23] SLICE_X53Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X53Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X53Y97 FDRE (Setup_fdre_C_D) -0.067 37.026 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23] ------------------------------------------------------------------- required time 37.026 arrival time -19.955 ------------------------------------------------------------------- slack 17.071 Slack (MET) : 17.078ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.474ns (logic 1.317ns (53.243%) route 1.157ns (46.757%)) Logic Levels: 0 Clock Path Skew: -0.205ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.507ns = ( 17.493 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.835 17.493 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X48Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y80 RAMD32 (Prop_ramd32_CLK_O) 1.317 18.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/O net (fo=1, routed) 1.157 19.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[15] SLICE_X53Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X53Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/C clock pessimism -0.601 37.289 clock uncertainty -0.197 37.092 SLICE_X53Y96 FDRE (Setup_fdre_C_D) -0.047 37.045 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15] ------------------------------------------------------------------- required time 37.045 arrival time -19.967 ------------------------------------------------------------------- slack 17.078 Slack (MET) : 17.085ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.458ns (logic 1.314ns (53.460%) route 1.144ns (46.540%)) Logic Levels: 0 Clock Path Skew: -0.203ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.508ns = ( 17.492 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.834 17.492 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X42Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X42Y80 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.806 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/O net (fo=1, routed) 1.144 19.950 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[35] SLICE_X47Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X47Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X47Y94 FDRE (Setup_fdre_C_D) -0.058 37.035 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35] ------------------------------------------------------------------- required time 37.035 arrival time -19.950 ------------------------------------------------------------------- slack 17.085 Slack (MET) : 17.087ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.417ns (logic 1.317ns (54.487%) route 1.100ns (45.513%)) Logic Levels: 0 Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 37.884 - 40.000 ) Source Clock Delay (SCD): -2.499ns = ( 17.501 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.843 17.501 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X44Y87 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y87 RAMD32 (Prop_ramd32_CLK_O) 1.317 18.818 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/O net (fo=1, routed) 1.100 19.918 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[33] SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.712 37.884 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/C clock pessimism -0.601 37.283 clock uncertainty -0.197 37.086 SLICE_X63Y92 FDRE (Setup_fdre_C_D) -0.081 37.005 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33] ------------------------------------------------------------------- required time 37.005 arrival time -19.918 ------------------------------------------------------------------- slack 17.087 Slack (MET) : 17.097ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.462ns (logic 1.314ns (53.369%) route 1.148ns (46.631%)) Logic Levels: 0 Clock Path Skew: -0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 37.885 - 40.000 ) Source Clock Delay (SCD): -2.503ns = ( 17.497 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.839 17.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X46Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y83 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.811 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/O net (fo=1, routed) 1.148 19.960 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[41] SLICE_X62Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.713 37.885 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X62Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/C clock pessimism -0.601 37.284 clock uncertainty -0.197 37.087 SLICE_X62Y95 FDRE (Setup_fdre_C_D) -0.031 37.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41] ------------------------------------------------------------------- required time 37.056 arrival time -19.960 ------------------------------------------------------------------- slack 17.097 Slack (MET) : 17.097ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.401ns (logic 1.314ns (54.733%) route 1.087ns (45.267%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.121ns = ( 37.879 - 40.000 ) Source Clock Delay (SCD): -2.498ns = ( 17.502 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.844 17.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y88 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/O net (fo=1, routed) 1.087 19.903 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[11] SLICE_X67Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.707 37.879 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X67Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/C clock pessimism -0.601 37.278 clock uncertainty -0.197 37.081 SLICE_X67Y90 FDRE (Setup_fdre_C_D) -0.081 37.000 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11] ------------------------------------------------------------------- required time 37.000 arrival time -19.903 ------------------------------------------------------------------- slack 17.097 Slack (MET) : 17.102ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.429ns (logic 1.314ns (54.096%) route 1.115ns (45.904%)) Logic Levels: 0 Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.497ns = ( 17.503 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.845 17.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X60Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y95 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.817 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 1.115 19.932 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[5] SLICE_X61Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X61Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/C clock pessimism -0.601 37.289 clock uncertainty -0.197 37.092 SLICE_X61Y97 FDRE (Setup_fdre_C_D) -0.058 37.034 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5] ------------------------------------------------------------------- required time 37.034 arrival time -19.932 ------------------------------------------------------------------- slack 17.102 Slack (MET) : 17.103ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.423ns (logic 1.314ns (54.222%) route 1.109ns (45.778%)) Logic Levels: 0 Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 37.884 - 40.000 ) Source Clock Delay (SCD): -2.499ns = ( 17.501 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.843 17.501 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X44Y87 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y87 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.815 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/O net (fo=1, routed) 1.109 19.925 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[35] SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.712 37.884 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/C clock pessimism -0.601 37.283 clock uncertainty -0.197 37.086 SLICE_X63Y92 FDRE (Setup_fdre_C_D) -0.058 37.028 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35] ------------------------------------------------------------------- required time 37.028 arrival time -19.925 ------------------------------------------------------------------- slack 17.103 Slack (MET) : 17.105ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.400ns (logic 1.314ns (54.740%) route 1.086ns (45.260%)) Logic Levels: 0 Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.495ns = ( 17.505 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.847 17.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X52Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y98 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 1.086 19.906 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[29] SLICE_X54Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X54Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/C clock pessimism -0.601 37.289 clock uncertainty -0.197 37.092 SLICE_X54Y98 FDRE (Setup_fdre_C_D) -0.081 37.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29] ------------------------------------------------------------------- required time 37.011 arrival time -19.906 ------------------------------------------------------------------- slack 17.105 Slack (MET) : 17.110ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 2.400ns (logic 1.309ns (54.550%) route 1.091ns (45.450%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.122ns = ( 37.878 - 40.000 ) Source Clock Delay (SCD): -2.497ns = ( 17.503 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.845 17.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y91 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.812 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/O net (fo=1, routed) 1.091 19.903 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[1] SLICE_X71Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.706 37.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X71Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/C clock pessimism -0.601 37.277 clock uncertainty -0.197 37.080 SLICE_X71Y93 FDRE (Setup_fdre_C_D) -0.067 37.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1] ------------------------------------------------------------------- required time 37.013 arrival time -19.903 ------------------------------------------------------------------- slack 17.110 --------------------------------------------------------------------------------------------------- From Clock: mlkem_clk_clk_pll To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 16.929ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 16.929ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.409ns (logic 1.336ns (55.465%) route 1.073ns (44.535%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 17.889 - 20.000 ) Source Clock Delay (SCD): -2.497ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X56Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y94 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.161 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 1.073 -0.088 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28] SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.717 17.889 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/C clock pessimism -0.601 17.288 clock uncertainty -0.197 17.091 SLICE_X55Y93 FDRE (Setup_fdre_C_D) -0.250 16.841 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28] ------------------------------------------------------------------- required time 16.841 arrival time 0.088 ------------------------------------------------------------------- slack 16.929 Slack (MET) : 17.005ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.308ns (logic 1.343ns (58.200%) route 0.965ns (41.800%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.122ns = ( 17.878 - 20.000 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X62Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y94 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.159 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 0.965 -0.194 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[14] SLICE_X62Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.706 17.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/C clock pessimism -0.601 17.277 clock uncertainty -0.197 17.080 SLICE_X62Y83 FDRE (Setup_fdre_C_D) -0.269 16.811 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14] ------------------------------------------------------------------- required time 16.811 arrival time 0.194 ------------------------------------------------------------------- slack 17.005 Slack (MET) : 17.085ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.409ns (logic 1.317ns (54.659%) route 1.092ns (45.341%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 17.889 - 20.000 ) Source Clock Delay (SCD): -2.497ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.180 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 1.092 -0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.717 17.889 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/C clock pessimism -0.601 17.288 clock uncertainty -0.197 17.091 SLICE_X55Y93 FDRE (Setup_fdre_C_D) -0.093 16.998 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] ------------------------------------------------------------------- required time 16.998 arrival time 0.087 ------------------------------------------------------------------- slack 17.085 Slack (MET) : 17.096ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.179ns (logic 1.336ns (61.314%) route 0.843ns (38.686%)) Logic Levels: 0 Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 ) Source Clock Delay (SCD): -2.503ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 0.843 -0.324 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[10] SLICE_X65Y87 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.708 17.880 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X65Y87 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/C clock pessimism -0.601 17.279 clock uncertainty -0.197 17.082 SLICE_X65Y87 FDRE (Setup_fdre_C_D) -0.310 16.772 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10] ------------------------------------------------------------------- required time 16.772 arrival time 0.324 ------------------------------------------------------------------- slack 17.096 Slack (MET) : 17.096ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.447ns (logic 1.317ns (53.824%) route 1.130ns (46.176%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X62Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y94 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 1.130 -0.055 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.712 17.884 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/C clock pessimism -0.601 17.283 clock uncertainty -0.197 17.086 SLICE_X62Y92 FDRE (Setup_fdre_C_D) -0.045 17.041 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] ------------------------------------------------------------------- required time 17.041 arrival time 0.055 ------------------------------------------------------------------- slack 17.096 Slack (MET) : 17.099ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.459ns (logic 1.314ns (53.433%) route 1.145ns (46.567%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.188 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 1.145 -0.042 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5] SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.712 17.884 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/C clock pessimism -0.601 17.283 clock uncertainty -0.197 17.086 SLICE_X62Y92 FDRE (Setup_fdre_C_D) -0.030 17.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5] ------------------------------------------------------------------- required time 17.056 arrival time 0.042 ------------------------------------------------------------------- slack 17.099 Slack (MET) : 17.114ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.237ns (logic 1.344ns (60.078%) route 0.893ns (39.922%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.122ns = ( 17.878 - 20.000 ) Source Clock Delay (SCD): -2.503ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.159 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 0.893 -0.265 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] SLICE_X62Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.706 17.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C clock pessimism -0.601 17.277 clock uncertainty -0.197 17.080 SLICE_X62Y83 FDRE (Setup_fdre_C_D) -0.232 16.848 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6] ------------------------------------------------------------------- required time 16.848 arrival time 0.265 ------------------------------------------------------------------- slack 17.114 Slack (MET) : 17.121ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.374ns (logic 1.314ns (55.339%) route 1.060ns (44.661%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 17.889 - 20.000 ) Source Clock Delay (SCD): -2.497ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.183 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 1.060 -0.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.717 17.889 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/C clock pessimism -0.601 17.288 clock uncertainty -0.197 17.091 SLICE_X55Y93 FDRE (Setup_fdre_C_D) -0.092 16.999 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] ------------------------------------------------------------------- required time 16.999 arrival time 0.122 ------------------------------------------------------------------- slack 17.121 Slack (MET) : 17.124ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.423ns (logic 1.314ns (54.223%) route 1.109ns (45.777%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 17.889 - 20.000 ) Source Clock Delay (SCD): -2.497ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X56Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y94 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.183 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 1.109 -0.073 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[29] SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.717 17.889 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/C clock pessimism -0.601 17.288 clock uncertainty -0.197 17.091 SLICE_X55Y93 FDRE (Setup_fdre_C_D) -0.040 17.051 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29] ------------------------------------------------------------------- required time 17.051 arrival time 0.073 ------------------------------------------------------------------- slack 17.124 Slack (MET) : 17.125ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.433ns (logic 1.317ns (54.122%) route 1.116ns (45.878%)) Logic Levels: 0 Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 17.888 - 20.000 ) Source Clock Delay (SCD): -2.497ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X56Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y94 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.180 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 1.116 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[27] SLICE_X56Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.716 17.888 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X56Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/C clock pessimism -0.601 17.287 clock uncertainty -0.197 17.090 SLICE_X56Y92 FDRE (Setup_fdre_C_D) -0.028 17.062 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27] ------------------------------------------------------------------- required time 17.062 arrival time 0.063 ------------------------------------------------------------------- slack 17.125 Slack (MET) : 17.128ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.219ns (logic 1.344ns (60.565%) route 0.875ns (39.435%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.122ns = ( 17.878 - 20.000 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 0.875 -0.282 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[0] SLICE_X62Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.706 17.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/C clock pessimism -0.601 17.277 clock uncertainty -0.197 17.080 SLICE_X62Y83 FDRE (Setup_fdre_C_D) -0.235 16.845 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0] ------------------------------------------------------------------- required time 16.845 arrival time 0.282 ------------------------------------------------------------------- slack 17.128 Slack (MET) : 17.162ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.318ns (logic 1.317ns (56.824%) route 1.001ns (43.176%)) Logic Levels: 0 Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 ) Source Clock Delay (SCD): -2.503ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.186 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 1.001 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[9] SLICE_X65Y87 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.708 17.880 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X65Y87 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/C clock pessimism -0.601 17.279 clock uncertainty -0.197 17.082 SLICE_X65Y87 FDRE (Setup_fdre_C_D) -0.105 16.977 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9] ------------------------------------------------------------------- required time 16.977 arrival time 0.185 ------------------------------------------------------------------- slack 17.162 Slack (MET) : 17.181ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.087ns (logic 1.343ns (64.338%) route 0.744ns (35.662%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 17.889 - 20.000 ) Source Clock Delay (SCD): -2.497ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.154 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 0.744 -0.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[20] SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.717 17.889 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/C clock pessimism -0.601 17.288 clock uncertainty -0.197 17.091 SLICE_X55Y93 FDRE (Setup_fdre_C_D) -0.319 16.772 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20] ------------------------------------------------------------------- required time 16.772 arrival time 0.409 ------------------------------------------------------------------- slack 17.181 Slack (MET) : 17.190ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.313ns (logic 1.317ns (56.947%) route 0.996ns (43.053%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.113ns = ( 17.887 - 20.000 ) Source Clock Delay (SCD): -2.495ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.847 -2.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y93 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.178 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O net (fo=1, routed) 0.996 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.715 17.887 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C clock pessimism -0.601 17.286 clock uncertainty -0.197 17.089 SLICE_X43Y88 FDRE (Setup_fdre_C_D) -0.081 17.008 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33] ------------------------------------------------------------------- required time 17.008 arrival time 0.182 ------------------------------------------------------------------- slack 17.190 Slack (MET) : 17.192ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.128ns (logic 1.336ns (62.777%) route 0.792ns (37.223%)) Logic Levels: 0 Clock Path Skew: -0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 17.889 - 20.000 ) Source Clock Delay (SCD): -2.503ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK SLICE_X64Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y95 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O net (fo=1, routed) 0.792 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] SLICE_X57Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.717 17.889 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk SLICE_X57Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C clock pessimism -0.601 17.288 clock uncertainty -0.197 17.091 SLICE_X57Y95 FDRE (Setup_fdre_C_D) -0.274 16.817 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4] ------------------------------------------------------------------- required time 16.817 arrival time 0.374 ------------------------------------------------------------------- slack 17.192 Slack (MET) : 17.201ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.087ns (logic 1.336ns (64.021%) route 0.751ns (35.979%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 17.889 - 20.000 ) Source Clock Delay (SCD): -2.497ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.161 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.751 -0.410 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.717 17.889 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C clock pessimism -0.601 17.288 clock uncertainty -0.197 17.091 SLICE_X55Y93 FDRE (Setup_fdre_C_D) -0.300 16.791 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22] ------------------------------------------------------------------- required time 16.791 arrival time 0.410 ------------------------------------------------------------------- slack 17.201 Slack (MET) : 17.220ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.073ns (logic 1.343ns (64.788%) route 0.730ns (35.212%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.113ns = ( 17.887 - 20.000 ) Source Clock Delay (SCD): -2.495ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.847 -2.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y93 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.152 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 0.730 -0.422 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[32] SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.715 17.887 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/C clock pessimism -0.601 17.286 clock uncertainty -0.197 17.089 SLICE_X43Y88 FDRE (Setup_fdre_C_D) -0.291 16.798 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32] ------------------------------------------------------------------- required time 16.798 arrival time 0.422 ------------------------------------------------------------------- slack 17.220 Slack (MET) : 17.227ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.138ns (logic 1.336ns (62.488%) route 0.802ns (37.512%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.166 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 0.802 -0.364 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[4] SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.712 17.884 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/C clock pessimism -0.601 17.283 clock uncertainty -0.197 17.086 SLICE_X62Y92 FDRE (Setup_fdre_C_D) -0.223 16.863 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4] ------------------------------------------------------------------- required time 16.863 arrival time 0.364 ------------------------------------------------------------------- slack 17.227 Slack (MET) : 17.251ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.291ns (logic 1.314ns (57.365%) route 0.977ns (42.635%)) Logic Levels: 0 Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.503ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.189 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 0.977 -0.212 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.712 17.884 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/C clock pessimism -0.601 17.283 clock uncertainty -0.197 17.086 SLICE_X62Y92 FDRE (Setup_fdre_C_D) -0.047 17.039 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11] ------------------------------------------------------------------- required time 17.039 arrival time 0.212 ------------------------------------------------------------------- slack 17.251 Slack (MET) : 17.253ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.253ns (logic 1.309ns (58.112%) route 0.944ns (41.888%)) Logic Levels: 0 Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 17.890 - 20.000 ) Source Clock Delay (SCD): -2.495ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.847 -2.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y93 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.186 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.944 -0.242 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] SLICE_X47Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.718 17.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X47Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/C clock pessimism -0.601 17.289 clock uncertainty -0.197 17.092 SLICE_X47Y92 FDRE (Setup_fdre_C_D) -0.081 17.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31] ------------------------------------------------------------------- required time 17.011 arrival time 0.242 ------------------------------------------------------------------- slack 17.253 Slack (MET) : 17.263ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.230ns (logic 0.518ns (23.224%) route 1.712ns (76.776%)) Logic Levels: 0 Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.503ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X64Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y93 FDCE (Prop_fdce_C_Q) 0.518 -1.985 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 1.712 -0.272 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[0] SLICE_X65Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.712 17.884 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X65Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.601 17.283 clock uncertainty -0.197 17.086 SLICE_X65Y94 FDCE (Setup_fdce_C_D) -0.095 16.991 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 16.991 arrival time 0.272 ------------------------------------------------------------------- slack 17.263 Slack (MET) : 17.266ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.051ns (logic 1.343ns (65.489%) route 0.708ns (34.511%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.113ns = ( 17.887 - 20.000 ) Source Clock Delay (SCD): -2.495ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.847 -2.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X48Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y93 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.152 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O net (fo=1, routed) 0.708 -0.444 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.715 17.887 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/C clock pessimism -0.601 17.286 clock uncertainty -0.197 17.089 SLICE_X43Y88 FDRE (Setup_fdre_C_D) -0.267 16.822 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] ------------------------------------------------------------------- required time 16.822 arrival time 0.444 ------------------------------------------------------------------- slack 17.266 Slack (MET) : 17.281ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.002ns (logic 1.336ns (66.719%) route 0.666ns (33.281%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.113ns = ( 17.887 - 20.000 ) Source Clock Delay (SCD): -2.495ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.847 -2.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y93 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.159 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O net (fo=1, routed) 0.666 -0.492 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.715 17.887 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/C clock pessimism -0.601 17.286 clock uncertainty -0.197 17.089 SLICE_X43Y88 FDRE (Setup_fdre_C_D) -0.300 16.789 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] ------------------------------------------------------------------- required time 16.789 arrival time 0.492 ------------------------------------------------------------------- slack 17.281 Slack (MET) : 17.293ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.252ns (logic 0.518ns (23.003%) route 1.734ns (76.997%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.119ns = ( 17.881 - 20.000 ) Source Clock Delay (SCD): -2.505ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.837 -2.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X66Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y95 FDCE (Prop_fdce_C_Q) 0.518 -1.987 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 1.734 -0.253 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[1] SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.709 17.881 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.601 17.280 clock uncertainty -0.197 17.083 SLICE_X66Y96 FDCE (Setup_fdce_C_D) -0.043 17.040 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 17.040 arrival time 0.253 ------------------------------------------------------------------- slack 17.293 Slack (MET) : 17.313ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.023ns (logic 1.343ns (66.400%) route 0.680ns (33.600%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) Source Clock Delay (SCD): -2.503ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.160 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 0.680 -0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.711 17.883 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/C clock pessimism -0.601 17.282 clock uncertainty -0.197 17.085 SLICE_X62Y90 FDRE (Setup_fdre_C_D) -0.252 16.833 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8] ------------------------------------------------------------------- required time 16.833 arrival time 0.480 ------------------------------------------------------------------- slack 17.313 Slack (MET) : 17.328ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.024ns (logic 1.344ns (66.414%) route 0.680ns (33.586%)) Logic Levels: 0 Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X62Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y94 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.680 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12] SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.711 17.883 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/C clock pessimism -0.601 17.282 clock uncertainty -0.197 17.085 SLICE_X62Y90 FDRE (Setup_fdre_C_D) -0.235 16.850 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12] ------------------------------------------------------------------- required time 16.850 arrival time 0.478 ------------------------------------------------------------------- slack 17.328 Slack (MET) : 17.332ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.202ns (logic 0.456ns (20.712%) route 1.746ns (79.288%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.122ns = ( 17.878 - 20.000 ) Source Clock Delay (SCD): -2.508ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.834 -2.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X73Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y96 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 1.746 -0.306 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[0] SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.706 17.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.601 17.277 clock uncertainty -0.197 17.080 SLICE_X72Y96 FDCE (Setup_fdce_C_D) -0.054 17.026 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 17.026 arrival time 0.306 ------------------------------------------------------------------- slack 17.332 Slack (MET) : 17.341ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.185ns (logic 1.314ns (60.146%) route 0.871ns (39.854%)) Logic Levels: 0 Clock Path Skew: -0.211ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 17.889 - 20.000 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X62Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y94 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.188 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/O net (fo=1, routed) 0.871 -0.317 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[17] SLICE_X53Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.717 17.889 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X53Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/C clock pessimism -0.601 17.288 clock uncertainty -0.197 17.091 SLICE_X53Y92 FDRE (Setup_fdre_C_D) -0.067 17.024 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17] ------------------------------------------------------------------- required time 17.024 arrival time 0.317 ------------------------------------------------------------------- slack 17.341 Slack (MET) : 17.345ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.990ns (logic 1.343ns (67.496%) route 0.647ns (32.504%)) Logic Levels: 0 Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.159 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 0.647 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[2] SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.711 17.883 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/C clock pessimism -0.601 17.282 clock uncertainty -0.197 17.085 SLICE_X62Y90 FDRE (Setup_fdre_C_D) -0.252 16.833 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2] ------------------------------------------------------------------- required time 16.833 arrival time 0.512 ------------------------------------------------------------------- slack 17.345 Slack (MET) : 17.349ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.177ns (logic 1.314ns (60.364%) route 0.863ns (39.636%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.113ns = ( 17.887 - 20.000 ) Source Clock Delay (SCD): -2.495ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.847 -2.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y93 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.181 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O net (fo=1, routed) 0.863 -0.318 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.715 17.887 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/C clock pessimism -0.601 17.286 clock uncertainty -0.197 17.089 SLICE_X43Y88 FDRE (Setup_fdre_C_D) -0.058 17.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35] ------------------------------------------------------------------- required time 17.031 arrival time 0.318 ------------------------------------------------------------------- slack 17.349 Slack (MET) : 17.355ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.138ns (logic 0.456ns (21.329%) route 1.682ns (78.671%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.122ns = ( 17.878 - 20.000 ) Source Clock Delay (SCD): -2.508ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.834 -2.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X73Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y95 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 1.682 -0.370 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[0] SLICE_X73Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.706 17.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk SLICE_X73Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.601 17.277 clock uncertainty -0.197 17.080 SLICE_X73Y94 FDCE (Setup_fdce_C_D) -0.095 16.985 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 16.985 arrival time 0.370 ------------------------------------------------------------------- slack 17.355 Slack (MET) : 17.356ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.981ns (logic 1.344ns (67.851%) route 0.637ns (32.149%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 17.889 - 20.000 ) Source Clock Delay (SCD): -2.497ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X56Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y94 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.637 -0.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.717 17.889 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C clock pessimism -0.601 17.288 clock uncertainty -0.197 17.091 SLICE_X55Y93 FDRE (Setup_fdre_C_D) -0.251 16.840 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24] ------------------------------------------------------------------- required time 16.840 arrival time 0.516 ------------------------------------------------------------------- slack 17.356 Slack (MET) : 17.357ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.995ns (logic 1.344ns (67.365%) route 0.651ns (32.635%)) Logic Levels: 0 Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 17.890 - 20.000 ) Source Clock Delay (SCD): -2.495ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.847 -2.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y93 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.151 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 0.651 -0.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] SLICE_X44Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.718 17.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X44Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/C clock pessimism -0.601 17.289 clock uncertainty -0.197 17.092 SLICE_X44Y92 FDRE (Setup_fdre_C_D) -0.235 16.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30] ------------------------------------------------------------------- required time 16.857 arrival time 0.499 ------------------------------------------------------------------- slack 17.357 Slack (MET) : 17.397ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.148ns (logic 0.456ns (21.229%) route 1.692ns (78.771%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) Source Clock Delay (SCD): -2.509ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X71Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y91 FDCE (Prop_fdce_C_Q) 0.456 -2.053 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 1.692 -0.361 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[1] SLICE_X70Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X70Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.601 17.276 clock uncertainty -0.197 17.079 SLICE_X70Y91 FDCE (Setup_fdce_C_D) -0.043 17.036 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 17.036 arrival time 0.361 ------------------------------------------------------------------- slack 17.397 Slack (MET) : 17.408ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.146ns (logic 1.317ns (61.365%) route 0.829ns (38.635%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.122ns = ( 17.878 - 20.000 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O net (fo=1, routed) 0.829 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] SLICE_X62Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.706 17.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/C clock pessimism -0.601 17.277 clock uncertainty -0.197 17.080 SLICE_X62Y83 FDRE (Setup_fdre_C_D) -0.028 17.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3] ------------------------------------------------------------------- required time 17.052 arrival time 0.355 ------------------------------------------------------------------- slack 17.408 Slack (MET) : 17.413ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.082ns (logic 0.518ns (24.876%) route 1.564ns (75.124%)) Logic Levels: 0 Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.503ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X64Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y93 FDCE (Prop_fdce_C_Q) 0.518 -1.985 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 1.564 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1] SLICE_X65Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.712 17.884 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X65Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.601 17.283 clock uncertainty -0.197 17.086 SLICE_X65Y94 FDCE (Setup_fdce_C_D) -0.093 16.993 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 16.993 arrival time 0.420 ------------------------------------------------------------------- slack 17.413 Slack (MET) : 17.420ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.074ns (logic 0.456ns (21.984%) route 1.618ns (78.016%)) Logic Levels: 0 Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 ) Source Clock Delay (SCD): -2.508ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.834 -2.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X73Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y96 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 1.618 -0.433 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[1] SLICE_X73Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.707 17.879 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X73Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.601 17.278 clock uncertainty -0.197 17.081 SLICE_X73Y97 FDCE (Setup_fdce_C_D) -0.095 16.986 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 16.986 arrival time 0.433 ------------------------------------------------------------------- slack 17.420 Slack (MET) : 17.423ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.896ns (logic 0.419ns (22.098%) route 1.477ns (77.902%)) Logic Levels: 0 Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X63Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y93 FDCE (Prop_fdce_C_Q) 0.419 -2.083 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=5, routed) 1.477 -0.605 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[3] SLICE_X65Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.711 17.883 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X65Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.601 17.282 clock uncertainty -0.197 17.085 SLICE_X65Y92 FDCE (Setup_fdce_C_D) -0.268 16.817 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 16.817 arrival time 0.605 ------------------------------------------------------------------- slack 17.423 Slack (MET) : 17.428ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.874ns (logic 1.343ns (71.683%) route 0.531ns (28.317%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 17.889 - 20.000 ) Source Clock Delay (SCD): -2.497ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X56Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y94 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.154 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 0.531 -0.623 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.717 17.889 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/C clock pessimism -0.601 17.288 clock uncertainty -0.197 17.091 SLICE_X55Y93 FDRE (Setup_fdre_C_D) -0.286 16.805 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26] ------------------------------------------------------------------- required time 16.805 arrival time 0.623 ------------------------------------------------------------------- slack 17.428 Slack (MET) : 17.428ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.100ns (logic 1.309ns (62.320%) route 0.791ns (37.680%)) Logic Levels: 0 Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 17.890 - 20.000 ) Source Clock Delay (SCD): -2.495ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.847 -2.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X48Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y93 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.186 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O net (fo=1, routed) 0.791 -0.394 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] SLICE_X47Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.718 17.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X47Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/C clock pessimism -0.601 17.289 clock uncertainty -0.197 17.092 SLICE_X47Y92 FDRE (Setup_fdre_C_D) -0.058 17.034 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] ------------------------------------------------------------------- required time 17.034 arrival time 0.394 ------------------------------------------------------------------- slack 17.428 Slack (MET) : 17.432ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.939ns (logic 0.478ns (24.648%) route 1.461ns (75.352%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.119ns = ( 17.881 - 20.000 ) Source Clock Delay (SCD): -2.505ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.837 -2.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X66Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y95 FDCE (Prop_fdce_C_Q) 0.478 -2.027 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 1.461 -0.565 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.709 17.881 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.601 17.280 clock uncertainty -0.197 17.083 SLICE_X66Y96 FDCE (Setup_fdce_C_D) -0.216 16.867 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 16.867 arrival time 0.565 ------------------------------------------------------------------- slack 17.432 Slack (MET) : 17.473ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.022ns (logic 0.456ns (22.553%) route 1.566ns (77.447%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.122ns = ( 17.878 - 20.000 ) Source Clock Delay (SCD): -2.508ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.834 -2.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X73Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y95 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 1.566 -0.486 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[2] SLICE_X73Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.706 17.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk SLICE_X73Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.601 17.277 clock uncertainty -0.197 17.080 SLICE_X73Y94 FDCE (Setup_fdce_C_D) -0.093 16.987 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 16.987 arrival time 0.486 ------------------------------------------------------------------- slack 17.473 Slack (MET) : 17.480ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.013ns (logic 0.456ns (22.653%) route 1.557ns (77.347%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) Source Clock Delay (SCD): -2.509ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X71Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y92 FDCE (Prop_fdce_C_Q) 0.456 -2.053 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 1.557 -0.496 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[2] SLICE_X73Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X73Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.601 17.276 clock uncertainty -0.197 17.079 SLICE_X73Y92 FDCE (Setup_fdce_C_D) -0.095 16.984 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 16.984 arrival time 0.496 ------------------------------------------------------------------- slack 17.480 Slack (MET) : 17.484ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.868ns (logic 1.344ns (71.959%) route 0.524ns (28.041%)) Logic Levels: 0 Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 17.888 - 20.000 ) Source Clock Delay (SCD): -2.497ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 0.524 -0.629 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] SLICE_X56Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.716 17.888 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X56Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/C clock pessimism -0.601 17.287 clock uncertainty -0.197 17.090 SLICE_X56Y92 FDRE (Setup_fdre_C_D) -0.235 16.855 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18] ------------------------------------------------------------------- required time 16.855 arrival time 0.629 ------------------------------------------------------------------- slack 17.484 Slack (MET) : 17.486ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.054ns (logic 0.518ns (25.213%) route 1.536ns (74.787%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.119ns = ( 17.881 - 20.000 ) Source Clock Delay (SCD): -2.505ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.837 -2.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X66Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y95 FDCE (Prop_fdce_C_Q) 0.518 -1.987 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 1.536 -0.450 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.709 17.881 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.601 17.280 clock uncertainty -0.197 17.083 SLICE_X66Y96 FDCE (Setup_fdce_C_D) -0.047 17.036 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 17.036 arrival time 0.450 ------------------------------------------------------------------- slack 17.486 Slack (MET) : 17.491ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.050ns (logic 0.456ns (22.243%) route 1.594ns (77.757%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) Source Clock Delay (SCD): -2.509ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X71Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y91 FDCE (Prop_fdce_C_Q) 0.456 -2.053 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 1.594 -0.459 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] SLICE_X70Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X70Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.601 17.276 clock uncertainty -0.197 17.079 SLICE_X70Y91 FDCE (Setup_fdce_C_D) -0.047 17.032 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 17.032 arrival time 0.459 ------------------------------------------------------------------- slack 17.491 Slack (MET) : 17.525ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.796ns (logic 0.419ns (23.331%) route 1.377ns (76.669%)) Logic Levels: 0 Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 ) Source Clock Delay (SCD): -2.508ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.834 -2.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X73Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y96 FDCE (Prop_fdce_C_Q) 0.419 -2.089 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 1.377 -0.712 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] SLICE_X73Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.707 17.879 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X73Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.601 17.278 clock uncertainty -0.197 17.081 SLICE_X73Y97 FDCE (Setup_fdce_C_D) -0.268 16.813 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 16.813 arrival time 0.712 ------------------------------------------------------------------- slack 17.525 Slack (MET) : 17.531ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.821ns (logic 1.336ns (73.353%) route 0.485ns (26.647%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X62Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y94 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.166 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.485 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.712 17.884 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/C clock pessimism -0.601 17.283 clock uncertainty -0.197 17.086 SLICE_X62Y92 FDRE (Setup_fdre_C_D) -0.235 16.851 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16] ------------------------------------------------------------------- required time 16.851 arrival time 0.680 ------------------------------------------------------------------- slack 17.531 Slack (MET) : 17.533ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.984ns (logic 1.317ns (66.368%) route 0.667ns (33.632%)) Logic Levels: 0 Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 17.888 - 20.000 ) Source Clock Delay (SCD): -2.495ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.847 -2.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X48Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y93 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.178 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O net (fo=1, routed) 0.667 -0.510 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] SLICE_X47Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.716 17.888 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X47Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/C clock pessimism -0.601 17.287 clock uncertainty -0.197 17.090 SLICE_X47Y88 FDRE (Setup_fdre_C_D) -0.067 17.023 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39] ------------------------------------------------------------------- required time 17.023 arrival time 0.510 ------------------------------------------------------------------- slack 17.533 Slack (MET) : 17.561ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.984ns (logic 0.456ns (22.985%) route 1.528ns (77.015%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.122ns = ( 17.878 - 20.000 ) Source Clock Delay (SCD): -2.508ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.834 -2.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X73Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y96 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 1.528 -0.524 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[3] SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.706 17.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.601 17.277 clock uncertainty -0.197 17.080 SLICE_X72Y96 FDCE (Setup_fdce_C_D) -0.043 17.037 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 17.037 arrival time 0.524 ------------------------------------------------------------------- slack 17.561 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: cpu_clk To Clock: cpu_clk Setup : 0 Failing Endpoints, Worst Slack 26.418ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 26.418ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.307ns (logic 0.642ns (19.413%) route 2.665ns (80.587%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.013ns = ( 28.309 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.010 0.985 u_Axi_CDC/arFifo/p_0_in SLICE_X19Y65 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.815 28.309 u_Axi_CDC/arFifo/cpu_clk SLICE_X19Y65 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.426 27.883 clock uncertainty -0.074 27.809 SLICE_X19Y65 FDCE (Recov_fdce_C_CLR) -0.405 27.404 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 27.404 arrival time -0.985 ------------------------------------------------------------------- slack 26.418 Slack (MET) : 26.418ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.307ns (logic 0.642ns (19.413%) route 2.665ns (80.587%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.013ns = ( 28.309 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.010 0.985 u_Axi_CDC/arFifo/p_0_in SLICE_X19Y65 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.815 28.309 u_Axi_CDC/arFifo/cpu_clk SLICE_X19Y65 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.426 27.883 clock uncertainty -0.074 27.809 SLICE_X19Y65 FDCE (Recov_fdce_C_CLR) -0.405 27.404 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 27.404 arrival time -0.985 ------------------------------------------------------------------- slack 26.418 Slack (MET) : 26.418ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.307ns (logic 0.642ns (19.413%) route 2.665ns (80.587%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.013ns = ( 28.309 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.010 0.985 u_Axi_CDC/arFifo/p_0_in SLICE_X19Y65 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.815 28.309 u_Axi_CDC/arFifo/cpu_clk SLICE_X19Y65 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.426 27.883 clock uncertainty -0.074 27.809 SLICE_X19Y65 FDCE (Recov_fdce_C_CLR) -0.405 27.404 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 27.404 arrival time -0.985 ------------------------------------------------------------------- slack 26.418 Slack (MET) : 26.418ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.307ns (logic 0.642ns (19.413%) route 2.665ns (80.587%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.013ns = ( 28.309 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.010 0.985 u_Axi_CDC/arFifo/p_0_in SLICE_X19Y65 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.815 28.309 u_Axi_CDC/arFifo/cpu_clk SLICE_X19Y65 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.426 27.883 clock uncertainty -0.074 27.809 SLICE_X19Y65 FDCE (Recov_fdce_C_CLR) -0.405 27.404 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 27.404 arrival time -0.985 ------------------------------------------------------------------- slack 26.418 Slack (MET) : 26.418ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.307ns (logic 0.642ns (19.413%) route 2.665ns (80.587%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.013ns = ( 28.309 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.010 0.985 u_Axi_CDC/arFifo/p_0_in SLICE_X19Y65 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.815 28.309 u_Axi_CDC/arFifo/cpu_clk SLICE_X19Y65 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.426 27.883 clock uncertainty -0.074 27.809 SLICE_X19Y65 FDCE (Recov_fdce_C_CLR) -0.405 27.404 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 27.404 arrival time -0.985 ------------------------------------------------------------------- slack 26.418 Slack (MET) : 26.602ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.169ns (logic 0.642ns (20.261%) route 2.527ns (79.739%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.872 0.847 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X18Y64 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X18Y64 FDCE (Recov_fdce_C_CLR) -0.361 27.449 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 27.449 arrival time -0.847 ------------------------------------------------------------------- slack 26.602 Slack (MET) : 26.602ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.169ns (logic 0.642ns (20.261%) route 2.527ns (79.739%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.872 0.847 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X18Y64 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X18Y64 FDCE (Recov_fdce_C_CLR) -0.361 27.449 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 27.449 arrival time -0.847 ------------------------------------------------------------------- slack 26.602 Slack (MET) : 26.602ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.169ns (logic 0.642ns (20.261%) route 2.527ns (79.739%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.872 0.847 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X18Y64 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X18Y64 FDCE (Recov_fdce_C_CLR) -0.361 27.449 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 27.449 arrival time -0.847 ------------------------------------------------------------------- slack 26.602 Slack (MET) : 26.644ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.169ns (logic 0.642ns (20.261%) route 2.527ns (79.739%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.872 0.847 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X18Y64 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X18Y64 FDCE (Recov_fdce_C_CLR) -0.319 27.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 27.491 arrival time -0.847 ------------------------------------------------------------------- slack 26.644 Slack (MET) : 26.644ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.169ns (logic 0.642ns (20.261%) route 2.527ns (79.739%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.872 0.847 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X18Y64 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X18Y64 FDCE (Recov_fdce_C_CLR) -0.319 27.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 27.491 arrival time -0.847 ------------------------------------------------------------------- slack 26.644 Slack (MET) : 26.644ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.169ns (logic 0.642ns (20.261%) route 2.527ns (79.739%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.872 0.847 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X18Y64 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X18Y64 FDCE (Recov_fdce_C_CLR) -0.319 27.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 27.491 arrival time -0.847 ------------------------------------------------------------------- slack 26.644 Slack (MET) : 26.678ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.093ns (logic 0.773ns (24.992%) route 2.320ns (75.008%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.851 0.771 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X12Y63 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X12Y63 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X12Y63 FDCE (Recov_fdce_C_CLR) -0.361 27.449 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 27.449 arrival time -0.771 ------------------------------------------------------------------- slack 26.678 Slack (MET) : 26.678ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.093ns (logic 0.773ns (24.992%) route 2.320ns (75.008%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.851 0.771 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X12Y63 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X12Y63 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X12Y63 FDCE (Recov_fdce_C_CLR) -0.361 27.449 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 27.449 arrival time -0.771 ------------------------------------------------------------------- slack 26.678 Slack (MET) : 26.720ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.093ns (logic 0.773ns (24.992%) route 2.320ns (75.008%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.851 0.771 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X12Y63 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y63 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X12Y63 FDCE (Recov_fdce_C_CLR) -0.319 27.491 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 27.491 arrival time -0.771 ------------------------------------------------------------------- slack 26.720 Slack (MET) : 26.720ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.093ns (logic 0.773ns (24.992%) route 2.320ns (75.008%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.851 0.771 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X12Y63 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X12Y63 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X12Y63 FDCE (Recov_fdce_C_CLR) -0.319 27.491 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 27.491 arrival time -0.771 ------------------------------------------------------------------- slack 26.720 Slack (MET) : 26.720ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.093ns (logic 0.773ns (24.992%) route 2.320ns (75.008%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.851 0.771 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X12Y63 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X12Y63 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X12Y63 FDCE (Recov_fdce_C_CLR) -0.319 27.491 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 27.491 arrival time -0.771 ------------------------------------------------------------------- slack 26.720 Slack (MET) : 26.913ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.813ns (logic 0.773ns (27.475%) route 2.040ns (72.525%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.571 0.492 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y64 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y64 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X13Y64 FDCE (Recov_fdce_C_CLR) -0.405 27.405 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 27.405 arrival time -0.492 ------------------------------------------------------------------- slack 26.913 Slack (MET) : 26.913ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.813ns (logic 0.773ns (27.475%) route 2.040ns (72.525%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.571 0.492 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y64 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y64 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X13Y64 FDCE (Recov_fdce_C_CLR) -0.405 27.405 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 27.405 arrival time -0.492 ------------------------------------------------------------------- slack 26.913 Slack (MET) : 26.913ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.813ns (logic 0.773ns (27.475%) route 2.040ns (72.525%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.571 0.492 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y64 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y64 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X13Y64 FDCE (Recov_fdce_C_CLR) -0.405 27.405 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 27.405 arrival time -0.492 ------------------------------------------------------------------- slack 26.913 Slack (MET) : 26.913ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.813ns (logic 0.773ns (27.475%) route 2.040ns (72.525%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.571 0.492 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y64 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y64 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X13Y64 FDCE (Recov_fdce_C_CLR) -0.405 27.405 u_Axi_CDC/rFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- required time 27.405 arrival time -0.492 ------------------------------------------------------------------- slack 26.913 Slack (MET) : 27.109ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.666ns (logic 0.642ns (24.084%) route 2.024ns (75.916%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.369 0.344 u_Axi_CDC/wFifo/p_0_in SLICE_X8Y58 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/wFifo/cpu_clk SLICE_X8Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.426 27.888 clock uncertainty -0.074 27.814 SLICE_X8Y58 FDCE (Recov_fdce_C_CLR) -0.361 27.453 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 27.453 arrival time -0.344 ------------------------------------------------------------------- slack 27.109 Slack (MET) : 27.109ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.666ns (logic 0.642ns (24.084%) route 2.024ns (75.916%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.369 0.344 u_Axi_CDC/wFifo/p_0_in SLICE_X8Y58 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/wFifo/cpu_clk SLICE_X8Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C clock pessimism -0.426 27.888 clock uncertainty -0.074 27.814 SLICE_X8Y58 FDCE (Recov_fdce_C_CLR) -0.361 27.453 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2] ------------------------------------------------------------------- required time 27.453 arrival time -0.344 ------------------------------------------------------------------- slack 27.109 Slack (MET) : 27.151ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.666ns (logic 0.642ns (24.084%) route 2.024ns (75.916%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.369 0.344 u_Axi_CDC/wFifo/p_0_in SLICE_X8Y58 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/wFifo/cpu_clk SLICE_X8Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.426 27.888 clock uncertainty -0.074 27.814 SLICE_X8Y58 FDCE (Recov_fdce_C_CLR) -0.319 27.495 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 27.495 arrival time -0.344 ------------------------------------------------------------------- slack 27.151 Slack (MET) : 27.151ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.666ns (logic 0.642ns (24.084%) route 2.024ns (75.916%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.369 0.344 u_Axi_CDC/wFifo/p_0_in SLICE_X8Y58 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/wFifo/cpu_clk SLICE_X8Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.426 27.888 clock uncertainty -0.074 27.814 SLICE_X8Y58 FDCE (Recov_fdce_C_CLR) -0.319 27.495 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 27.495 arrival time -0.344 ------------------------------------------------------------------- slack 27.151 Slack (MET) : 27.298ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.471ns (logic 0.773ns (31.281%) route 1.698ns (68.719%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.013ns = ( 28.309 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.229 0.150 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X14Y65 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.815 28.309 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.426 27.883 clock uncertainty -0.074 27.809 SLICE_X14Y65 FDCE (Recov_fdce_C_CLR) -0.361 27.448 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 27.448 arrival time -0.150 ------------------------------------------------------------------- slack 27.298 Slack (MET) : 27.298ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.471ns (logic 0.773ns (31.281%) route 1.698ns (68.719%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.013ns = ( 28.309 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.229 0.150 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X14Y65 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.815 28.309 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.426 27.883 clock uncertainty -0.074 27.809 SLICE_X14Y65 FDCE (Recov_fdce_C_CLR) -0.361 27.448 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 27.448 arrival time -0.150 ------------------------------------------------------------------- slack 27.298 Slack (MET) : 27.340ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.471ns (logic 0.773ns (31.281%) route 1.698ns (68.719%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.013ns = ( 28.309 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.229 0.150 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X14Y65 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.815 28.309 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.426 27.883 clock uncertainty -0.074 27.809 SLICE_X14Y65 FDCE (Recov_fdce_C_CLR) -0.319 27.490 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 27.490 arrival time -0.150 ------------------------------------------------------------------- slack 27.340 Slack (MET) : 27.340ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.471ns (logic 0.773ns (31.281%) route 1.698ns (68.719%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.013ns = ( 28.309 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.229 0.150 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X14Y65 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.815 28.309 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.426 27.883 clock uncertainty -0.074 27.809 SLICE_X14Y65 FDCE (Recov_fdce_C_CLR) -0.319 27.490 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 27.490 arrival time -0.150 ------------------------------------------------------------------- slack 27.340 Slack (MET) : 27.344ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.432ns (logic 0.642ns (26.400%) route 1.790ns (73.600%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.007ns = ( 28.315 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.135 0.110 u_Axi_CDC/wFifo/p_0_in SLICE_X10Y58 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 28.315 u_Axi_CDC/wFifo/cpu_clk SLICE_X10Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C clock pessimism -0.426 27.889 clock uncertainty -0.074 27.815 SLICE_X10Y58 FDCE (Recov_fdce_C_CLR) -0.361 27.454 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3] ------------------------------------------------------------------- required time 27.454 arrival time -0.110 ------------------------------------------------------------------- slack 27.344 Slack (MET) : 27.385ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.343ns (logic 0.642ns (27.398%) route 1.701ns (72.602%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.046 0.022 u_Axi_CDC/awFifo/p_0_in SLICE_X17Y61 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/awFifo/cpu_clk SLICE_X17Y61 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X17Y61 FDCE (Recov_fdce_C_CLR) -0.405 27.407 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 27.407 arrival time -0.022 ------------------------------------------------------------------- slack 27.385 Slack (MET) : 27.385ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.343ns (logic 0.642ns (27.398%) route 1.701ns (72.602%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.046 0.022 u_Axi_CDC/awFifo/p_0_in SLICE_X17Y61 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/awFifo/cpu_clk SLICE_X17Y61 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X17Y61 FDCE (Recov_fdce_C_CLR) -0.405 27.407 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 27.407 arrival time -0.022 ------------------------------------------------------------------- slack 27.385 Slack (MET) : 27.385ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.343ns (logic 0.642ns (27.398%) route 1.701ns (72.602%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.046 0.022 u_Axi_CDC/awFifo/p_0_in SLICE_X17Y61 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/awFifo/cpu_clk SLICE_X17Y61 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X17Y61 FDCE (Recov_fdce_C_CLR) -0.405 27.407 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 27.407 arrival time -0.022 ------------------------------------------------------------------- slack 27.385 Slack (MET) : 27.385ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.343ns (logic 0.642ns (27.398%) route 1.701ns (72.602%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.046 0.022 u_Axi_CDC/awFifo/p_0_in SLICE_X17Y61 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/awFifo/cpu_clk SLICE_X17Y61 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X17Y61 FDCE (Recov_fdce_C_CLR) -0.405 27.407 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 27.407 arrival time -0.022 ------------------------------------------------------------------- slack 27.385 Slack (MET) : 27.385ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.343ns (logic 0.642ns (27.398%) route 1.701ns (72.602%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.046 0.022 u_Axi_CDC/awFifo/p_0_in SLICE_X17Y61 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/awFifo/cpu_clk SLICE_X17Y61 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X17Y61 FDCE (Recov_fdce_C_CLR) -0.405 27.407 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 27.407 arrival time -0.022 ------------------------------------------------------------------- slack 27.385 Slack (MET) : 27.386ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.432ns (logic 0.642ns (26.400%) route 1.790ns (73.600%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.007ns = ( 28.315 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.135 0.110 u_Axi_CDC/wFifo/p_0_in SLICE_X10Y58 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 28.315 u_Axi_CDC/wFifo/cpu_clk SLICE_X10Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.426 27.889 clock uncertainty -0.074 27.815 SLICE_X10Y58 FDCE (Recov_fdce_C_CLR) -0.319 27.496 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 27.496 arrival time -0.110 ------------------------------------------------------------------- slack 27.386 Slack (MET) : 27.386ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.432ns (logic 0.642ns (26.400%) route 1.790ns (73.600%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.007ns = ( 28.315 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.135 0.110 u_Axi_CDC/wFifo/p_0_in SLICE_X10Y58 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 28.315 u_Axi_CDC/wFifo/cpu_clk SLICE_X10Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.426 27.889 clock uncertainty -0.074 27.815 SLICE_X10Y58 FDCE (Recov_fdce_C_CLR) -0.319 27.496 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 27.496 arrival time -0.110 ------------------------------------------------------------------- slack 27.386 Slack (MET) : 27.394ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.333ns (logic 0.773ns (33.137%) route 1.560ns (66.863%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.090 0.011 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X15Y64 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y64 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X15Y64 FDCE (Recov_fdce_C_CLR) -0.405 27.405 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 27.405 arrival time -0.011 ------------------------------------------------------------------- slack 27.394 Slack (MET) : 27.394ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.333ns (logic 0.773ns (33.137%) route 1.560ns (66.863%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.090 0.011 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X15Y64 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y64 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X15Y64 FDCE (Recov_fdce_C_CLR) -0.405 27.405 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 27.405 arrival time -0.011 ------------------------------------------------------------------- slack 27.394 Slack (MET) : 27.394ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.333ns (logic 0.773ns (33.137%) route 1.560ns (66.863%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.090 0.011 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X15Y64 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y64 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X15Y64 FDCE (Recov_fdce_C_CLR) -0.405 27.405 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 27.405 arrival time -0.011 ------------------------------------------------------------------- slack 27.394 Slack (MET) : 27.394ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.333ns (logic 0.773ns (33.137%) route 1.560ns (66.863%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns = ( 28.310 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.090 0.011 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X15Y64 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 28.310 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y64 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C clock pessimism -0.426 27.884 clock uncertainty -0.074 27.810 SLICE_X15Y64 FDCE (Recov_fdce_C_CLR) -0.405 27.405 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 27.405 arrival time -0.011 ------------------------------------------------------------------- slack 27.394 Slack (MET) : 27.408ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.321ns (logic 0.773ns (33.312%) route 1.548ns (66.688%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.078 -0.001 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X15Y61 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/bFifo/cpu_clk SLICE_X15Y61 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X15Y61 FDCE (Recov_fdce_C_CLR) -0.405 27.407 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 27.407 arrival time 0.001 ------------------------------------------------------------------- slack 27.408 Slack (MET) : 27.408ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.321ns (logic 0.773ns (33.312%) route 1.548ns (66.688%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.078 -0.001 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X15Y61 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/bFifo/cpu_clk SLICE_X15Y61 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X15Y61 FDCE (Recov_fdce_C_CLR) -0.405 27.407 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 27.407 arrival time 0.001 ------------------------------------------------------------------- slack 27.408 Slack (MET) : 27.408ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.321ns (logic 0.773ns (33.312%) route 1.548ns (66.688%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.078 -0.001 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X15Y61 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/bFifo/cpu_clk SLICE_X15Y61 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X15Y61 FDCE (Recov_fdce_C_CLR) -0.405 27.407 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 27.407 arrival time 0.001 ------------------------------------------------------------------- slack 27.408 Slack (MET) : 27.429ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.343ns (logic 0.642ns (27.398%) route 1.701ns (72.602%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.046 0.022 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y61 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X16Y61 FDCE (Recov_fdce_C_CLR) -0.361 27.451 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 27.451 arrival time -0.022 ------------------------------------------------------------------- slack 27.429 Slack (MET) : 27.429ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.343ns (logic 0.642ns (27.398%) route 1.701ns (72.602%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.046 0.022 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y61 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X16Y61 FDCE (Recov_fdce_C_CLR) -0.361 27.451 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 27.451 arrival time -0.022 ------------------------------------------------------------------- slack 27.429 Slack (MET) : 27.429ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.343ns (logic 0.642ns (27.398%) route 1.701ns (72.602%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.046 0.022 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y61 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X16Y61 FDCE (Recov_fdce_C_CLR) -0.361 27.451 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 27.451 arrival time -0.022 ------------------------------------------------------------------- slack 27.429 Slack (MET) : 27.452ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.321ns (logic 0.773ns (33.312%) route 1.548ns (66.688%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.478 -1.844 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.469 -1.374 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.295 -1.079 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.078 -0.001 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X14Y61 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/bFifo/cpu_clk SLICE_X14Y61 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X14Y61 FDCE (Recov_fdce_C_CLR) -0.361 27.451 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 27.451 arrival time 0.001 ------------------------------------------------------------------- slack 27.452 Slack (MET) : 27.471ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.343ns (logic 0.642ns (27.398%) route 1.701ns (72.602%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.046 0.022 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y61 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X16Y61 FDCE (Recov_fdce_C_CLR) -0.319 27.493 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 27.493 arrival time -0.022 ------------------------------------------------------------------- slack 27.471 Slack (MET) : 27.471ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.343ns (logic 0.642ns (27.398%) route 1.701ns (72.602%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.046 0.022 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y61 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X16Y61 FDCE (Recov_fdce_C_CLR) -0.319 27.493 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 27.493 arrival time -0.022 ------------------------------------------------------------------- slack 27.471 Slack (MET) : 27.471ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.343ns (logic 0.642ns (27.398%) route 1.701ns (72.602%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 28.312 - 30.323 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.020 -2.322 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.518 -1.804 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.655 -1.148 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.124 -1.024 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.046 0.022 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y61 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 28.312 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.426 27.886 clock uncertainty -0.074 27.812 SLICE_X16Y61 FDCE (Recov_fdce_C_CLR) -0.319 27.493 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 27.493 arrival time -0.022 ------------------------------------------------------------------- slack 27.471 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: mlkem_clk_clk_pll To Clock: mlkem_clk_clk_pll Setup : 0 Failing Endpoints, Worst Slack 28.755ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 28.755ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[67][2]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.600ns (logic 0.608ns (5.736%) route 9.992ns (94.264%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.763 7.923 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X152Y199 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[67][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X152Y199 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[67][2]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X152Y199 FDCE (Recov_fdce_C_CLR) -0.527 36.678 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[67][2] ------------------------------------------------------------------- required time 36.678 arrival time -7.923 ------------------------------------------------------------------- slack 28.755 Slack (MET) : 28.807ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[81][2]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.462ns (logic 0.608ns (5.812%) route 9.854ns (94.188%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.625 7.785 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X153Y198 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[81][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X153Y198 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[81][2]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X153Y198 FDCE (Recov_fdce_C_CLR) -0.613 36.592 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[81][2] ------------------------------------------------------------------- required time 36.592 arrival time -7.785 ------------------------------------------------------------------- slack 28.807 Slack (MET) : 28.879ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[83][4]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.389ns (logic 0.608ns (5.853%) route 9.781ns (94.147%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.552 7.712 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X153Y193 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[83][4]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X153Y193 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[83][4]/C clock pessimism -0.514 37.281 clock uncertainty -0.077 37.204 SLICE_X153Y193 FDCE (Recov_fdce_C_CLR) -0.613 36.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[83][4] ------------------------------------------------------------------- required time 36.591 arrival time -7.712 ------------------------------------------------------------------- slack 28.879 Slack (MET) : 28.893ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[89][2]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.462ns (logic 0.608ns (5.812%) route 9.854ns (94.188%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.625 7.785 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X152Y198 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[89][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X152Y198 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[89][2]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X152Y198 FDCE (Recov_fdce_C_CLR) -0.527 36.678 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[89][2] ------------------------------------------------------------------- required time 36.678 arrival time -7.785 ------------------------------------------------------------------- slack 28.893 Slack (MET) : 28.907ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[79][2]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.363ns (logic 0.608ns (5.867%) route 9.755ns (94.133%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.041ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.527 7.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X155Y197 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[79][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.625 37.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X155Y197 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[79][2]/C clock pessimism -0.514 37.283 clock uncertainty -0.077 37.206 SLICE_X155Y197 FDCE (Recov_fdce_C_CLR) -0.613 36.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[79][2] ------------------------------------------------------------------- required time 36.593 arrival time -7.687 ------------------------------------------------------------------- slack 28.907 Slack (MET) : 28.908ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][30]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.364ns (logic 0.608ns (5.866%) route 9.756ns (94.134%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.023 -1.198 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.152 -1.046 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 8.733 7.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X53Y129 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][30]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X53Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][30]/C clock pessimism -0.435 37.279 clock uncertainty -0.077 37.203 SLICE_X53Y129 FDCE (Recov_fdce_C_CLR) -0.607 36.596 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][30] ------------------------------------------------------------------- required time 36.596 arrival time -7.688 ------------------------------------------------------------------- slack 28.908 Slack (MET) : 28.909ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][1]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.359ns (logic 0.608ns (5.869%) route 9.751ns (94.131%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.523 7.682 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X151Y195 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X151Y195 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][1]/C clock pessimism -0.514 37.281 clock uncertainty -0.077 37.204 SLICE_X151Y195 FDCE (Recov_fdce_C_CLR) -0.613 36.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][1] ------------------------------------------------------------------- required time 36.591 arrival time -7.682 ------------------------------------------------------------------- slack 28.909 Slack (MET) : 28.920ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[83][0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.347ns (logic 0.608ns (5.876%) route 9.739ns (94.124%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.511 7.671 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X153Y196 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[83][0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X153Y196 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[83][0]/C clock pessimism -0.514 37.281 clock uncertainty -0.077 37.204 SLICE_X153Y196 FDCE (Recov_fdce_C_CLR) -0.613 36.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[83][0] ------------------------------------------------------------------- required time 36.591 arrival time -7.671 ------------------------------------------------------------------- slack 28.920 Slack (MET) : 28.925ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.344ns (logic 0.608ns (5.878%) route 9.736ns (94.122%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.507 7.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X151Y197 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X151Y197 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][0]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X151Y197 FDCE (Recov_fdce_C_CLR) -0.613 36.592 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][0] ------------------------------------------------------------------- required time 36.592 arrival time -7.667 ------------------------------------------------------------------- slack 28.925 Slack (MET) : 28.925ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][2]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.344ns (logic 0.608ns (5.878%) route 9.736ns (94.122%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.507 7.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X151Y197 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X151Y197 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][2]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X151Y197 FDCE (Recov_fdce_C_CLR) -0.613 36.592 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][2] ------------------------------------------------------------------- required time 36.592 arrival time -7.667 ------------------------------------------------------------------- slack 28.925 Slack (MET) : 28.925ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][5]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.344ns (logic 0.608ns (5.878%) route 9.736ns (94.122%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.507 7.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X151Y197 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][5]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X151Y197 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][5]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X151Y197 FDCE (Recov_fdce_C_CLR) -0.613 36.592 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[91][5] ------------------------------------------------------------------- required time 36.592 arrival time -7.667 ------------------------------------------------------------------- slack 28.925 Slack (MET) : 28.925ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[91][0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.344ns (logic 0.608ns (5.878%) route 9.736ns (94.122%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.507 7.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X151Y197 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[91][0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X151Y197 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[91][0]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X151Y197 FDCE (Recov_fdce_C_CLR) -0.613 36.592 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[91][0] ------------------------------------------------------------------- required time 36.592 arrival time -7.667 ------------------------------------------------------------------- slack 28.925 Slack (MET) : 28.932ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][6]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.336ns (logic 0.608ns (5.882%) route 9.728ns (94.118%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.499 7.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X147Y199 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][6]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X147Y199 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][6]/C clock pessimism -0.514 37.281 clock uncertainty -0.077 37.204 SLICE_X147Y199 FDCE (Recov_fdce_C_CLR) -0.613 36.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][6] ------------------------------------------------------------------- required time 36.591 arrival time -7.659 ------------------------------------------------------------------- slack 28.932 Slack (MET) : 28.934ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[85][2]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.334ns (logic 0.608ns (5.883%) route 9.726ns (94.117%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.498 7.658 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X151Y198 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[85][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X151Y198 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[85][2]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X151Y198 FDCE (Recov_fdce_C_CLR) -0.613 36.592 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[85][2] ------------------------------------------------------------------- required time 36.592 arrival time -7.658 ------------------------------------------------------------------- slack 28.934 Slack (MET) : 28.956ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[93][0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.312ns (logic 0.608ns (5.896%) route 9.704ns (94.104%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.476 7.636 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X155Y195 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[93][0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X155Y195 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[93][0]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X155Y195 FDCE (Recov_fdce_C_CLR) -0.613 36.592 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[93][0] ------------------------------------------------------------------- required time 36.592 arrival time -7.636 ------------------------------------------------------------------- slack 28.956 Slack (MET) : 28.958ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[93][4]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.311ns (logic 0.608ns (5.897%) route 9.703ns (94.103%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.475 7.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X155Y193 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[93][4]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X155Y193 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[93][4]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X155Y193 FDCE (Recov_fdce_C_CLR) -0.613 36.592 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[93][4] ------------------------------------------------------------------- required time 36.592 arrival time -7.634 ------------------------------------------------------------------- slack 28.958 Slack (MET) : 28.965ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[224][2]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.371ns (logic 0.608ns (5.862%) route 9.763ns (94.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.138ns = ( 37.862 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.535 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X159Y183 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[224][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.691 37.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X159Y183 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[224][2]/C clock pessimism -0.514 37.349 clock uncertainty -0.077 37.272 SLICE_X159Y183 FDCE (Recov_fdce_C_CLR) -0.613 36.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[224][2] ------------------------------------------------------------------- required time 36.659 arrival time -7.695 ------------------------------------------------------------------- slack 28.965 Slack (MET) : 28.965ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[69][4]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.389ns (logic 0.608ns (5.853%) route 9.781ns (94.147%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.552 7.712 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X152Y193 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[69][4]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X152Y193 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[69][4]/C clock pessimism -0.514 37.281 clock uncertainty -0.077 37.204 SLICE_X152Y193 FDCE (Recov_fdce_C_CLR) -0.527 36.677 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[69][4] ------------------------------------------------------------------- required time 36.677 arrival time -7.712 ------------------------------------------------------------------- slack 28.965 Slack (MET) : 28.972ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[9][0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.573ns (logic 0.608ns (5.750%) route 9.965ns (94.250%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 37.986 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.737 7.897 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X148Y204 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[9][0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.814 37.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X148Y204 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[9][0]/C clock pessimism -0.514 37.472 clock uncertainty -0.077 37.396 SLICE_X148Y204 FDCE (Recov_fdce_C_CLR) -0.527 36.869 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[9][0] ------------------------------------------------------------------- required time 36.869 arrival time -7.897 ------------------------------------------------------------------- slack 28.972 Slack (MET) : 28.993ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.363ns (logic 0.608ns (5.867%) route 9.755ns (94.133%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.041ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.527 7.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X154Y197 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.625 37.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X154Y197 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][0]/C clock pessimism -0.514 37.283 clock uncertainty -0.077 37.206 SLICE_X154Y197 FDCE (Recov_fdce_C_CLR) -0.527 36.679 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][0] ------------------------------------------------------------------- required time 36.679 arrival time -7.687 ------------------------------------------------------------------- slack 28.993 Slack (MET) : 28.993ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][2]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.363ns (logic 0.608ns (5.867%) route 9.755ns (94.133%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.041ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.527 7.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X154Y197 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.625 37.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X154Y197 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][2]/C clock pessimism -0.514 37.283 clock uncertainty -0.077 37.206 SLICE_X154Y197 FDCE (Recov_fdce_C_CLR) -0.527 36.679 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][2] ------------------------------------------------------------------- required time 36.679 arrival time -7.687 ------------------------------------------------------------------- slack 28.993 Slack (MET) : 28.993ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][4]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.363ns (logic 0.608ns (5.867%) route 9.755ns (94.133%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.041ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.527 7.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X154Y197 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][4]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.625 37.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X154Y197 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][4]/C clock pessimism -0.514 37.283 clock uncertainty -0.077 37.206 SLICE_X154Y197 FDCE (Recov_fdce_C_CLR) -0.527 36.679 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][4] ------------------------------------------------------------------- required time 36.679 arrival time -7.687 ------------------------------------------------------------------- slack 28.993 Slack (MET) : 28.994ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][30]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.364ns (logic 0.608ns (5.866%) route 9.756ns (94.134%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.023 -1.198 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.152 -1.046 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 8.733 7.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X52Y129 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][30]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X52Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][30]/C clock pessimism -0.435 37.279 clock uncertainty -0.077 37.203 SLICE_X52Y129 FDCE (Recov_fdce_C_CLR) -0.521 36.682 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][30] ------------------------------------------------------------------- required time 36.682 arrival time -7.688 ------------------------------------------------------------------- slack 28.994 Slack (MET) : 28.995ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[85][0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.359ns (logic 0.608ns (5.869%) route 9.751ns (94.131%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.523 7.682 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X150Y195 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[85][0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X150Y195 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[85][0]/C clock pessimism -0.514 37.281 clock uncertainty -0.077 37.204 SLICE_X150Y195 FDCE (Recov_fdce_C_CLR) -0.527 36.677 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[85][0] ------------------------------------------------------------------- required time 36.677 arrival time -7.682 ------------------------------------------------------------------- slack 28.995 Slack (MET) : 28.995ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[85][1]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.359ns (logic 0.608ns (5.869%) route 9.751ns (94.131%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.523 7.682 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X150Y195 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[85][1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X150Y195 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[85][1]/C clock pessimism -0.514 37.281 clock uncertainty -0.077 37.204 SLICE_X150Y195 FDCE (Recov_fdce_C_CLR) -0.527 36.677 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[85][1] ------------------------------------------------------------------- required time 36.677 arrival time -7.682 ------------------------------------------------------------------- slack 28.995 Slack (MET) : 29.006ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[95][0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.347ns (logic 0.608ns (5.876%) route 9.739ns (94.124%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.511 7.671 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X152Y196 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[95][0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X152Y196 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[95][0]/C clock pessimism -0.514 37.281 clock uncertainty -0.077 37.204 SLICE_X152Y196 FDCE (Recov_fdce_C_CLR) -0.527 36.677 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[95][0] ------------------------------------------------------------------- required time 36.677 arrival time -7.671 ------------------------------------------------------------------- slack 29.006 Slack (MET) : 29.011ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][5]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.344ns (logic 0.608ns (5.878%) route 9.736ns (94.122%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.507 7.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X150Y197 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][5]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X150Y197 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][5]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X150Y197 FDCE (Recov_fdce_C_CLR) -0.527 36.678 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[71][5] ------------------------------------------------------------------- required time 36.678 arrival time -7.667 ------------------------------------------------------------------- slack 29.011 Slack (MET) : 29.011ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[71][0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.344ns (logic 0.608ns (5.878%) route 9.736ns (94.122%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.507 7.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X150Y197 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[71][0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X150Y197 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[71][0]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X150Y197 FDCE (Recov_fdce_C_CLR) -0.527 36.678 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[71][0] ------------------------------------------------------------------- required time 36.678 arrival time -7.667 ------------------------------------------------------------------- slack 29.011 Slack (MET) : 29.018ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[11][6]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.336ns (logic 0.608ns (5.882%) route 9.728ns (94.118%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.499 7.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X146Y199 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[11][6]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X146Y199 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[11][6]/C clock pessimism -0.514 37.281 clock uncertainty -0.077 37.204 SLICE_X146Y199 FDCE (Recov_fdce_C_CLR) -0.527 36.677 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[11][6] ------------------------------------------------------------------- required time 36.677 arrival time -7.659 ------------------------------------------------------------------- slack 29.018 Slack (MET) : 29.020ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[69][2]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.334ns (logic 0.608ns (5.883%) route 9.726ns (94.117%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.498 7.658 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X150Y198 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[69][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X150Y198 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[69][2]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X150Y198 FDCE (Recov_fdce_C_CLR) -0.527 36.678 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[69][2] ------------------------------------------------------------------- required time 36.678 arrival time -7.658 ------------------------------------------------------------------- slack 29.020 Slack (MET) : 29.024ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[73][4]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.243ns (logic 0.608ns (5.936%) route 9.635ns (94.064%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.207ns = ( 37.793 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.406 7.566 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X153Y192 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[73][4]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.622 37.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X153Y192 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[73][4]/C clock pessimism -0.514 37.280 clock uncertainty -0.077 37.203 SLICE_X153Y192 FDCE (Recov_fdce_C_CLR) -0.613 36.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[73][4] ------------------------------------------------------------------- required time 36.590 arrival time -7.566 ------------------------------------------------------------------- slack 29.024 Slack (MET) : 29.024ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[73][6]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.243ns (logic 0.608ns (5.936%) route 9.635ns (94.064%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.207ns = ( 37.793 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.406 7.566 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X153Y192 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[73][6]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.622 37.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X153Y192 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[73][6]/C clock pessimism -0.514 37.280 clock uncertainty -0.077 37.203 SLICE_X153Y192 FDCE (Recov_fdce_C_CLR) -0.613 36.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[73][6] ------------------------------------------------------------------- required time 36.590 arrival time -7.566 ------------------------------------------------------------------- slack 29.024 Slack (MET) : 29.024ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[73][2]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.243ns (logic 0.608ns (5.936%) route 9.635ns (94.064%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.207ns = ( 37.793 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.406 7.566 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X153Y192 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[73][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.622 37.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X153Y192 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[73][2]/C clock pessimism -0.514 37.280 clock uncertainty -0.077 37.203 SLICE_X153Y192 FDCE (Recov_fdce_C_CLR) -0.613 36.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[73][2] ------------------------------------------------------------------- required time 36.590 arrival time -7.566 ------------------------------------------------------------------- slack 29.024 Slack (MET) : 29.024ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[3][0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.435ns (logic 0.608ns (5.827%) route 9.827ns (94.173%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 37.986 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.599 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X149Y203 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[3][0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.814 37.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X149Y203 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[3][0]/C clock pessimism -0.514 37.472 clock uncertainty -0.077 37.396 SLICE_X149Y203 FDCE (Recov_fdce_C_CLR) -0.613 36.783 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[3][0] ------------------------------------------------------------------- required time 36.783 arrival time -7.758 ------------------------------------------------------------------- slack 29.024 Slack (MET) : 29.024ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[3][2]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.435ns (logic 0.608ns (5.827%) route 9.827ns (94.173%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 37.986 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.599 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X149Y203 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[3][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.814 37.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X149Y203 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[3][2]/C clock pessimism -0.514 37.472 clock uncertainty -0.077 37.396 SLICE_X149Y203 FDCE (Recov_fdce_C_CLR) -0.613 36.783 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[3][2] ------------------------------------------------------------------- required time 36.783 arrival time -7.758 ------------------------------------------------------------------- slack 29.024 Slack (MET) : 29.032ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.427ns (logic 0.608ns (5.831%) route 9.819ns (94.169%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 37.986 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.591 7.751 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X145Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.814 37.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X145Y205 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][0]/C clock pessimism -0.514 37.472 clock uncertainty -0.077 37.396 SLICE_X145Y205 FDCE (Recov_fdce_C_CLR) -0.613 36.783 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][0] ------------------------------------------------------------------- required time 36.783 arrival time -7.751 ------------------------------------------------------------------- slack 29.032 Slack (MET) : 29.032ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][2]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.427ns (logic 0.608ns (5.831%) route 9.819ns (94.169%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 37.986 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.591 7.751 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X145Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.814 37.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X145Y205 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][2]/C clock pessimism -0.514 37.472 clock uncertainty -0.077 37.396 SLICE_X145Y205 FDCE (Recov_fdce_C_CLR) -0.613 36.783 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][2] ------------------------------------------------------------------- required time 36.783 arrival time -7.751 ------------------------------------------------------------------- slack 29.032 Slack (MET) : 29.032ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][5]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.427ns (logic 0.608ns (5.831%) route 9.819ns (94.169%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 37.986 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.591 7.751 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X145Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][5]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.814 37.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X145Y205 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][5]/C clock pessimism -0.514 37.472 clock uncertainty -0.077 37.396 SLICE_X145Y205 FDCE (Recov_fdce_C_CLR) -0.613 36.783 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[23][5] ------------------------------------------------------------------- required time 36.783 arrival time -7.751 ------------------------------------------------------------------- slack 29.032 Slack (MET) : 29.042ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[81][0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.312ns (logic 0.608ns (5.896%) route 9.704ns (94.104%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.476 7.636 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X154Y195 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[81][0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X154Y195 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[81][0]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X154Y195 FDCE (Recov_fdce_C_CLR) -0.527 36.678 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[81][0] ------------------------------------------------------------------- required time 36.678 arrival time -7.636 ------------------------------------------------------------------- slack 29.042 Slack (MET) : 29.043ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][27]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.315ns (logic 0.608ns (5.894%) route 9.707ns (94.106%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.045ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.287ns = ( 37.713 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.023 -1.198 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.152 -1.046 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 8.684 7.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X52Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][27]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.541 37.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X52Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][27]/C clock pessimism -0.435 37.278 clock uncertainty -0.077 37.202 SLICE_X52Y128 FDCE (Recov_fdce_C_CLR) -0.521 36.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][27] ------------------------------------------------------------------- required time 36.681 arrival time -7.638 ------------------------------------------------------------------- slack 29.043 Slack (MET) : 29.043ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.315ns (logic 0.608ns (5.894%) route 9.707ns (94.106%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.045ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.287ns = ( 37.713 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.023 -1.198 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.152 -1.046 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 8.684 7.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X52Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.541 37.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X52Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28]/C clock pessimism -0.435 37.278 clock uncertainty -0.077 37.202 SLICE_X52Y128 FDCE (Recov_fdce_C_CLR) -0.521 36.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28] ------------------------------------------------------------------- required time 36.681 arrival time -7.638 ------------------------------------------------------------------- slack 29.043 Slack (MET) : 29.043ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][31]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.315ns (logic 0.608ns (5.894%) route 9.707ns (94.106%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.045ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.287ns = ( 37.713 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.023 -1.198 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.152 -1.046 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 8.684 7.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X52Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][31]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.541 37.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X52Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][31]/C clock pessimism -0.435 37.278 clock uncertainty -0.077 37.202 SLICE_X52Y128 FDCE (Recov_fdce_C_CLR) -0.521 36.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][31] ------------------------------------------------------------------- required time 36.681 arrival time -7.638 ------------------------------------------------------------------- slack 29.043 Slack (MET) : 29.043ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[19][0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.414ns (logic 0.608ns (5.838%) route 9.806ns (94.162%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.147ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.016ns = ( 37.984 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.578 7.738 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X143Y207 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[19][0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.812 37.984 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X143Y207 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[19][0]/C clock pessimism -0.514 37.470 clock uncertainty -0.077 37.394 SLICE_X143Y207 FDCE (Recov_fdce_C_CLR) -0.613 36.781 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[19][0] ------------------------------------------------------------------- required time 36.781 arrival time -7.738 ------------------------------------------------------------------- slack 29.043 Slack (MET) : 29.044ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[81][4]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.311ns (logic 0.608ns (5.897%) route 9.703ns (94.103%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.475 7.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X154Y193 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[81][4]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X154Y193 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[81][4]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X154Y193 FDCE (Recov_fdce_C_CLR) -0.527 36.678 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[81][4] ------------------------------------------------------------------- required time 36.678 arrival time -7.634 ------------------------------------------------------------------- slack 29.044 Slack (MET) : 29.051ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[248][2]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.371ns (logic 0.608ns (5.862%) route 9.763ns (94.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.138ns = ( 37.862 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.535 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X158Y183 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[248][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.691 37.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X158Y183 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[248][2]/C clock pessimism -0.514 37.349 clock uncertainty -0.077 37.272 SLICE_X158Y183 FDCE (Recov_fdce_C_CLR) -0.527 36.745 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[248][2] ------------------------------------------------------------------- required time 36.745 arrival time -7.695 ------------------------------------------------------------------- slack 29.051 Slack (MET) : 29.051ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[248][6]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.371ns (logic 0.608ns (5.862%) route 9.763ns (94.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.138ns = ( 37.862 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.535 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X158Y183 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[248][6]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.691 37.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X158Y183 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[248][6]/C clock pessimism -0.514 37.349 clock uncertainty -0.077 37.272 SLICE_X158Y183 FDCE (Recov_fdce_C_CLR) -0.527 36.745 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[248][6] ------------------------------------------------------------------- required time 36.745 arrival time -7.695 ------------------------------------------------------------------- slack 29.051 Slack (MET) : 29.054ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[81][0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.215ns (logic 0.608ns (5.952%) route 9.607ns (94.048%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.378 7.538 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X149Y197 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[81][0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.624 37.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X149Y197 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[81][0]/C clock pessimism -0.514 37.282 clock uncertainty -0.077 37.205 SLICE_X149Y197 FDCE (Recov_fdce_C_CLR) -0.613 36.592 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[81][0] ------------------------------------------------------------------- required time 36.592 arrival time -7.538 ------------------------------------------------------------------- slack 29.054 Slack (MET) : 29.055ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[75][1]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.213ns (logic 0.608ns (5.953%) route 9.605ns (94.047%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.377 7.537 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X151Y194 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[75][1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X151Y194 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[75][1]/C clock pessimism -0.514 37.281 clock uncertainty -0.077 37.204 SLICE_X151Y194 FDCE (Recov_fdce_C_CLR) -0.613 36.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[75][1] ------------------------------------------------------------------- required time 36.591 arrival time -7.537 ------------------------------------------------------------------- slack 29.055 Slack (MET) : 29.061ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[21][6]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.207ns (logic 0.608ns (5.957%) route 9.599ns (94.043%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.370 7.530 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X145Y199 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[21][6]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.623 37.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X145Y199 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[21][6]/C clock pessimism -0.514 37.281 clock uncertainty -0.077 37.204 SLICE_X145Y199 FDCE (Recov_fdce_C_CLR) -0.613 36.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[21][6] ------------------------------------------------------------------- required time 36.591 arrival time -7.530 ------------------------------------------------------------------- slack 29.061 Slack (MET) : 29.066ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[21][5]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 10.393ns (logic 0.608ns (5.850%) route 9.785ns (94.150%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 37.986 - 40.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.228 -0.992 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg_3[0] SLICE_X57Y104 LUT5 (Prop_lut5_I0_O) 0.152 -0.840 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 8.557 7.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X147Y204 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[21][5]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.814 37.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X147Y204 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[21][5]/C clock pessimism -0.514 37.472 clock uncertainty -0.077 37.396 SLICE_X147Y204 FDCE (Recov_fdce_C_CLR) -0.613 36.783 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[21][5] ------------------------------------------------------------------- required time 36.783 arrival time -7.717 ------------------------------------------------------------------- slack 29.066 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk To Clock: mlkem_clk_clk_pll Setup : 0 Failing Endpoints, Worst Slack 8.522ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 8.522ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 10.488ns (logic 0.642ns (6.121%) route 9.846ns (93.879%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.283ns = ( 37.717 - 40.000 ) Source Clock Delay (SCD): -2.496ns = ( 17.504 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 17.504 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 18.022 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 21.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 21.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.318 27.992 pll_clk.u_rst_mlkem/prst SLICE_X67Y102 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.545 37.717 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[0]/C clock pessimism -0.601 37.116 clock uncertainty -0.197 36.920 SLICE_X67Y102 FDCE (Recov_fdce_C_CLR) -0.405 36.515 pll_clk.u_rst_mlkem/delay_reg[0] ------------------------------------------------------------------- required time 36.515 arrival time -27.992 ------------------------------------------------------------------- slack 8.522 Slack (MET) : 8.522ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 10.488ns (logic 0.642ns (6.121%) route 9.846ns (93.879%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.283ns = ( 37.717 - 40.000 ) Source Clock Delay (SCD): -2.496ns = ( 17.504 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 17.504 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 18.022 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 21.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 21.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.318 27.992 pll_clk.u_rst_mlkem/prst SLICE_X67Y102 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.545 37.717 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C clock pessimism -0.601 37.116 clock uncertainty -0.197 36.920 SLICE_X67Y102 FDCE (Recov_fdce_C_CLR) -0.405 36.515 pll_clk.u_rst_mlkem/delay_reg[1] ------------------------------------------------------------------- required time 36.515 arrival time -27.992 ------------------------------------------------------------------- slack 8.522 Slack (MET) : 8.949ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 10.266ns (logic 0.642ns (6.254%) route 9.624ns (93.746%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.122ns = ( 37.878 - 40.000 ) Source Clock Delay (SCD): -2.496ns = ( 17.504 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 17.504 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 18.022 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 21.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 21.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.096 27.770 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/prst SLICE_X70Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.706 37.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C clock pessimism -0.601 37.277 clock uncertainty -0.197 37.080 SLICE_X70Y96 FDCE (Recov_fdce_C_CLR) -0.361 36.719 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg ------------------------------------------------------------------- required time 36.719 arrival time -27.770 ------------------------------------------------------------------- slack 8.949 Slack (MET) : 8.991ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 10.266ns (logic 0.642ns (6.254%) route 9.624ns (93.746%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.122ns = ( 37.878 - 40.000 ) Source Clock Delay (SCD): -2.496ns = ( 17.504 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 17.504 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 18.022 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 21.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 21.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.096 27.770 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/prst SLICE_X70Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.706 37.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C clock pessimism -0.601 37.277 clock uncertainty -0.197 37.080 SLICE_X70Y96 FDCE (Recov_fdce_C_CLR) -0.319 36.761 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg ------------------------------------------------------------------- required time 36.761 arrival time -27.770 ------------------------------------------------------------------- slack 8.991 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: mlkem_clk_clk_pll To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 16.719ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 16.719ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.477ns (logic 0.608ns (24.543%) route 1.869ns (75.457%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.119ns = ( 17.881 - 20.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.023 -1.198 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.152 -1.046 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.846 -0.199 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 SLICE_X68Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.709 17.881 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C clock pessimism -0.601 17.280 clock uncertainty -0.197 17.083 SLICE_X68Y94 FDCE (Recov_fdce_C_CLR) -0.563 16.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg ------------------------------------------------------------------- required time 16.520 arrival time 0.199 ------------------------------------------------------------------- slack 16.719 Slack (MET) : 16.761ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.477ns (logic 0.608ns (24.543%) route 1.869ns (75.457%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.119ns = ( 17.881 - 20.000 ) Source Clock Delay (SCD): -2.677ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 1.665 -2.677 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.023 -1.198 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.152 -1.046 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.846 -0.199 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 SLICE_X68Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.709 17.881 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C clock pessimism -0.601 17.280 clock uncertainty -0.197 17.083 SLICE_X68Y94 FDCE (Recov_fdce_C_CLR) -0.521 16.562 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg ------------------------------------------------------------------- required time 16.562 arrival time 0.199 ------------------------------------------------------------------- slack 16.761 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 5.353ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.353ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.257ns (logic 0.642ns (4.503%) route 13.615ns (95.497%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 10.087 11.761 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X122Y7 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.917 18.088 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X122Y7 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[5]/C clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X122Y7 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[5] ------------------------------------------------------------------- required time 17.114 arrival time -11.761 ------------------------------------------------------------------- slack 5.353 Slack (MET) : 5.353ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.257ns (logic 0.642ns (4.503%) route 13.615ns (95.497%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 10.087 11.761 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X122Y7 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.917 18.088 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X122Y7 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[6]/C clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X122Y7 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[6] ------------------------------------------------------------------- required time 17.114 arrival time -11.761 ------------------------------------------------------------------- slack 5.353 Slack (MET) : 5.353ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.257ns (logic 0.642ns (4.503%) route 13.615ns (95.497%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 10.087 11.761 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X122Y7 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.917 18.088 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X122Y7 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[7]/C clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X122Y7 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[7] ------------------------------------------------------------------- required time 17.114 arrival time -11.761 ------------------------------------------------------------------- slack 5.353 Slack (MET) : 5.365ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.245ns (logic 0.642ns (4.507%) route 13.603ns (95.493%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 10.075 11.749 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X121Y7 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.917 18.088 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X121Y7 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[0]/C clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X121Y7 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[0] ------------------------------------------------------------------- required time 17.114 arrival time -11.749 ------------------------------------------------------------------- slack 5.365 Slack (MET) : 5.365ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.245ns (logic 0.642ns (4.507%) route 13.603ns (95.493%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 10.075 11.749 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X121Y7 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.917 18.088 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X121Y7 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8]/C clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X121Y7 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8] ------------------------------------------------------------------- required time 17.114 arrival time -11.749 ------------------------------------------------------------------- slack 5.365 Slack (MET) : 5.365ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.245ns (logic 0.642ns (4.507%) route 13.603ns (95.493%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 10.075 11.749 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X121Y7 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.917 18.088 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X121Y7 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9]/C clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X121Y7 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9] ------------------------------------------------------------------- required time 17.114 arrival time -11.749 ------------------------------------------------------------------- slack 5.365 Slack (MET) : 5.365ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.245ns (logic 0.642ns (4.507%) route 13.603ns (95.493%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 10.075 11.749 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X121Y7 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.917 18.088 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X121Y7 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg/C clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X121Y7 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg ------------------------------------------------------------------- required time 17.114 arrival time -11.749 ------------------------------------------------------------------- slack 5.365 Slack (MET) : 5.494ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.116ns (logic 0.642ns (4.548%) route 13.474ns (95.452%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 9.946 11.621 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X122Y8 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.917 18.088 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X122Y8 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2]/C clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X122Y8 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2] ------------------------------------------------------------------- required time 17.114 arrival time -11.621 ------------------------------------------------------------------- slack 5.494 Slack (MET) : 5.494ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.116ns (logic 0.642ns (4.548%) route 13.474ns (95.452%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 9.946 11.621 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X122Y8 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.917 18.088 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X122Y8 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3]/C clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X122Y8 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3] ------------------------------------------------------------------- required time 17.114 arrival time -11.621 ------------------------------------------------------------------- slack 5.494 Slack (MET) : 5.494ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.116ns (logic 0.642ns (4.548%) route 13.474ns (95.452%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 9.946 11.621 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X122Y8 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.917 18.088 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X122Y8 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4]/C clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X122Y8 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4] ------------------------------------------------------------------- required time 17.114 arrival time -11.621 ------------------------------------------------------------------- slack 5.494 Slack (MET) : 5.592ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.104ns (logic 0.642ns (4.552%) route 13.462ns (95.448%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 9.934 11.609 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X120Y8 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.917 18.088 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X120Y8 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1]/C clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X120Y8 FDCE (Recov_fdce_C_CLR) -0.319 17.200 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1] ------------------------------------------------------------------- required time 17.200 arrival time -11.609 ------------------------------------------------------------------- slack 5.592 Slack (MET) : 6.161ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.434ns (logic 0.642ns (4.779%) route 12.792ns (95.221%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 9.265 10.939 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X118Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.902 18.073 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X118Y23 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[6]/C clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X118Y23 FDCE (Recov_fdce_C_CLR) -0.405 17.099 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[6] ------------------------------------------------------------------- required time 17.099 arrival time -10.939 ------------------------------------------------------------------- slack 6.161 Slack (MET) : 6.161ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.434ns (logic 0.642ns (4.779%) route 12.792ns (95.221%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 9.265 10.939 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X118Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.902 18.073 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X118Y23 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[7]/C clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X118Y23 FDCE (Recov_fdce_C_CLR) -0.405 17.099 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[7] ------------------------------------------------------------------- required time 17.099 arrival time -10.939 ------------------------------------------------------------------- slack 6.161 Slack (MET) : 6.161ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.434ns (logic 0.642ns (4.779%) route 12.792ns (95.221%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 9.265 10.939 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X118Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.902 18.073 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X118Y23 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[8]/C clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X118Y23 FDCE (Recov_fdce_C_CLR) -0.405 17.099 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[8] ------------------------------------------------------------------- required time 17.099 arrival time -10.939 ------------------------------------------------------------------- slack 6.161 Slack (MET) : 6.495ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.100ns (logic 0.642ns (4.901%) route 12.458ns (95.099%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.930 10.604 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X117Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.902 18.073 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X117Y23 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[5]/C clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X117Y23 FDCE (Recov_fdce_C_CLR) -0.405 17.099 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[5] ------------------------------------------------------------------- required time 17.099 arrival time -10.604 ------------------------------------------------------------------- slack 6.495 Slack (MET) : 6.495ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.100ns (logic 0.642ns (4.901%) route 12.458ns (95.099%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.930 10.604 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X117Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.902 18.073 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X117Y23 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[9]/C clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X117Y23 FDCE (Recov_fdce_C_CLR) -0.405 17.099 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[9] ------------------------------------------------------------------- required time 17.099 arrival time -10.604 ------------------------------------------------------------------- slack 6.495 Slack (MET) : 6.495ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_sp_en_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.100ns (logic 0.642ns (4.901%) route 12.458ns (95.099%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.930 10.604 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X117Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_sp_en_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.902 18.073 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X117Y23 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_sp_en_reg/C clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X117Y23 FDCE (Recov_fdce_C_CLR) -0.405 17.099 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_sp_en_reg ------------------------------------------------------------------- required time 17.099 arrival time -10.604 ------------------------------------------------------------------- slack 6.495 Slack (MET) : 6.539ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.100ns (logic 0.642ns (4.901%) route 12.458ns (95.099%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.930 10.604 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.902 18.073 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X116Y23 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[1]/C clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X116Y23 FDCE (Recov_fdce_C_CLR) -0.361 17.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[1] ------------------------------------------------------------------- required time 17.143 arrival time -10.604 ------------------------------------------------------------------- slack 6.539 Slack (MET) : 6.539ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.100ns (logic 0.642ns (4.901%) route 12.458ns (95.099%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.930 10.604 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.902 18.073 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X116Y23 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[3]/C clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X116Y23 FDCE (Recov_fdce_C_CLR) -0.361 17.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[3] ------------------------------------------------------------------- required time 17.143 arrival time -10.604 ------------------------------------------------------------------- slack 6.539 Slack (MET) : 6.581ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.100ns (logic 0.642ns (4.901%) route 12.458ns (95.099%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.930 10.604 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.902 18.073 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X116Y23 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[2]/C clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X116Y23 FDCE (Recov_fdce_C_CLR) -0.319 17.185 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[2] ------------------------------------------------------------------- required time 17.185 arrival time -10.604 ------------------------------------------------------------------- slack 6.581 Slack (MET) : 6.581ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.100ns (logic 0.642ns (4.901%) route 12.458ns (95.099%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.930 10.604 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.902 18.073 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X116Y23 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[4]/C clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X116Y23 FDCE (Recov_fdce_C_CLR) -0.319 17.185 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[4] ------------------------------------------------------------------- required time 17.185 arrival time -10.604 ------------------------------------------------------------------- slack 6.581 Slack (MET) : 6.685ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.908ns (logic 0.642ns (4.974%) route 12.266ns (95.026%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.069ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.929ns = ( 18.071 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.739 10.413 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X117Y25 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.900 18.071 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X117Y25 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[7]/C clock pessimism -0.498 17.573 clock uncertainty -0.071 17.502 SLICE_X117Y25 FDCE (Recov_fdce_C_CLR) -0.405 17.097 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[7] ------------------------------------------------------------------- required time 17.097 arrival time -10.413 ------------------------------------------------------------------- slack 6.685 Slack (MET) : 6.685ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.908ns (logic 0.642ns (4.974%) route 12.266ns (95.026%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.069ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.929ns = ( 18.071 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.739 10.413 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X117Y25 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.900 18.071 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X117Y25 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[8]/C clock pessimism -0.498 17.573 clock uncertainty -0.071 17.502 SLICE_X117Y25 FDCE (Recov_fdce_C_CLR) -0.405 17.097 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[8] ------------------------------------------------------------------- required time 17.097 arrival time -10.413 ------------------------------------------------------------------- slack 6.685 Slack (MET) : 6.685ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.908ns (logic 0.642ns (4.974%) route 12.266ns (95.026%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.069ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.929ns = ( 18.071 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.739 10.413 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X117Y25 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.900 18.071 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X117Y25 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[9]/C clock pessimism -0.498 17.573 clock uncertainty -0.071 17.502 SLICE_X117Y25 FDCE (Recov_fdce_C_CLR) -0.405 17.097 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[9] ------------------------------------------------------------------- required time 17.097 arrival time -10.413 ------------------------------------------------------------------- slack 6.685 Slack (MET) : 6.771ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.908ns (logic 0.642ns (4.974%) route 12.266ns (95.026%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.069ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.929ns = ( 18.071 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.739 10.413 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y25 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.900 18.071 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X116Y25 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[6]/C clock pessimism -0.498 17.573 clock uncertainty -0.071 17.502 SLICE_X116Y25 FDCE (Recov_fdce_C_CLR) -0.319 17.183 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[6] ------------------------------------------------------------------- required time 17.183 arrival time -10.413 ------------------------------------------------------------------- slack 6.771 Slack (MET) : 6.831ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.850ns (logic 0.642ns (4.996%) route 12.208ns (95.004%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.680 10.354 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y26 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.902 18.073 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X116Y26 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[4]/C clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X116Y26 FDCE (Recov_fdce_C_CLR) -0.319 17.185 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[4] ------------------------------------------------------------------- required time 17.185 arrival time -10.354 ------------------------------------------------------------------- slack 6.831 Slack (MET) : 6.831ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.850ns (logic 0.642ns (4.996%) route 12.208ns (95.004%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.680 10.354 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y26 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.902 18.073 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X116Y26 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[5]/C clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X116Y26 FDCE (Recov_fdce_C_CLR) -0.319 17.185 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[5] ------------------------------------------------------------------- required time 17.185 arrival time -10.354 ------------------------------------------------------------------- slack 6.831 Slack (MET) : 6.839ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_do_en_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.803ns (logic 0.642ns (5.014%) route 12.161ns (94.986%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.074ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.924ns = ( 18.076 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.633 10.308 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y21 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_do_en_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.905 18.076 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X116Y21 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_do_en_reg/C clock pessimism -0.498 17.578 clock uncertainty -0.071 17.507 SLICE_X116Y21 FDCE (Recov_fdce_C_CLR) -0.361 17.146 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_do_en_reg ------------------------------------------------------------------- required time 17.146 arrival time -10.308 ------------------------------------------------------------------- slack 6.839 Slack (MET) : 6.873ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/req_addr_q_reg[20]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.789ns (logic 0.642ns (5.020%) route 12.147ns (94.980%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns = ( 18.068 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.619 10.293 u_axi_ram/u_axi_sram_sp/prst SLICE_X0Y63 FDCE f u_axi_ram/u_axi_sram_sp/req_addr_q_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.896 18.068 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X0Y63 FDCE r u_axi_ram/u_axi_sram_sp/req_addr_q_reg[20]/C clock pessimism -0.426 17.641 clock uncertainty -0.071 17.571 SLICE_X0Y63 FDCE (Recov_fdce_C_CLR) -0.405 17.166 u_axi_ram/u_axi_sram_sp/req_addr_q_reg[20] ------------------------------------------------------------------- required time 17.166 arrival time -10.293 ------------------------------------------------------------------- slack 6.873 Slack (MET) : 6.877ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/req_addr_q_reg[17]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.784ns (logic 0.642ns (5.022%) route 12.142ns (94.978%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns = ( 18.068 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.614 10.289 u_axi_ram/u_axi_sram_sp/prst SLICE_X1Y63 FDCE f u_axi_ram/u_axi_sram_sp/req_addr_q_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.896 18.068 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X1Y63 FDCE r u_axi_ram/u_axi_sram_sp/req_addr_q_reg[17]/C clock pessimism -0.426 17.641 clock uncertainty -0.071 17.571 SLICE_X1Y63 FDCE (Recov_fdce_C_CLR) -0.405 17.166 u_axi_ram/u_axi_sram_sp/req_addr_q_reg[17] ------------------------------------------------------------------- required time 17.166 arrival time -10.289 ------------------------------------------------------------------- slack 6.877 Slack (MET) : 6.881ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.803ns (logic 0.642ns (5.014%) route 12.161ns (94.986%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.074ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.924ns = ( 18.076 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.633 10.308 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y21 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.905 18.076 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X116Y21 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[0]/C clock pessimism -0.498 17.578 clock uncertainty -0.071 17.507 SLICE_X116Y21 FDCE (Recov_fdce_C_CLR) -0.319 17.188 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[0] ------------------------------------------------------------------- required time 17.188 arrival time -10.308 ------------------------------------------------------------------- slack 6.881 Slack (MET) : 7.079ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.561ns (logic 0.642ns (5.111%) route 11.919ns (94.889%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.072ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.926ns = ( 18.074 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.392 10.066 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y27 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.903 18.074 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X116Y27 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[1]/C clock pessimism -0.498 17.576 clock uncertainty -0.071 17.505 SLICE_X116Y27 FDCE (Recov_fdce_C_CLR) -0.361 17.144 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[1] ------------------------------------------------------------------- required time 17.144 arrival time -10.066 ------------------------------------------------------------------- slack 7.079 Slack (MET) : 7.079ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.561ns (logic 0.642ns (5.111%) route 11.919ns (94.889%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.072ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.926ns = ( 18.074 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.392 10.066 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y27 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.903 18.074 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X116Y27 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[3]/C clock pessimism -0.498 17.576 clock uncertainty -0.071 17.505 SLICE_X116Y27 FDCE (Recov_fdce_C_CLR) -0.361 17.144 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[3] ------------------------------------------------------------------- required time 17.144 arrival time -10.066 ------------------------------------------------------------------- slack 7.079 Slack (MET) : 7.121ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.561ns (logic 0.642ns (5.111%) route 11.919ns (94.889%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.072ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.926ns = ( 18.074 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.392 10.066 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y27 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.903 18.074 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X116Y27 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[0]/C clock pessimism -0.498 17.576 clock uncertainty -0.071 17.505 SLICE_X116Y27 FDCE (Recov_fdce_C_CLR) -0.319 17.186 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[0] ------------------------------------------------------------------- required time 17.186 arrival time -10.066 ------------------------------------------------------------------- slack 7.121 Slack (MET) : 7.121ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.561ns (logic 0.642ns (5.111%) route 11.919ns (94.889%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.072ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.926ns = ( 18.074 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.392 10.066 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y27 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.903 18.074 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X116Y27 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[2]/C clock pessimism -0.498 17.576 clock uncertainty -0.071 17.505 SLICE_X116Y27 FDCE (Recov_fdce_C_CLR) -0.319 17.186 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[2] ------------------------------------------------------------------- required time 17.186 arrival time -10.066 ------------------------------------------------------------------- slack 7.121 Slack (MET) : 7.212ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.449ns (logic 0.642ns (5.157%) route 11.807ns (94.843%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns = ( 18.068 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.279 9.954 u_axi_ram/u_axi_sram_sp/prst SLICE_X3Y64 FDCE f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.896 18.068 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X3Y64 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[5]/C clock pessimism -0.426 17.641 clock uncertainty -0.071 17.571 SLICE_X3Y64 FDCE (Recov_fdce_C_CLR) -0.405 17.166 u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[5] ------------------------------------------------------------------- required time 17.166 arrival time -9.953 ------------------------------------------------------------------- slack 7.212 Slack (MET) : 7.487ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.173ns (logic 0.642ns (5.274%) route 11.531ns (94.726%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.933ns = ( 18.067 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.003 9.678 u_axi_ram/u_axi_sram_sp/prst SLICE_X0Y65 FDCE f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.895 18.067 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X0Y65 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C clock pessimism -0.426 17.640 clock uncertainty -0.071 17.570 SLICE_X0Y65 FDCE (Recov_fdce_C_CLR) -0.405 17.165 u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4] ------------------------------------------------------------------- required time 17.165 arrival time -9.678 ------------------------------------------------------------------- slack 7.487 Slack (MET) : 7.492ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.169ns (logic 0.642ns (5.276%) route 11.527ns (94.724%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.933ns = ( 18.067 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.999 9.673 u_axi_ram/u_axi_sram_sp/prst SLICE_X1Y65 FDCE f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.895 18.067 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X1Y65 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[6]/C clock pessimism -0.426 17.640 clock uncertainty -0.071 17.570 SLICE_X1Y65 FDCE (Recov_fdce_C_CLR) -0.405 17.165 u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[6] ------------------------------------------------------------------- required time 17.165 arrival time -9.673 ------------------------------------------------------------------- slack 7.492 Slack (MET) : 7.492ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.169ns (logic 0.642ns (5.276%) route 11.527ns (94.724%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.933ns = ( 18.067 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.999 9.673 u_axi_ram/u_axi_sram_sp/prst SLICE_X1Y65 FDCE f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.895 18.067 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X1Y65 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[7]/C clock pessimism -0.426 17.640 clock uncertainty -0.071 17.570 SLICE_X1Y65 FDCE (Recov_fdce_C_CLR) -0.405 17.165 u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[7] ------------------------------------------------------------------- required time 17.165 arrival time -9.673 ------------------------------------------------------------------- slack 7.492 Slack (MET) : 7.555ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.945ns (logic 0.642ns (5.375%) route 11.303ns (94.625%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.775 9.449 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X80Y92 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.691 17.863 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/sys_clk SLICE_X80Y92 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[1]/C clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X80Y92 FDCE (Recov_fdce_C_CLR) -0.361 17.005 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[1] ------------------------------------------------------------------- required time 17.005 arrival time -9.449 ------------------------------------------------------------------- slack 7.555 Slack (MET) : 7.555ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.945ns (logic 0.642ns (5.375%) route 11.303ns (94.625%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.775 9.449 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X80Y92 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.691 17.863 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/sys_clk SLICE_X80Y92 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[3]/C clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X80Y92 FDCE (Recov_fdce_C_CLR) -0.361 17.005 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[3] ------------------------------------------------------------------- required time 17.005 arrival time -9.449 ------------------------------------------------------------------- slack 7.555 Slack (MET) : 7.566ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/req_addr_q_reg[13]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.087ns (logic 0.642ns (5.312%) route 11.445ns (94.688%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.128ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.941ns = ( 18.059 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.917 9.591 u_axi_ram/u_axi_sram_sp/prst SLICE_X5Y71 FDCE f u_axi_ram/u_axi_sram_sp/req_addr_q_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.887 18.059 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X5Y71 FDCE r u_axi_ram/u_axi_sram_sp/req_addr_q_reg[13]/C clock pessimism -0.426 17.632 clock uncertainty -0.071 17.562 SLICE_X5Y71 FDCE (Recov_fdce_C_CLR) -0.405 17.157 u_axi_ram/u_axi_sram_sp/req_addr_q_reg[13] ------------------------------------------------------------------- required time 17.157 arrival time -9.591 ------------------------------------------------------------------- slack 7.566 Slack (MET) : 7.566ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/req_addr_q_reg[16]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.087ns (logic 0.642ns (5.312%) route 11.445ns (94.688%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.128ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.941ns = ( 18.059 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.917 9.591 u_axi_ram/u_axi_sram_sp/prst SLICE_X5Y71 FDCE f u_axi_ram/u_axi_sram_sp/req_addr_q_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.887 18.059 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X5Y71 FDCE r u_axi_ram/u_axi_sram_sp/req_addr_q_reg[16]/C clock pessimism -0.426 17.632 clock uncertainty -0.071 17.562 SLICE_X5Y71 FDCE (Recov_fdce_C_CLR) -0.405 17.157 u_axi_ram/u_axi_sram_sp/req_addr_q_reg[16] ------------------------------------------------------------------- required time 17.157 arrival time -9.591 ------------------------------------------------------------------- slack 7.566 Slack (MET) : 7.566ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/ax_req_q_addr_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.087ns (logic 0.642ns (5.311%) route 11.445ns (94.689%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.129ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.940ns = ( 18.060 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.918 9.592 u_axi_ram/u_axi_sram_sp/prst SLICE_X5Y69 FDCE f u_axi_ram/u_axi_sram_sp/ax_req_q_addr_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.888 18.060 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X5Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_addr_reg[7]/C clock pessimism -0.426 17.633 clock uncertainty -0.071 17.563 SLICE_X5Y69 FDCE (Recov_fdce_C_CLR) -0.405 17.158 u_axi_ram/u_axi_sram_sp/ax_req_q_addr_reg[7] ------------------------------------------------------------------- required time 17.158 arrival time -9.592 ------------------------------------------------------------------- slack 7.566 Slack (MET) : 7.597ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.945ns (logic 0.642ns (5.375%) route 11.303ns (94.625%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.775 9.449 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X80Y92 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.691 17.863 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/sys_clk SLICE_X80Y92 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[0]/C clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X80Y92 FDCE (Recov_fdce_C_CLR) -0.319 17.047 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[0] ------------------------------------------------------------------- required time 17.047 arrival time -9.449 ------------------------------------------------------------------- slack 7.597 Slack (MET) : 7.597ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.945ns (logic 0.642ns (5.375%) route 11.303ns (94.625%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.775 9.449 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X80Y92 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.691 17.863 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/sys_clk SLICE_X80Y92 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[2]/C clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X80Y92 FDCE (Recov_fdce_C_CLR) -0.319 17.047 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[2] ------------------------------------------------------------------- required time 17.047 arrival time -9.449 ------------------------------------------------------------------- slack 7.597 Slack (MET) : 7.597ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.945ns (logic 0.642ns (5.375%) route 11.303ns (94.625%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.775 9.449 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X80Y92 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.691 17.863 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/sys_clk SLICE_X80Y92 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[4]/C clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X80Y92 FDCE (Recov_fdce_C_CLR) -0.319 17.047 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[4] ------------------------------------------------------------------- required time 17.047 arrival time -9.449 ------------------------------------------------------------------- slack 7.597 Slack (MET) : 7.636ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.821ns (logic 0.642ns (5.431%) route 11.179ns (94.569%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.651 9.325 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X81Y91 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.691 17.863 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/sys_clk SLICE_X81Y91 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[6]/C clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X81Y91 FDCE (Recov_fdce_C_CLR) -0.405 16.961 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[6] ------------------------------------------------------------------- required time 16.961 arrival time -9.325 ------------------------------------------------------------------- slack 7.636 Slack (MET) : 7.636ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.821ns (logic 0.642ns (5.431%) route 11.179ns (94.569%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.651 9.325 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X81Y91 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.691 17.863 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/sys_clk SLICE_X81Y91 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[7]/C clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X81Y91 FDCE (Recov_fdce_C_CLR) -0.405 16.961 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[7] ------------------------------------------------------------------- required time 16.961 arrival time -9.325 ------------------------------------------------------------------- slack 7.636 Slack (MET) : 7.636ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.821ns (logic 0.642ns (5.431%) route 11.179ns (94.569%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.651 9.325 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X81Y91 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.691 17.863 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/sys_clk SLICE_X81Y91 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[8]/C clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X81Y91 FDCE (Recov_fdce_C_CLR) -0.405 16.961 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[8] ------------------------------------------------------------------- required time 16.961 arrival time -9.325 ------------------------------------------------------------------- slack 7.636 -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: cpu_clk Max Delay 59 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_cpu/delay_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 9.556ns (logic 0.642ns (6.718%) route 8.914ns (93.282%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.561ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.934ns Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 5.387 7.061 pll_clk.u_rst_cpu/prst SLICE_X6Y63 FDCE f pll_clk.u_rst_cpu/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.894 -1.934 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[0]/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_cpu/delay_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 9.556ns (logic 0.642ns (6.718%) route 8.914ns (93.282%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.561ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.934ns Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 5.387 7.061 pll_clk.u_rst_cpu/prst SLICE_X6Y63 FDCE f pll_clk.u_rst_cpu/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.894 -1.934 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 9.556ns (logic 0.642ns (6.718%) route 8.914ns (93.282%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.561ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.934ns Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 5.387 7.061 u_Axi_CDC/bFifo/bufferCC_12/prst SLICE_X6Y63 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.894 -1.934 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 9.556ns (logic 0.642ns (6.718%) route 8.914ns (93.282%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.561ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.934ns Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 5.387 7.061 u_Axi_CDC/bFifo/bufferCC_12/prst SLICE_X6Y63 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.894 -1.934 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.809ns (logic 0.612ns (33.833%) route 1.197ns (66.167%)) Logic Levels: 0 Clock Path Skew: -0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.503ns Source Clock Delay (SCD): -0.349ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.959 -0.349 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X12Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y71 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.263 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 1.197 1.460 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] SLICE_X9Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.760 -0.503 u_Axi_CDC/rFifo/cpu_clk SLICE_X9Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.748ns (logic 0.482ns (27.570%) route 1.266ns (72.430%)) Logic Levels: 0 Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.961 -0.347 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X10Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y70 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.135 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 1.266 1.401 u_Axi_CDC/rFifo/_zz_ram_port10__2[21] SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.737ns (logic 0.612ns (35.228%) route 1.125ns (64.772%)) Logic Levels: 0 Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.508ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X12Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y70 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.264 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 1.125 1.389 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] SLICE_X12Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.755 -0.508 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.734ns (logic 0.612ns (35.287%) route 1.122ns (64.713%)) Logic Levels: 0 Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.508ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X10Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y71 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.264 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 1.122 1.386 u_Axi_CDC/rFifo/_zz_ram_port10__2[24] SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.755 -0.508 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 3.779ns (logic 1.314ns (34.772%) route 2.465ns (65.228%)) Logic Levels: 0 Clock Path Skew: 0.564ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.845ns Source Clock Delay (SCD): -2.409ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.933 -2.409 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X12Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y71 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.095 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 2.465 1.370 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.984 -1.845 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.683ns (logic 0.595ns (35.348%) route 1.088ns (64.652%)) Logic Levels: 0 Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X10Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y71 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.247 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 1.088 1.335 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.650ns (logic 0.612ns (37.082%) route 1.038ns (62.918%)) Logic Levels: 0 Clock Path Skew: -0.158ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.505ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.961 -0.347 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X10Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y70 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.265 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 1.038 1.303 u_Axi_CDC/rFifo/_zz_ram_port10__2[18] SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 3.702ns (logic 1.317ns (35.572%) route 2.385ns (64.428%)) Logic Levels: 0 Clock Path Skew: 0.566ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.843ns Source Clock Delay (SCD): -2.409ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.933 -2.409 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X12Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y71 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.092 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 2.385 1.294 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] SLICE_X12Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.986 -1.843 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.602ns (logic 0.485ns (30.276%) route 1.117ns (69.724%)) Logic Levels: 0 Clock Path Skew: -0.157ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.505ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y70 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.137 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 1.117 1.254 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 3.653ns (logic 1.317ns (36.056%) route 2.336ns (63.944%)) Logic Levels: 0 Clock Path Skew: 0.561ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.846ns Source Clock Delay (SCD): -2.407ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.935 -2.407 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X10Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y71 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.090 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 2.336 1.246 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.983 -1.846 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.583ns (logic 0.480ns (30.319%) route 1.103ns (69.681%)) Logic Levels: 0 Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X12Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y70 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 1.103 1.235 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.582ns (logic 0.491ns (31.031%) route 1.091ns (68.969%)) Logic Levels: 0 Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X10Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y71 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.143 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 1.091 1.234 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.581ns (logic 0.482ns (30.488%) route 1.099ns (69.512%)) Logic Levels: 0 Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.508ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y70 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.134 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 1.099 1.233 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.755 -0.508 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.576ns (logic 0.595ns (37.763%) route 0.981ns (62.237%)) Logic Levels: 0 Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.508ns Source Clock Delay (SCD): -0.349ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.959 -0.349 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X12Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y71 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.246 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 0.981 1.226 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.755 -0.508 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.526ns (logic 0.595ns (39.003%) route 0.931ns (60.997%)) Logic Levels: 0 Clock Path Skew: -0.128ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.476ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y70 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.247 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.931 1.177 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] SLICE_X7Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.787 -0.476 u_Axi_CDC/rFifo/cpu_clk SLICE_X7Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.526ns (logic 0.491ns (32.182%) route 1.035ns (67.818%)) Logic Levels: 0 Clock Path Skew: -0.158ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.349ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.959 -0.349 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X12Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y71 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.142 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 1.035 1.177 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.516ns (logic 0.612ns (40.374%) route 0.904ns (59.626%)) Logic Levels: 0 Clock Path Skew: -0.157ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.505ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y70 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.264 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 0.904 1.168 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] SLICE_X12Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.515ns (logic 0.491ns (32.407%) route 1.024ns (67.593%)) Logic Levels: 0 Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y70 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.143 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 1.024 1.167 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.513ns (logic 0.595ns (39.323%) route 0.918ns (60.677%)) Logic Levels: 0 Clock Path Skew: -0.158ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.505ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.961 -0.347 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X10Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y70 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.248 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.918 1.166 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.502ns (logic 0.612ns (40.758%) route 0.890ns (59.242%)) Logic Levels: 0 Clock Path Skew: -0.122ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.470ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y70 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.264 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.890 1.153 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] SLICE_X7Y38 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.793 -0.470 u_Axi_CDC/rFifo/cpu_clk SLICE_X7Y38 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.495ns (logic 0.482ns (32.245%) route 1.013ns (67.755%)) Logic Levels: 0 Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X12Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y70 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.134 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O net (fo=1, routed) 1.013 1.147 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.487ns (logic 0.485ns (32.621%) route 1.002ns (67.379%)) Logic Levels: 0 Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.500ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X10Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y71 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.137 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 1.002 1.139 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] SLICE_X10Y33 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.763 -0.500 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y33 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.481ns (logic 0.480ns (32.416%) route 1.001ns (67.584%)) Logic Levels: 0 Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.508ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.961 -0.347 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X10Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y70 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.133 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 1.001 1.134 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.755 -0.508 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.478ns (logic 0.595ns (40.270%) route 0.883ns (59.730%)) Logic Levels: 0 Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X12Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y70 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.247 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.883 1.129 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.468ns (logic 0.491ns (33.444%) route 0.977ns (66.556%)) Logic Levels: 0 Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y70 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.143 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 0.977 1.120 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.459ns (logic 0.480ns (32.908%) route 0.979ns (67.092%)) Logic Levels: 0 Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.508ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y70 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O net (fo=1, routed) 0.979 1.110 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.755 -0.508 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.454ns (logic 0.595ns (40.919%) route 0.859ns (59.081%)) Logic Levels: 0 Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.508ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y70 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.247 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.859 1.106 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] SLICE_X8Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.755 -0.508 u_Axi_CDC/rFifo/cpu_clk SLICE_X8Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.446ns (logic 0.491ns (33.957%) route 0.955ns (66.043%)) Logic Levels: 0 Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X12Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y70 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.143 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 0.955 1.098 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.443ns (logic 0.491ns (34.023%) route 0.952ns (65.977%)) Logic Levels: 0 Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.961 -0.347 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X10Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y70 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.144 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 0.952 1.096 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.405ns (logic 0.485ns (34.519%) route 0.920ns (65.481%)) Logic Levels: 0 Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X12Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y70 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.137 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 0.920 1.057 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.367ns (logic 0.480ns (35.110%) route 0.887ns (64.890%)) Logic Levels: 0 Clock Path Skew: -0.122ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.470ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X10Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y71 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 0.887 1.019 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] SLICE_X7Y38 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.793 -0.470 u_Axi_CDC/rFifo/cpu_clk SLICE_X7Y38 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.365ns (logic 0.485ns (35.533%) route 0.880ns (64.467%)) Logic Levels: 0 Clock Path Skew: -0.158ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.505ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.961 -0.347 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X10Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y70 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.138 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.880 1.018 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] SLICE_X12Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.326ns (logic 0.485ns (36.570%) route 0.841ns (63.430%)) Logic Levels: 0 Clock Path Skew: -0.156ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.505ns Source Clock Delay (SCD): -0.349ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.959 -0.349 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X12Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y71 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.136 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 0.841 0.977 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] SLICE_X12Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_matmul_axi_slave/done_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.350ns (logic 0.175ns (12.959%) route 1.175ns (87.041%)) Logic Levels: 0 Clock Path Skew: -0.194ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.575ns Source Clock Delay (SCD): -0.381ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_matmul_axi_slave/sys_clk SLICE_X47Y90 FDRE r u_matmul_axi_slave/done_reg/C ------------------------------------------------------------------- ------------------- SLICE_X47Y90 FDRE (Prop_fdre_C_Q) 0.175 -0.206 r u_matmul_axi_slave/done_reg/Q net (fo=11, routed) 1.175 0.969 u_cpu/u_csr/interrupt[2] SLICE_X34Y54 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.687 -0.575 u_cpu/u_csr/cpu_clk SLICE_X34Y54 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C Slack: inf Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.308ns (logic 0.184ns (14.068%) route 1.124ns (85.932%)) Logic Levels: 0 Clock Path Skew: -0.196ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.578ns Source Clock Delay (SCD): -0.382ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/sys_clk SLICE_X60Y93 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y93 FDCE (Prop_fdce_C_Q) 0.184 -0.198 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/Q net (fo=1, routed) 1.124 0.926 u_cpu/u_csr/interrupt[3] SLICE_X39Y54 FDRE r u_cpu/u_csr/csr_estat_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.684 -0.578 u_cpu/u_csr/cpu_clk SLICE_X39Y54 FDRE r u_cpu/u_csr/csr_estat_reg[5]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.002ns (logic 0.482ns (48.095%) route 0.520ns (51.905%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.961 -0.347 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X16Y69 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y69 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.135 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O net (fo=1, routed) 0.520 0.655 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] SLICE_X13Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.695 -0.567 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.687ns (logic 0.204ns (29.701%) route 0.483ns (70.299%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.571ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.961 -0.347 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.204 -0.143 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.483 0.340 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0] SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.691 -0.571 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_cdma_matmul_bridge/seq_done_flag_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.701ns (logic 0.231ns (32.960%) route 0.470ns (67.040%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.618ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.922 -0.386 u_cdma_matmul_bridge/sys_clk SLICE_X58Y87 FDRE r u_cdma_matmul_bridge/seq_done_flag_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y87 FDRE (Prop_fdre_C_Q) 0.175 -0.211 r u_cdma_matmul_bridge/seq_done_flag_reg/Q net (fo=3, routed) 0.470 0.259 u_snix_axil_cdma_mux_8ch/cdma_matmul_seq_irq SLICE_X50Y78 LUT5 (Prop_lut5_I4_O) 0.056 0.315 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O net (fo=1, routed) 0.000 0.315 u_cpu/u_csr/interrupt[1] SLICE_X50Y78 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.644 -0.618 u_cpu/u_csr/cpu_clk SLICE_X50Y78 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.617ns (logic 0.184ns (29.806%) route 0.433ns (70.194%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.571ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.961 -0.347 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.184 -0.163 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=4, routed) 0.433 0.270 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.691 -0.571 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.605ns (logic 0.175ns (28.945%) route 0.430ns (71.055%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.568ns Source Clock Delay (SCD): -0.338ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/sys_clk SLICE_X13Y59 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y59 FDCE (Prop_fdce_C_Q) 0.175 -0.163 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.430 0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] SLICE_X9Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X9Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.607ns (logic 0.204ns (33.635%) route 0.403ns (66.365%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.571ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.961 -0.347 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.204 -0.143 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=2, routed) 0.403 0.259 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2] SLICE_X12Y63 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.691 -0.571 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X12Y63 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.537ns (logic 0.204ns (38.005%) route 0.333ns (61.995%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.571ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.961 -0.347 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.204 -0.143 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.333 0.190 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1] SLICE_X12Y63 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.691 -0.571 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X12Y63 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.480ns (logic 0.184ns (38.351%) route 0.296ns (61.649%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.569ns Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.965 -0.343 u_Axi_CDC/awFifo/sys_clk SLICE_X16Y65 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X16Y65 FDCE (Prop_fdce_C_Q) 0.184 -0.159 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.296 0.137 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2] SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.693 -0.569 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.476ns (logic 0.204ns (42.831%) route 0.272ns (57.169%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.569ns Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.965 -0.343 u_Axi_CDC/awFifo/sys_clk SLICE_X16Y65 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X16Y65 FDCE (Prop_fdce_C_Q) 0.204 -0.139 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.272 0.133 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1] SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.693 -0.569 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.469ns (logic 0.204ns (43.462%) route 0.265ns (56.538%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.571ns Source Clock Delay (SCD): -0.346ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.962 -0.346 u_Axi_CDC/arFifo/sys_clk SLICE_X20Y67 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y67 FDCE (Prop_fdce_C_Q) 0.204 -0.142 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.265 0.123 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.691 -0.571 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.462ns (logic 0.184ns (39.797%) route 0.278ns (60.203%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.571ns Source Clock Delay (SCD): -0.346ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.962 -0.346 u_Axi_CDC/arFifo/sys_clk SLICE_X20Y67 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y67 FDCE (Prop_fdce_C_Q) 0.184 -0.162 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.278 0.116 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.691 -0.571 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: cpu_clk To Clock: sys_clk Max Delay 162 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.136ns (logic 0.612ns (53.884%) route 0.524ns (46.116%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.576ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK SLICE_X22Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y60 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.270 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/O net (fo=1, routed) 0.524 0.794 u_Axi_CDC/awFifo/_zz_ram_port10[24] SLICE_X27Y64 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/awFifo/sys_clk SLICE_X27Y64 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.094ns (logic 0.612ns (55.964%) route 0.482ns (44.036%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.575ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X22Y62 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y62 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.268 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/O net (fo=1, routed) 0.482 0.749 u_Axi_CDC/arFifo/_zz_ram_port10__1[6] SLICE_X27Y62 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_Axi_CDC/arFifo/sys_clk SLICE_X27Y62 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Fast Process Corner) Data Path Delay: 1.056ns (logic 0.260ns (24.623%) route 0.796ns (75.377%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.256ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.569ns Source Clock Delay (SCD): -0.313ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.995 -0.313 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.204 -0.109 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.272 0.163 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.056 0.219 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.524 0.743 u_Axi_CDC/awFifo/bufferCC_12/p_0_in SLICE_X8Y60 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C Slack: inf Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Fast Process Corner) Data Path Delay: 1.056ns (logic 0.260ns (24.623%) route 0.796ns (75.377%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.256ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.569ns Source Clock Delay (SCD): -0.313ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.995 -0.313 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.204 -0.109 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.272 0.163 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.056 0.219 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.524 0.743 u_Axi_CDC/awFifo/bufferCC_12/p_0_in SLICE_X8Y60 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.084ns (logic 0.482ns (44.468%) route 0.602ns (55.532%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.576ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK SLICE_X22Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y60 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.140 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB_D1/O net (fo=1, routed) 0.602 0.742 u_Axi_CDC/awFifo/_zz_ram_port10[27] SLICE_X27Y64 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/awFifo/sys_clk SLICE_X27Y64 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.072ns (logic 0.595ns (55.524%) route 0.477ns (44.476%)) Logic Levels: 0 Clock Path Skew: -0.236ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.578ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK SLICE_X22Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y60 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.253 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/O net (fo=1, routed) 0.477 0.729 u_Axi_CDC/awFifo/_zz_ram_port10[25] SLICE_X28Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.684 -0.578 u_Axi_CDC/awFifo/sys_clk SLICE_X28Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.072ns (logic 0.595ns (55.482%) route 0.477ns (44.518%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.576ns Source Clock Delay (SCD): -0.345ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X22Y64 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y64 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.250 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/O net (fo=1, routed) 0.477 0.727 u_Axi_CDC/arFifo/_zz_ram_port10__1[19] SLICE_X27Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/arFifo/sys_clk SLICE_X27Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.023ns (logic 0.485ns (47.408%) route 0.538ns (52.592%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.541ns Source Clock Delay (SCD): -0.308ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.000 -0.308 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X6Y55 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y55 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.177 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 0.538 0.715 u_Axi_CDC/wFifo/_zz_ram_port10__0[4] SLICE_X5Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.721 -0.541 u_Axi_CDC/wFifo/sys_clk SLICE_X5Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.058ns (logic 0.612ns (57.828%) route 0.446ns (42.172%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.576ns Source Clock Delay (SCD): -0.345ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X22Y63 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y63 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.267 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/O net (fo=1, routed) 0.446 0.713 u_Axi_CDC/awFifo/_zz_ram_port10[18] SLICE_X27Y64 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/awFifo/sys_clk SLICE_X27Y64 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.044ns (logic 0.612ns (58.639%) route 0.432ns (41.361%)) Logic Levels: 0 Clock Path Skew: -0.236ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.575ns Source Clock Delay (SCD): -0.339ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X16Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y60 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.273 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 0.432 0.704 u_Axi_CDC/awFifo/_zz_ram_port10[0] SLICE_X25Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_Axi_CDC/awFifo/sys_clk SLICE_X25Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.044ns (logic 0.480ns (45.980%) route 0.564ns (54.020%)) Logic Levels: 0 Clock Path Skew: -0.236ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.578ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK SLICE_X22Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y60 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.138 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC_D1/O net (fo=1, routed) 0.564 0.702 u_Axi_CDC/awFifo/_zz_ram_port10[29] SLICE_X29Y64 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.684 -0.578 u_Axi_CDC/awFifo/sys_clk SLICE_X29Y64 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.024ns (logic 0.480ns (46.872%) route 0.544ns (53.128%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.577ns Source Clock Delay (SCD): -0.345ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X22Y64 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y64 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.135 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/O net (fo=1, routed) 0.544 0.679 u_Axi_CDC/arFifo/_zz_ram_port10__1[23] SLICE_X22Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.685 -0.577 u_Axi_CDC/arFifo/sys_clk SLICE_X22Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.020ns (logic 0.491ns (48.117%) route 0.529ns (51.883%)) Logic Levels: 0 Clock Path Skew: -0.236ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.578ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK SLICE_X22Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y60 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.149 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB/O net (fo=1, routed) 0.529 0.678 u_Axi_CDC/awFifo/_zz_ram_port10[26] SLICE_X28Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.684 -0.578 u_Axi_CDC/awFifo/sys_clk SLICE_X28Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[26]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.017ns (logic 0.482ns (47.372%) route 0.535ns (52.628%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.574ns Source Clock Delay (SCD): -0.340ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.968 -0.340 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X20Y61 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y61 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.142 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/O net (fo=1, routed) 0.535 0.677 u_Axi_CDC/arFifo/_zz_ram_port10__1[3] SLICE_X27Y61 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.688 -0.574 u_Axi_CDC/arFifo/sys_clk SLICE_X27Y61 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.016ns (logic 0.485ns (47.750%) route 0.531ns (52.250%)) Logic Levels: 0 Clock Path Skew: -0.236ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.578ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK SLICE_X22Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y60 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.143 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/O net (fo=1, routed) 0.531 0.674 u_Axi_CDC/awFifo/_zz_ram_port10[28] SLICE_X28Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.684 -0.578 u_Axi_CDC/awFifo/sys_clk SLICE_X28Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.007ns (logic 0.482ns (47.841%) route 0.525ns (52.159%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.578ns Source Clock Delay (SCD): -0.345ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X22Y64 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y64 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.137 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/O net (fo=1, routed) 0.525 0.662 u_Axi_CDC/arFifo/_zz_ram_port10__1[21] SLICE_X25Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.684 -0.578 u_Axi_CDC/arFifo/sys_clk SLICE_X25Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.995ns (logic 0.595ns (59.818%) route 0.400ns (40.182%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.576ns Source Clock Delay (SCD): -0.345ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X22Y63 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y63 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.250 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/O net (fo=1, routed) 0.400 0.650 u_Axi_CDC/awFifo/_zz_ram_port10[19] SLICE_X27Y64 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/awFifo/sys_clk SLICE_X27Y64 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.952ns (logic 0.612ns (64.274%) route 0.340ns (35.726%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.541ns Source Clock Delay (SCD): -0.308ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.000 -0.308 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X6Y55 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y55 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.304 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 0.340 0.644 u_Axi_CDC/wFifo/_zz_ram_port10__0[0] SLICE_X6Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.721 -0.541 u_Axi_CDC/wFifo/sys_clk SLICE_X6Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.968ns (logic 0.595ns (61.440%) route 0.373ns (38.560%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.574ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X22Y61 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y61 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.253 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/O net (fo=1, routed) 0.373 0.626 u_Axi_CDC/arFifo/_zz_ram_port10__1[13] SLICE_X27Y61 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.688 -0.574 u_Axi_CDC/arFifo/sys_clk SLICE_X27Y61 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.960ns (logic 0.482ns (50.211%) route 0.478ns (49.789%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.575ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X22Y62 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y62 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.138 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/O net (fo=1, routed) 0.478 0.616 u_Axi_CDC/arFifo/_zz_ram_port10__1[9] SLICE_X27Y62 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_Axi_CDC/arFifo/sys_clk SLICE_X27Y62 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.957ns (logic 0.480ns (50.162%) route 0.477ns (49.838%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.575ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X22Y62 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y62 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.136 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/O net (fo=1, routed) 0.477 0.613 u_Axi_CDC/arFifo/_zz_ram_port10__1[11] SLICE_X27Y62 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_Axi_CDC/arFifo/sys_clk SLICE_X27Y62 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.956ns (logic 0.480ns (50.226%) route 0.476ns (49.774%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.578ns Source Clock Delay (SCD): -0.345ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X22Y63 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y63 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.135 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC_D1/O net (fo=1, routed) 0.476 0.610 u_Axi_CDC/awFifo/_zz_ram_port10[23] SLICE_X28Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.684 -0.578 u_Axi_CDC/awFifo/sys_clk SLICE_X28Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.945ns (logic 0.485ns (51.316%) route 0.460ns (48.684%)) Logic Levels: 0 Clock Path Skew: -0.236ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.578ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X22Y61 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y61 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.143 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/O net (fo=1, routed) 0.460 0.603 u_Axi_CDC/arFifo/_zz_ram_port10__1[16] SLICE_X29Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.684 -0.578 u_Axi_CDC/arFifo/sys_clk SLICE_X29Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.947ns (logic 0.612ns (64.597%) route 0.335ns (35.403%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.576ns Source Clock Delay (SCD): -0.345ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X22Y64 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y64 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.267 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/O net (fo=1, routed) 0.335 0.602 u_Axi_CDC/arFifo/_zz_ram_port10__1[18] SLICE_X25Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/arFifo/sys_clk SLICE_X25Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.938ns (logic 0.612ns (65.223%) route 0.326ns (34.777%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.578ns Source Clock Delay (SCD): -0.346ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X22Y65 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y65 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.266 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/O net (fo=1, routed) 0.326 0.592 u_Axi_CDC/arFifo/_zz_ram_port10__1[24] SLICE_X25Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.684 -0.578 u_Axi_CDC/arFifo/sys_clk SLICE_X25Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.891ns (logic 0.612ns (68.680%) route 0.279ns (31.320%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.541ns Source Clock Delay (SCD): -0.309ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.999 -0.309 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X6Y57 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y57 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.303 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.279 0.582 u_Axi_CDC/wFifo/_zz_ram_port10__0[24] SLICE_X6Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.721 -0.541 u_Axi_CDC/wFifo/sys_clk SLICE_X6Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.925ns (logic 0.595ns (64.325%) route 0.330ns (35.675%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.576ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X22Y62 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y62 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.251 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 0.330 0.581 u_Axi_CDC/arFifo/_zz_ram_port10__1[7] SLICE_X25Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/arFifo/sys_clk SLICE_X25Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.882ns (logic 0.485ns (55.003%) route 0.397ns (44.997%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.541ns Source Clock Delay (SCD): -0.308ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.000 -0.308 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X6Y56 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y56 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.177 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 0.397 0.574 u_Axi_CDC/wFifo/_zz_ram_port10__0[10] SLICE_X5Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.721 -0.541 u_Axi_CDC/wFifo/sys_clk SLICE_X5Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.881ns (logic 0.612ns (69.470%) route 0.269ns (30.530%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.541ns Source Clock Delay (SCD): -0.308ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.000 -0.308 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X6Y54 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y54 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.304 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 0.269 0.573 u_Axi_CDC/wFifo/_zz_ram_port10__0[18] SLICE_X4Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.721 -0.541 u_Axi_CDC/wFifo/sys_clk SLICE_X4Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.916ns (logic 0.491ns (53.582%) route 0.425ns (46.418%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.575ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X22Y62 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y62 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.147 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/O net (fo=1, routed) 0.425 0.572 u_Axi_CDC/arFifo/_zz_ram_port10__1[8] SLICE_X27Y62 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_Axi_CDC/arFifo/sys_clk SLICE_X27Y62 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.879ns (logic 0.595ns (67.701%) route 0.284ns (32.299%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.541ns Source Clock Delay (SCD): -0.308ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.000 -0.308 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X6Y55 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y55 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.287 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.284 0.571 u_Axi_CDC/wFifo/_zz_ram_port10__0[1] SLICE_X5Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.721 -0.541 u_Axi_CDC/wFifo/sys_clk SLICE_X5Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.874ns (logic 0.595ns (68.077%) route 0.279ns (31.923%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.541ns Source Clock Delay (SCD): -0.308ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.000 -0.308 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X6Y54 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y54 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.287 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.279 0.566 u_Axi_CDC/wFifo/_zz_ram_port10__0[19] SLICE_X5Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.721 -0.541 u_Axi_CDC/wFifo/sys_clk SLICE_X5Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.904ns (logic 0.612ns (67.704%) route 0.292ns (32.296%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.574ns Source Clock Delay (SCD): -0.340ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.968 -0.340 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X20Y61 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y61 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.272 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 0.292 0.564 u_Axi_CDC/arFifo/_zz_ram_port10__1[0] SLICE_X24Y61 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.688 -0.574 u_Axi_CDC/arFifo/sys_clk SLICE_X24Y61 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.895ns (logic 0.612ns (68.397%) route 0.283ns (31.603%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.336ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.972 -0.336 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X8Y54 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X8Y54 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.276 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.283 0.559 u_Axi_CDC/wFifo/_zz_ram_port10__0[12] SLICE_X9Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.695 -0.567 u_Axi_CDC/wFifo/sys_clk SLICE_X9Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.895ns (logic 0.480ns (53.640%) route 0.415ns (46.360%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.576ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X22Y61 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y61 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.138 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/O net (fo=1, routed) 0.415 0.553 u_Axi_CDC/arFifo/_zz_ram_port10__1[17] SLICE_X27Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/arFifo/sys_clk SLICE_X27Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[17]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.893ns (logic 0.491ns (54.979%) route 0.402ns (45.021%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.578ns Source Clock Delay (SCD): -0.345ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X22Y64 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y64 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.146 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/O net (fo=1, routed) 0.402 0.548 u_Axi_CDC/arFifo/_zz_ram_port10__1[20] SLICE_X25Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.684 -0.578 u_Axi_CDC/arFifo/sys_clk SLICE_X25Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[20]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.890ns (logic 0.595ns (66.872%) route 0.295ns (33.128%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.577ns Source Clock Delay (SCD): -0.346ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X22Y65 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y65 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.249 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/O net (fo=1, routed) 0.295 0.544 u_Axi_CDC/arFifo/_zz_ram_port10__1[25] SLICE_X22Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.685 -0.577 u_Axi_CDC/arFifo/sys_clk SLICE_X22Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.883ns (logic 0.595ns (67.377%) route 0.288ns (32.623%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.574ns Source Clock Delay (SCD): -0.340ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.968 -0.340 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X20Y61 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y61 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.255 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/O net (fo=1, routed) 0.288 0.543 u_Axi_CDC/arFifo/_zz_ram_port10__1[1] SLICE_X24Y61 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.688 -0.574 u_Axi_CDC/arFifo/sys_clk SLICE_X24Y61 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.895ns (logic 0.595ns (66.446%) route 0.300ns (33.554%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.582ns Source Clock Delay (SCD): -0.355ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.953 -0.355 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X36Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.240 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/O net (fo=1, routed) 0.300 0.540 u_Axi_CDC/arFifo/_zz_ram_port10__1[31] SLICE_X33Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.680 -0.582 u_Axi_CDC/arFifo/sys_clk SLICE_X33Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.897ns (logic 0.491ns (54.735%) route 0.406ns (45.265%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.587ns Source Clock Delay (SCD): -0.360ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.948 -0.360 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X36Y72 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y72 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.131 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/O net (fo=1, routed) 0.406 0.537 u_Axi_CDC/awFifo/_zz_ram_port10[32] SLICE_X37Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.675 -0.587 u_Axi_CDC/awFifo/sys_clk SLICE_X37Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.842ns (logic 0.480ns (57.028%) route 0.362ns (42.972%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.541ns Source Clock Delay (SCD): -0.309ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.999 -0.309 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X6Y57 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y57 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.171 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 0.362 0.533 u_Axi_CDC/wFifo/_zz_ram_port10__0[29] SLICE_X6Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.721 -0.541 u_Axi_CDC/wFifo/sys_clk SLICE_X6Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.840ns (logic 0.482ns (57.382%) route 0.358ns (42.618%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.541ns Source Clock Delay (SCD): -0.308ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.000 -0.308 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X6Y55 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y55 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.174 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB_D1/O net (fo=1, routed) 0.358 0.532 u_Axi_CDC/wFifo/_zz_ram_port10__0[3] SLICE_X5Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.721 -0.541 u_Axi_CDC/wFifo/sys_clk SLICE_X5Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.866ns (logic 0.595ns (68.729%) route 0.271ns (31.271%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.336ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.972 -0.336 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X8Y54 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X8Y54 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.259 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.271 0.530 u_Axi_CDC/wFifo/_zz_ram_port10__0[13] SLICE_X9Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.695 -0.567 u_Axi_CDC/wFifo/sys_clk SLICE_X9Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.886ns (logic 0.595ns (67.157%) route 0.291ns (32.843%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.587ns Source Clock Delay (SCD): -0.358ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.950 -0.358 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK SLICE_X36Y70 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y70 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.237 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/O net (fo=1, routed) 0.291 0.528 u_Axi_CDC/awFifo/_zz_ram_port10[37] SLICE_X38Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.675 -0.587 u_Axi_CDC/awFifo/sys_clk SLICE_X38Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[47]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.875ns (logic 0.480ns (54.862%) route 0.395ns (45.138%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.578ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X22Y66 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y66 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.133 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/O net (fo=1, routed) 0.395 0.528 u_Axi_CDC/arFifo/_zz_ram_port10__1[47] SLICE_X25Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[47]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.684 -0.578 u_Axi_CDC/arFifo/sys_clk SLICE_X25Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[47]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.873ns (logic 0.612ns (70.069%) route 0.261ns (29.931%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.575ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X22Y66 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y66 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.265 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/O net (fo=1, routed) 0.261 0.526 u_Axi_CDC/arFifo/_zz_ram_port10__1[42] SLICE_X23Y66 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_Axi_CDC/arFifo/sys_clk SLICE_X23Y66 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.852ns (logic 0.595ns (69.797%) route 0.257ns (30.203%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.568ns Source Clock Delay (SCD): -0.336ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.972 -0.336 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X10Y56 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y56 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.259 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.257 0.516 u_Axi_CDC/wFifo/_zz_ram_port10__0[31] SLICE_X11Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.694 -0.568 u_Axi_CDC/wFifo/sys_clk SLICE_X11Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.854ns (logic 0.595ns (69.686%) route 0.259ns (30.314%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.570ns Source Clock Delay (SCD): -0.339ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X20Y59 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y59 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.256 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/O net (fo=1, routed) 0.259 0.515 u_Axi_CDC/awFifo/_zz_ram_port10[13] SLICE_X21Y59 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.692 -0.570 u_Axi_CDC/awFifo/sys_clk SLICE_X21Y59 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.853ns (logic 0.595ns (69.735%) route 0.258ns (30.265%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.570ns Source Clock Delay (SCD): -0.339ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X16Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y60 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.256 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/O net (fo=1, routed) 0.258 0.514 u_Axi_CDC/awFifo/_zz_ram_port10[1] SLICE_X16Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.692 -0.570 u_Axi_CDC/awFifo/sys_clk SLICE_X16Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.874ns (logic 0.612ns (70.054%) route 0.262ns (29.946%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.587ns Source Clock Delay (SCD): -0.360ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.948 -0.360 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X36Y72 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y72 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.252 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/O net (fo=1, routed) 0.262 0.513 u_Axi_CDC/awFifo/_zz_ram_port10[30] SLICE_X37Y72 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.675 -0.587 u_Axi_CDC/awFifo/sys_clk SLICE_X37Y72 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: clkfbout_clk_pll To Clock: Max Delay 1 Endpoint Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT (clock source 'clkfbout_clk_pll' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Path Group: (none) Path Type: Max at Fast Process Corner Data Path Delay: 1.519ns (logic 0.029ns (1.909%) route 1.490ns (98.091%)) Logic Levels: 1 (BUFG=1) Clock Uncertainty: 0.169ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.075ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clkfbout_clk_pll fall edge) 10.000 10.000 f K21 0.000 10.000 f clk (IN) net (fo=0) 0.000 10.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 10.419 f pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 10.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.847 8.053 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT net (fo=1, routed) 0.611 8.663 pll_clk.u_clk_pll/inst/clkfbout_clk_pll BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.029 8.692 f pll_clk.u_clk_pll/inst/clkf_buf/O net (fo=1, routed) 0.880 9.572 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: Max Delay 41 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_axi_dvi/DVI_SQU_R_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 14.957ns (logic 6.235ns (41.684%) route 8.722ns (58.316%)) Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.005 -2.337 u_axi_dvi/sys_clk SLICE_X6Y74 FDRE r u_axi_dvi/DVI_SQU_R_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y74 FDRE (Prop_fdre_C_Q) 0.518 -1.819 r u_axi_dvi/DVI_SQU_R_reg[16]/Q net (fo=3, routed) 1.223 -0.595 u_axi_dvi/p_0_in[0] SLICE_X7Y75 LUT2 (Prop_lut2_I1_O) 0.124 -0.471 r u_axi_dvi/video_red_OBUF[2]_inst_i_268/O net (fo=1, routed) 0.000 -0.471 u_axi_dvi/video_red_OBUF[2]_inst_i_268_n_0 SLICE_X7Y75 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 0.061 r u_axi_dvi/video_red_OBUF[2]_inst_i_230/CO[3] net (fo=1, routed) 0.000 0.061 u_axi_dvi/video_red_OBUF[2]_inst_i_230_n_0 SLICE_X7Y76 CARRY4 (Prop_carry4_CI_O[1]) 0.334 0.395 r u_axi_dvi/video_red_OBUF[2]_inst_i_190/O[1] net (fo=1, routed) 0.846 1.240 u_axi_dvi/video_red_OBUF[2]_inst_i_190_n_6 SLICE_X6Y76 LUT2 (Prop_lut2_I1_O) 0.303 1.543 r u_axi_dvi/video_red_OBUF[2]_inst_i_124/O net (fo=1, routed) 0.000 1.543 u_axi_dvi/video_red_OBUF[2]_inst_i_124_n_0 SLICE_X6Y76 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 2.076 r u_axi_dvi/video_red_OBUF[2]_inst_i_61/CO[3] net (fo=1, routed) 0.000 2.076 u_axi_dvi/video_red_OBUF[2]_inst_i_61_n_0 SLICE_X6Y77 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 2.193 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3] net (fo=1, routed) 0.000 2.193 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0 SLICE_X6Y78 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 2.310 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3] net (fo=1, routed) 1.499 3.810 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0 SLICE_X8Y75 LUT5 (Prop_lut5_I3_O) 0.124 3.934 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 5.154 9.088 video_red_OBUF[0] K23 OBUF (Prop_obuf_I_O) 3.533 12.620 r video_red_OBUF[0]_inst/O net (fo=0) 0.000 12.620 video_red[0] K23 r video_red[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/DVI_SQU_R_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 14.866ns (logic 6.289ns (42.301%) route 8.578ns (57.699%)) Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.005 -2.337 u_axi_dvi/sys_clk SLICE_X6Y74 FDRE r u_axi_dvi/DVI_SQU_R_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y74 FDRE (Prop_fdre_C_Q) 0.518 -1.819 r u_axi_dvi/DVI_SQU_R_reg[16]/Q net (fo=3, routed) 1.223 -0.595 u_axi_dvi/p_0_in[0] SLICE_X7Y75 LUT2 (Prop_lut2_I1_O) 0.124 -0.471 r u_axi_dvi/video_red_OBUF[2]_inst_i_268/O net (fo=1, routed) 0.000 -0.471 u_axi_dvi/video_red_OBUF[2]_inst_i_268_n_0 SLICE_X7Y75 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 0.061 r u_axi_dvi/video_red_OBUF[2]_inst_i_230/CO[3] net (fo=1, routed) 0.000 0.061 u_axi_dvi/video_red_OBUF[2]_inst_i_230_n_0 SLICE_X7Y76 CARRY4 (Prop_carry4_CI_O[1]) 0.334 0.395 r u_axi_dvi/video_red_OBUF[2]_inst_i_190/O[1] net (fo=1, routed) 0.846 1.240 u_axi_dvi/video_red_OBUF[2]_inst_i_190_n_6 SLICE_X6Y76 LUT2 (Prop_lut2_I1_O) 0.303 1.543 r u_axi_dvi/video_red_OBUF[2]_inst_i_124/O net (fo=1, routed) 0.000 1.543 u_axi_dvi/video_red_OBUF[2]_inst_i_124_n_0 SLICE_X6Y76 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 2.076 r u_axi_dvi/video_red_OBUF[2]_inst_i_61/CO[3] net (fo=1, routed) 0.000 2.076 u_axi_dvi/video_red_OBUF[2]_inst_i_61_n_0 SLICE_X6Y77 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 2.193 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3] net (fo=1, routed) 0.000 2.193 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0 SLICE_X6Y78 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 2.310 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3] net (fo=1, routed) 1.499 3.810 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0 SLICE_X8Y75 LUT5 (Prop_lut5_I3_O) 0.124 3.934 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 5.010 8.943 video_red_OBUF[0] E26 OBUF (Prop_obuf_I_O) 3.587 12.530 r video_red_OBUF[2]_inst/O net (fo=0) 0.000 12.530 video_red[2] E26 r video_red[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/DVI_SQU_R_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 14.843ns (logic 6.262ns (42.189%) route 8.581ns (57.811%)) Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.005 -2.337 u_axi_dvi/sys_clk SLICE_X6Y74 FDRE r u_axi_dvi/DVI_SQU_R_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y74 FDRE (Prop_fdre_C_Q) 0.518 -1.819 r u_axi_dvi/DVI_SQU_R_reg[16]/Q net (fo=3, routed) 1.223 -0.595 u_axi_dvi/p_0_in[0] SLICE_X7Y75 LUT2 (Prop_lut2_I1_O) 0.124 -0.471 r u_axi_dvi/video_red_OBUF[2]_inst_i_268/O net (fo=1, routed) 0.000 -0.471 u_axi_dvi/video_red_OBUF[2]_inst_i_268_n_0 SLICE_X7Y75 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 0.061 r u_axi_dvi/video_red_OBUF[2]_inst_i_230/CO[3] net (fo=1, routed) 0.000 0.061 u_axi_dvi/video_red_OBUF[2]_inst_i_230_n_0 SLICE_X7Y76 CARRY4 (Prop_carry4_CI_O[1]) 0.334 0.395 r u_axi_dvi/video_red_OBUF[2]_inst_i_190/O[1] net (fo=1, routed) 0.846 1.240 u_axi_dvi/video_red_OBUF[2]_inst_i_190_n_6 SLICE_X6Y76 LUT2 (Prop_lut2_I1_O) 0.303 1.543 r u_axi_dvi/video_red_OBUF[2]_inst_i_124/O net (fo=1, routed) 0.000 1.543 u_axi_dvi/video_red_OBUF[2]_inst_i_124_n_0 SLICE_X6Y76 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 2.076 r u_axi_dvi/video_red_OBUF[2]_inst_i_61/CO[3] net (fo=1, routed) 0.000 2.076 u_axi_dvi/video_red_OBUF[2]_inst_i_61_n_0 SLICE_X6Y77 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 2.193 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3] net (fo=1, routed) 0.000 2.193 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0 SLICE_X6Y78 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 2.310 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3] net (fo=1, routed) 1.499 3.810 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0 SLICE_X8Y75 LUT5 (Prop_lut5_I3_O) 0.124 3.934 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 5.013 8.947 video_red_OBUF[0] F24 OBUF (Prop_obuf_I_O) 3.560 12.507 r video_red_OBUF[1]_inst/O net (fo=0) 0.000 12.507 video_red[1] F24 r video_red[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 (clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_clk (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.589ns (logic 3.629ns (42.252%) route 4.960ns (57.748%)) Logic Levels: 2 (BUFG=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk fall edge) 10.000 10.000 f K21 0.000 10.000 f clk (IN) net (fo=0) 0.000 10.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 11.463 f pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 12.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 3.725 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 5.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 5.658 f pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 3.123 8.781 video_clk_OBUF H22 OBUF (Prop_obuf_I_O) 3.533 12.314 f video_clk_OBUF_inst/O net (fo=0) 0.000 12.314 video_clk H22 f video_clk (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 12.981ns (logic 4.012ns (30.910%) route 8.968ns (69.090%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.024 -2.318 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y61 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y61 FDCE (Prop_fdce_C_Q) 0.456 -1.862 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q net (fo=1, routed) 8.968 7.107 dpy0_OBUF[6] B17 OBUF (Prop_obuf_I_O) 3.556 10.663 r dpy0_OBUF[6]_inst/O net (fo=0) 0.000 10.663 dpy0[6] B17 r dpy0[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_TX (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 12.570ns (logic 4.124ns (32.813%) route 8.445ns (67.187%)) Logic Levels: 2 (LUT3=1 OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.937 -2.405 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X30Y59 FDRE r u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y59 FDRE (Prop_fdre_C_Q) 0.456 -1.949 f u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/Q net (fo=13, routed) 1.267 -0.681 u_axi_uart_controller/uart0/regs/transmitter/tf_pop_reg_0[1] SLICE_X34Y56 LUT3 (Prop_lut3_I1_O) 0.124 -0.557 f u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O net (fo=1, routed) 7.178 6.621 UART_TX_IOBUF_inst/T H18 OBUFT (TriStatE_obuft_T_O) 3.544 10.165 r UART_TX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 10.165 UART_TX H18 r UART_TX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 12.027ns (logic 3.993ns (33.199%) route 8.034ns (66.801%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.025 -2.317 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y59 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y59 FDCE (Prop_fdce_C_Q) 0.456 -1.861 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q net (fo=1, routed) 8.034 6.174 dpy1_OBUF[6] F15 OBUF (Prop_obuf_I_O) 3.537 9.711 r dpy1_OBUF[6]_inst/O net (fo=0) 0.000 9.711 dpy1[6] F15 r dpy1[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[8]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_de (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.795ns (logic 4.495ns (38.108%) route 7.300ns (61.892%)) Logic Levels: 3 (LUT5=1 LUT6=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.008 -2.334 u_axi_dvi/sys_clk SLICE_X5Y77 FDRE r u_axi_dvi/hdata_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y77 FDRE (Prop_fdre_C_Q) 0.456 -1.878 f u_axi_dvi/hdata_reg[8]/Q net (fo=12, routed) 1.185 -0.693 u_axi_dvi/hdata_reg_n_0_[8] SLICE_X5Y79 LUT5 (Prop_lut5_I1_O) 0.152 -0.541 f u_axi_dvi/video_de_OBUF_inst_i_3/O net (fo=1, routed) 1.182 0.641 u_axi_dvi/video_de_OBUF_inst_i_3_n_0 SLICE_X8Y79 LUT6 (Prop_lut6_I5_O) 0.326 0.967 r u_axi_dvi/video_de_OBUF_inst_i_1/O net (fo=1, routed) 4.933 5.900 video_de_OBUF G24 OBUF (Prop_obuf_I_O) 3.561 9.461 r video_de_OBUF_inst/O net (fo=0) 0.000 9.461 video_de G24 r video_de (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.686ns (logic 4.001ns (34.240%) route 7.685ns (65.760%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.024 -2.318 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y61 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y61 FDCE (Prop_fdce_C_Q) 0.456 -1.862 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q net (fo=1, routed) 7.685 5.823 dpy0_OBUF[1] D19 OBUF (Prop_obuf_I_O) 3.545 9.368 r dpy0_OBUF[1]_inst/O net (fo=0) 0.000 9.368 dpy0[1] D19 r dpy0[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[8]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[8] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.627ns (logic 4.210ns (36.209%) route 7.417ns (63.791%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.019 -2.323 u_confreg/sys_clk SLICE_X2Y83 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y83 FDRE (Prop_fdre_C_Q) 0.478 -1.845 r u_confreg/led_data_reg[8]_lopt_replica/Q net (fo=1, routed) 7.417 5.572 lopt_14 C23 OBUF (Prop_obuf_I_O) 3.732 9.304 r leds_OBUF[8]_inst/O net (fo=0) 0.000 9.304 leds[8] C23 r leds[8] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.384ns (logic 3.970ns (34.876%) route 7.414ns (65.124%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.025 -2.317 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y60 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y60 FDCE (Prop_fdce_C_Q) 0.456 -1.861 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q net (fo=1, routed) 7.414 5.553 dpy1_OBUF[3] F17 OBUF (Prop_obuf_I_O) 3.514 9.067 r dpy1_OBUF[3]_inst/O net (fo=0) 0.000 9.067 dpy1[3] F17 r dpy1[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.286ns (logic 4.001ns (35.448%) route 7.285ns (64.551%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.025 -2.317 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y60 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y60 FDCE (Prop_fdce_C_Q) 0.456 -1.861 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q net (fo=1, routed) 7.285 5.425 dpy0_OBUF[7] C17 OBUF (Prop_obuf_I_O) 3.545 8.969 r dpy0_OBUF[7]_inst/O net (fo=0) 0.000 8.969 dpy0[7] C17 r dpy0[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.049ns (logic 3.990ns (36.111%) route 7.059ns (63.889%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.025 -2.317 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y60 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y60 FDCE (Prop_fdce_C_Q) 0.456 -1.861 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q net (fo=1, routed) 7.059 5.198 dpy1_OBUF[5] G16 OBUF (Prop_obuf_I_O) 3.534 8.732 r dpy1_OBUF[5]_inst/O net (fo=0) 0.000 8.732 dpy1[5] G16 r dpy1[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_vsync (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.939ns (logic 4.379ns (40.026%) route 6.561ns (59.974%)) Logic Levels: 4 (LUT2=1 LUT4=1 LUT6=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.932 -2.410 u_axi_dvi/sys_clk SLICE_X11Y72 FDRE r u_axi_dvi/vdata_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X11Y72 FDRE (Prop_fdre_C_Q) 0.456 -1.954 r u_axi_dvi/vdata_reg[3]/Q net (fo=11, routed) 0.751 -1.203 u_axi_dvi/vdata_reg_n_0_[3] SLICE_X13Y72 LUT2 (Prop_lut2_I0_O) 0.124 -1.079 f u_axi_dvi/vdata[11]_i_4/O net (fo=3, routed) 0.975 -0.104 u_axi_dvi/vdata[11]_i_4_n_0 SLICE_X10Y73 LUT6 (Prop_lut6_I5_O) 0.124 0.020 r u_axi_dvi/video_vsync_OBUF_inst_i_2/O net (fo=1, routed) 0.893 0.913 u_axi_dvi/video_vsync_OBUF_inst_i_2_n_0 SLICE_X8Y72 LUT4 (Prop_lut4_I0_O) 0.124 1.037 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O net (fo=1, routed) 3.942 4.979 video_vsync_OBUF H24 OBUF (Prop_obuf_I_O) 3.551 8.530 r video_vsync_OBUF_inst/O net (fo=0) 0.000 8.530 video_vsync H24 r video_vsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.812ns (logic 4.029ns (37.266%) route 6.783ns (62.734%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.024 -2.318 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y61 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y61 FDCE (Prop_fdce_C_Q) 0.456 -1.862 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q net (fo=1, routed) 6.783 4.921 dpy0_OBUF[3] A19 OBUF (Prop_obuf_I_O) 3.573 8.494 r dpy0_OBUF[3]_inst/O net (fo=0) 0.000 8.494 dpy0[3] A19 r dpy0[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.767ns (logic 3.995ns (37.107%) route 6.772ns (62.893%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.024 -2.318 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y61 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y61 FDCE (Prop_fdce_C_Q) 0.456 -1.862 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q net (fo=1, routed) 6.772 4.910 dpy0_OBUF[4] E18 OBUF (Prop_obuf_I_O) 3.539 8.449 r dpy0_OBUF[4]_inst/O net (fo=0) 0.000 8.449 dpy0[4] E18 r dpy0[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.659ns (logic 3.998ns (37.506%) route 6.661ns (62.494%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.025 -2.317 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y59 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y59 FDCE (Prop_fdce_C_Q) 0.456 -1.861 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q net (fo=1, routed) 6.661 4.800 dpy1_OBUF[4] E16 OBUF (Prop_obuf_I_O) 3.542 8.342 r dpy1_OBUF[4]_inst/O net (fo=0) 0.000 8.342 dpy1[4] E16 r dpy1[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.518ns (logic 4.002ns (38.049%) route 6.516ns (61.951%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.024 -2.318 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y61 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y61 FDCE (Prop_fdce_C_Q) 0.456 -1.862 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q net (fo=1, routed) 6.516 4.654 dpy0_OBUF[5] C19 OBUF (Prop_obuf_I_O) 3.546 8.200 r dpy0_OBUF[5]_inst/O net (fo=0) 0.000 8.200 dpy0[5] C19 r dpy0[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[15]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[15] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.409ns (logic 4.081ns (39.205%) route 6.328ns (60.795%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.019 -2.323 u_confreg/sys_clk SLICE_X2Y83 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y83 FDRE (Prop_fdre_C_Q) 0.518 -1.805 r u_confreg/led_data_reg[15]_lopt_replica/Q net (fo=1, routed) 6.328 4.524 lopt_6 B20 OBUF (Prop_obuf_I_O) 3.563 8.086 r leds_OBUF[15]_inst/O net (fo=0) 0.000 8.086 leds[15] B20 r leds[15] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_RX (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.365ns (logic 4.100ns (39.560%) route 6.264ns (60.440%)) Logic Levels: 2 (LUT2=1 OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.937 -2.405 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X30Y59 FDRE r u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y59 FDRE (Prop_fdre_C_Q) 0.456 -1.949 r u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/Q net (fo=2, routed) 0.956 -0.992 u_axi_uart_controller/uart0/regs/sclk_por SLICE_X25Y59 LUT2 (Prop_lut2_I1_O) 0.124 -0.868 r u_axi_uart_controller/uart0/regs/UART_RX_IOBUF_inst_i_1/O net (fo=1, routed) 5.308 4.440 UART_RX_IOBUF_inst/I J20 OBUFT (Prop_obuft_I_O) 3.520 7.960 r UART_RX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 7.960 UART_RX J20 r UART_RX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[4]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.248ns (logic 4.018ns (39.211%) route 6.229ns (60.789%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.018 -2.324 u_confreg/sys_clk SLICE_X0Y82 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y82 FDRE (Prop_fdre_C_Q) 0.456 -1.868 r u_confreg/led_data_reg[4]_lopt_replica/Q net (fo=1, routed) 6.229 4.362 lopt_10 C22 OBUF (Prop_obuf_I_O) 3.562 7.924 r leds_OBUF[4]_inst/O net (fo=0) 0.000 7.924 leds[4] C22 r leds[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[10]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[10] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.063ns (logic 4.003ns (39.780%) route 6.060ns (60.220%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.022 -2.320 u_confreg/sys_clk SLICE_X3Y85 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X3Y85 FDRE (Prop_fdre_C_Q) 0.456 -1.864 r u_confreg/led_data_reg[10]_lopt_replica/Q net (fo=1, routed) 6.060 4.196 lopt_1 D21 OBUF (Prop_obuf_I_O) 3.547 7.743 r leds_OBUF[10]_inst/O net (fo=0) 0.000 7.743 leds[10] D21 r leds[10] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[11]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[11] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.916ns (logic 4.023ns (40.566%) route 5.894ns (59.434%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.023 -2.319 u_confreg/sys_clk SLICE_X4Y89 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X4Y89 FDRE (Prop_fdre_C_Q) 0.456 -1.863 r u_confreg/led_data_reg[11]_lopt_replica/Q net (fo=1, routed) 5.894 4.031 lopt_2 A18 OBUF (Prop_obuf_I_O) 3.567 7.598 r leds_OBUF[11]_inst/O net (fo=0) 0.000 7.598 leds[11] A18 r leds[11] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_hsync (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.930ns (logic 4.249ns (42.789%) route 5.681ns (57.211%)) Logic Levels: 3 (LUT5=2 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.007 -2.335 u_axi_dvi/sys_clk SLICE_X5Y76 FDRE r u_axi_dvi/hdata_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y76 FDRE (Prop_fdre_C_Q) 0.456 -1.879 r u_axi_dvi/hdata_reg[3]/Q net (fo=11, routed) 1.495 -0.384 u_axi_dvi/hdata_reg_n_0_[3] SLICE_X1Y79 LUT5 (Prop_lut5_I2_O) 0.124 -0.260 f u_axi_dvi/video_hsync_OBUF_inst_i_2/O net (fo=1, routed) 0.433 0.173 u_axi_dvi/video_hsync_OBUF_inst_i_2_n_0 SLICE_X1Y79 LUT5 (Prop_lut5_I4_O) 0.124 0.297 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O net (fo=1, routed) 3.753 4.050 video_hsync_OBUF J24 OBUF (Prop_obuf_I_O) 3.545 7.595 r video_hsync_OBUF_inst/O net (fo=0) 0.000 7.595 video_hsync J24 r video_hsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[13]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[13] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.787ns (logic 4.027ns (41.143%) route 5.760ns (58.857%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.023 -2.319 u_confreg/sys_clk SLICE_X4Y89 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X4Y89 FDRE (Prop_fdre_C_Q) 0.456 -1.863 r u_confreg/led_data_reg[13]_lopt_replica/Q net (fo=1, routed) 5.760 3.897 lopt_4 A22 OBUF (Prop_obuf_I_O) 3.571 7.468 r leds_OBUF[13]_inst/O net (fo=0) 0.000 7.468 leds[13] A22 r leds[13] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[1]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.770ns (logic 3.997ns (40.912%) route 5.773ns (59.088%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.024 -2.318 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.862 r u_confreg/led_data_reg[1]_lopt_replica/Q net (fo=1, routed) 5.773 3.911 lopt_7 E21 OBUF (Prop_obuf_I_O) 3.541 7.452 r leds_OBUF[1]_inst/O net (fo=0) 0.000 7.452 leds[1] E21 r leds[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[9]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[9] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.736ns (logic 4.237ns (43.523%) route 5.498ns (56.477%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.019 -2.323 u_confreg/sys_clk SLICE_X2Y83 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y83 FDRE (Prop_fdre_C_Q) 0.478 -1.845 r u_confreg/led_data_reg[9]_lopt_replica/Q net (fo=1, routed) 5.498 3.654 lopt_15 A23 OBUF (Prop_obuf_I_O) 3.759 7.413 r leds_OBUF[9]_inst/O net (fo=0) 0.000 7.413 leds[9] A23 r leds[9] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.642ns (logic 3.976ns (41.237%) route 5.666ns (58.763%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.025 -2.317 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y60 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y60 FDCE (Prop_fdce_C_Q) 0.456 -1.861 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q net (fo=1, routed) 5.666 3.805 dpy1_OBUF[7] G17 OBUF (Prop_obuf_I_O) 3.520 7.325 r dpy1_OBUF[7]_inst/O net (fo=0) 0.000 7.325 dpy1[7] G17 r dpy1[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.621ns (logic 4.021ns (41.799%) route 5.599ns (58.201%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.025 -2.317 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y60 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y60 FDCE (Prop_fdce_C_Q) 0.456 -1.861 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q net (fo=1, routed) 5.599 3.739 dpy1_OBUF[0] A17 OBUF (Prop_obuf_I_O) 3.565 7.304 r dpy1_OBUF[0]_inst/O net (fo=0) 0.000 7.304 dpy1[0] A17 r dpy1[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[3]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.414ns (logic 4.080ns (43.339%) route 5.334ns (56.661%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.020 -2.322 u_confreg/sys_clk SLICE_X2Y84 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y84 FDRE (Prop_fdre_C_Q) 0.518 -1.804 r u_confreg/led_data_reg[3]_lopt_replica/Q net (fo=1, routed) 5.334 3.531 lopt_9 D23 OBUF (Prop_obuf_I_O) 3.562 7.093 r leds_OBUF[3]_inst/O net (fo=0) 0.000 7.093 leds[3] D23 r leds[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[2]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.411ns (logic 4.105ns (43.619%) route 5.306ns (56.381%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.019 -2.323 u_confreg/sys_clk SLICE_X2Y83 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y83 FDRE (Prop_fdre_C_Q) 0.518 -1.805 r u_confreg/led_data_reg[2]_lopt_replica/Q net (fo=1, routed) 5.306 3.501 lopt_8 A24 OBUF (Prop_obuf_I_O) 3.587 7.088 r leds_OBUF[2]_inst/O net (fo=0) 0.000 7.088 leds[2] A24 r leds[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.370ns (logic 4.005ns (42.742%) route 5.365ns (57.258%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.025 -2.317 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y60 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y60 FDCE (Prop_fdce_C_Q) 0.456 -1.861 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q net (fo=1, routed) 5.365 3.505 dpy1_OBUF[1] D16 OBUF (Prop_obuf_I_O) 3.549 7.054 r dpy1_OBUF[1]_inst/O net (fo=0) 0.000 7.054 dpy1[1] D16 r dpy1[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.296ns (logic 4.016ns (43.203%) route 5.280ns (56.797%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.024 -2.318 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y61 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y61 FDCE (Prop_fdce_C_Q) 0.456 -1.862 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q net (fo=1, routed) 5.280 3.418 dpy0_OBUF[0] B19 OBUF (Prop_obuf_I_O) 3.560 6.978 r dpy0_OBUF[0]_inst/O net (fo=0) 0.000 6.978 dpy0[0] B19 r dpy0[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[14]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[14] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.298ns (logic 4.081ns (43.890%) route 5.217ns (56.110%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.019 -2.323 u_confreg/sys_clk SLICE_X2Y83 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y83 FDRE (Prop_fdre_C_Q) 0.518 -1.805 r u_confreg/led_data_reg[14]_lopt_replica/Q net (fo=1, routed) 5.217 3.412 lopt_5 A20 OBUF (Prop_obuf_I_O) 3.563 6.975 r leds_OBUF[14]_inst/O net (fo=0) 0.000 6.975 leds[14] A20 r leds[14] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.274ns (logic 3.998ns (43.106%) route 5.276ns (56.894%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.025 -2.317 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y59 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y59 FDCE (Prop_fdce_C_Q) 0.456 -1.861 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q net (fo=1, routed) 5.276 3.416 dpy1_OBUF[2] E17 OBUF (Prop_obuf_I_O) 3.542 6.957 r dpy1_OBUF[2]_inst/O net (fo=0) 0.000 6.957 dpy1[2] E17 r dpy1[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.974ns (logic 4.014ns (44.734%) route 4.960ns (55.266%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.024 -2.318 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y61 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y61 FDCE (Prop_fdce_C_Q) 0.456 -1.862 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q net (fo=1, routed) 4.960 3.098 dpy0_OBUF[2] B21 OBUF (Prop_obuf_I_O) 3.558 6.656 r dpy0_OBUF[2]_inst/O net (fo=0) 0.000 6.656 dpy0[2] B21 r dpy0[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[6]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.877ns (logic 3.998ns (45.034%) route 4.879ns (54.966%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.018 -2.324 u_confreg/sys_clk SLICE_X0Y82 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y82 FDRE (Prop_fdre_C_Q) 0.456 -1.868 r u_confreg/led_data_reg[6]_lopt_replica/Q net (fo=1, routed) 4.879 3.012 lopt_12 E20 OBUF (Prop_obuf_I_O) 3.542 6.553 r leds_OBUF[6]_inst/O net (fo=0) 0.000 6.553 leds[6] E20 r leds[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[12]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[12] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.647ns (logic 4.060ns (46.955%) route 4.587ns (53.045%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.019 -2.323 u_confreg/sys_clk SLICE_X2Y83 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y83 FDRE (Prop_fdre_C_Q) 0.518 -1.805 r u_confreg/led_data_reg[12]_lopt_replica/Q net (fo=1, routed) 4.587 2.782 lopt_3 D20 OBUF (Prop_obuf_I_O) 3.542 6.325 r leds_OBUF[12]_inst/O net (fo=0) 0.000 6.325 leds[12] D20 r leds[12] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[5]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.593ns (logic 4.009ns (46.660%) route 4.583ns (53.340%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.015 -2.327 u_confreg/sys_clk SLICE_X1Y80 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X1Y80 FDRE (Prop_fdre_C_Q) 0.456 -1.871 r u_confreg/led_data_reg[5]_lopt_replica/Q net (fo=1, routed) 4.583 2.713 lopt_11 C21 OBUF (Prop_obuf_I_O) 3.553 6.266 r leds_OBUF[5]_inst/O net (fo=0) 0.000 6.266 leds[5] C21 r leds[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.502ns (logic 4.031ns (47.411%) route 4.471ns (52.589%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.023 -2.319 u_confreg/sys_clk SLICE_X4Y89 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X4Y89 FDRE (Prop_fdre_C_Q) 0.456 -1.863 r u_confreg/led_data_reg[0]_lopt_replica/Q net (fo=1, routed) 4.471 2.609 lopt B24 OBUF (Prop_obuf_I_O) 3.575 6.183 r leds_OBUF[0]_inst/O net (fo=0) 0.000 6.183 leds[0] B24 r leds[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[7]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.468ns (logic 4.028ns (47.566%) route 4.440ns (52.434%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.015 -2.327 u_confreg/sys_clk SLICE_X0Y80 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y80 FDRE (Prop_fdre_C_Q) 0.456 -1.871 r u_confreg/led_data_reg[7]_lopt_replica/Q net (fo=1, routed) 4.440 2.570 lopt_13 B22 OBUF (Prop_obuf_I_O) 3.572 6.142 r leds_OBUF[7]_inst/O net (fo=0) 0.000 6.142 leds[7] B22 r leds[7] (OUT) ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: To Clock: sys_clk Max Delay 163 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: dip_sw[28] (input port) Destination: u_confreg/s_rdata_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 11.148ns (logic 1.716ns (15.390%) route 9.432ns (84.610%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R5 0.000 0.000 r dip_sw[28] (IN) net (fo=0) 0.000 0.000 dip_sw[28] R5 IBUF (Prop_ibuf_I_O) 1.468 1.468 r dip_sw_IBUF[28]_inst/O net (fo=1, routed) 8.637 10.104 u_confreg/dip_sw_IBUF[28] SLICE_X10Y73 LUT5 (Prop_lut5_I4_O) 0.124 10.228 r u_confreg/s_rdata[28]_i_4/O net (fo=1, routed) 0.795 11.024 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 SLICE_X11Y71 LUT6 (Prop_lut6_I4_O) 0.124 11.148 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O net (fo=1, routed) 0.000 11.148 u_confreg/u_int_ctrl_n_3 SLICE_X11Y71 FDRE r u_confreg/s_rdata_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_confreg/sys_clk SLICE_X11Y71 FDRE r u_confreg/s_rdata_reg[28]/C Slack: inf Source: dip_sw[29] (input port) Destination: u_confreg/s_rdata_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.723ns (logic 1.726ns (16.097%) route 8.997ns (83.903%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T5 0.000 0.000 r dip_sw[29] (IN) net (fo=0) 0.000 0.000 dip_sw[29] T5 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[29]_inst/O net (fo=1, routed) 8.199 9.677 u_confreg/dip_sw_IBUF[29] SLICE_X9Y74 LUT5 (Prop_lut5_I4_O) 0.124 9.801 r u_confreg/s_rdata[29]_i_4/O net (fo=1, routed) 0.798 10.599 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 SLICE_X11Y71 LUT6 (Prop_lut6_I4_O) 0.124 10.723 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O net (fo=1, routed) 0.000 10.723 u_confreg/u_int_ctrl_n_2 SLICE_X11Y71 FDRE r u_confreg/s_rdata_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_confreg/sys_clk SLICE_X11Y71 FDRE r u_confreg/s_rdata_reg[29]/C Slack: inf Source: dip_sw[6] (input port) Destination: u_confreg/s_rdata_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.656ns (logic 1.736ns (16.290%) route 8.920ns (83.710%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.013ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L3 0.000 0.000 r dip_sw[6] (IN) net (fo=0) 0.000 0.000 dip_sw[6] L3 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[6]_inst/O net (fo=1, routed) 8.469 9.956 u_confreg/dip_sw_IBUF[6] SLICE_X12Y65 LUT5 (Prop_lut5_I4_O) 0.124 10.080 r u_confreg/s_rdata[6]_i_4/O net (fo=1, routed) 0.452 10.532 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 SLICE_X12Y65 LUT6 (Prop_lut6_I4_O) 0.124 10.656 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O net (fo=1, routed) 0.000 10.656 u_confreg/u_int_ctrl_n_25 SLICE_X12Y65 FDRE r u_confreg/s_rdata_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.815 -2.013 u_confreg/sys_clk SLICE_X12Y65 FDRE r u_confreg/s_rdata_reg[6]/C Slack: inf Source: dip_sw[2] (input port) Destination: u_confreg/s_rdata_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.571ns (logic 1.743ns (16.490%) route 8.828ns (83.509%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M2 0.000 0.000 r dip_sw[2] (IN) net (fo=0) 0.000 0.000 dip_sw[2] M2 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[2]_inst/O net (fo=1, routed) 8.165 9.660 u_confreg/dip_sw_IBUF[2] SLICE_X9Y61 LUT5 (Prop_lut5_I4_O) 0.124 9.784 r u_confreg/s_rdata[2]_i_4/O net (fo=1, routed) 0.663 10.447 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 SLICE_X8Y61 LUT6 (Prop_lut6_I4_O) 0.124 10.571 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O net (fo=1, routed) 0.000 10.571 u_confreg/u_int_ctrl_n_29 SLICE_X8Y61 FDRE r u_confreg/s_rdata_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.818 -2.010 u_confreg/sys_clk SLICE_X8Y61 FDRE r u_confreg/s_rdata_reg[2]/C Slack: inf Source: dip_sw[23] (input port) Destination: u_confreg/s_rdata_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.514ns (logic 1.766ns (16.801%) route 8.748ns (83.199%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.022ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N1 0.000 0.000 r dip_sw[23] (IN) net (fo=0) 0.000 0.000 dip_sw[23] N1 IBUF (Prop_ibuf_I_O) 1.518 1.518 r dip_sw_IBUF[23]_inst/O net (fo=1, routed) 8.596 10.115 u_confreg/dip_sw_IBUF[23] SLICE_X9Y73 LUT5 (Prop_lut5_I4_O) 0.124 10.239 r u_confreg/s_rdata[23]_i_4/O net (fo=1, routed) 0.151 10.390 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 SLICE_X9Y73 LUT6 (Prop_lut6_I4_O) 0.124 10.514 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O net (fo=1, routed) 0.000 10.514 u_confreg/u_int_ctrl_n_8 SLICE_X9Y73 FDRE r u_confreg/s_rdata_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.806 -2.022 u_confreg/sys_clk SLICE_X9Y73 FDRE r u_confreg/s_rdata_reg[23]/C Slack: inf Source: dip_sw[18] (input port) Destination: u_confreg/s_rdata_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.416ns (logic 1.737ns (16.677%) route 8.679ns (83.323%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.014ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N3 0.000 0.000 r dip_sw[18] (IN) net (fo=0) 0.000 0.000 dip_sw[18] N3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[18]_inst/O net (fo=1, routed) 8.377 9.866 u_confreg/dip_sw_IBUF[18] SLICE_X17Y66 LUT5 (Prop_lut5_I4_O) 0.124 9.990 r u_confreg/s_rdata[18]_i_4/O net (fo=1, routed) 0.302 10.292 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 SLICE_X15Y66 LUT6 (Prop_lut6_I4_O) 0.124 10.416 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O net (fo=1, routed) 0.000 10.416 u_confreg/u_int_ctrl_n_13 SLICE_X15Y66 FDRE r u_confreg/s_rdata_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.814 -2.014 u_confreg/sys_clk SLICE_X15Y66 FDRE r u_confreg/s_rdata_reg[18]/C Slack: inf Source: touch_btn[3] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.171ns (logic 1.513ns (14.873%) route 8.658ns (85.127%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -1.935ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.935ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- U2 0.000 0.000 r touch_btn[3] (IN) net (fo=0) 0.000 0.000 touch_btn[3] U2 IBUF (Prop_ibuf_I_O) 1.513 1.513 r touch_btn_IBUF[3]_inst/O net (fo=1, routed) 8.658 10.171 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] SLICE_X7Y65 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.893 -1.935 u_confreg/u_int_ctrl/sys_clk SLICE_X7Y65 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C Slack: inf Source: touch_btn[2] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.112ns (logic 1.487ns (14.703%) route 8.626ns (85.297%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -1.936ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.936ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P3 0.000 0.000 r touch_btn[2] (IN) net (fo=0) 0.000 0.000 touch_btn[2] P3 IBUF (Prop_ibuf_I_O) 1.487 1.487 r touch_btn_IBUF[2]_inst/O net (fo=1, routed) 8.626 10.112 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] SLICE_X5Y66 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.892 -1.936 u_confreg/u_int_ctrl/sys_clk SLICE_X5Y66 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C Slack: inf Source: dip_sw[3] (input port) Destination: u_confreg/s_rdata_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.089ns (logic 1.752ns (17.369%) route 8.336ns (82.631%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.934ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.934ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P1 0.000 0.000 r dip_sw[3] (IN) net (fo=0) 0.000 0.000 dip_sw[3] P1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[3]_inst/O net (fo=1, routed) 8.182 9.687 u_confreg/dip_sw_IBUF[3] SLICE_X7Y63 LUT5 (Prop_lut5_I4_O) 0.124 9.811 r u_confreg/s_rdata[3]_i_4/O net (fo=1, routed) 0.154 9.965 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 SLICE_X7Y63 LUT6 (Prop_lut6_I4_O) 0.124 10.089 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O net (fo=1, routed) 0.000 10.089 u_confreg/u_int_ctrl_n_28 SLICE_X7Y63 FDRE r u_confreg/s_rdata_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.894 -1.934 u_confreg/sys_clk SLICE_X7Y63 FDRE r u_confreg/s_rdata_reg[3]/C Slack: inf Source: dip_sw[15] (input port) Destination: u_confreg/s_rdata_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.021ns (logic 1.742ns (17.386%) route 8.279ns (82.614%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L2 0.000 0.000 r dip_sw[15] (IN) net (fo=0) 0.000 0.000 dip_sw[15] L2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[15]_inst/O net (fo=1, routed) 8.124 9.618 u_confreg/dip_sw_IBUF[15] SLICE_X13Y70 LUT5 (Prop_lut5_I4_O) 0.124 9.742 r u_confreg/s_rdata[15]_i_4/O net (fo=1, routed) 0.154 9.897 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 SLICE_X13Y70 LUT6 (Prop_lut6_I4_O) 0.124 10.021 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O net (fo=1, routed) 0.000 10.021 u_confreg/u_int_ctrl_n_16 SLICE_X13Y70 FDRE r u_confreg/s_rdata_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_confreg/sys_clk SLICE_X13Y70 FDRE r u_confreg/s_rdata_reg[15]/C Slack: inf Source: dip_sw[17] (input port) Destination: u_confreg/s_rdata_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.890ns (logic 1.752ns (17.715%) route 8.138ns (82.285%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K1 0.000 0.000 r dip_sw[17] (IN) net (fo=0) 0.000 0.000 dip_sw[17] K1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[17]_inst/O net (fo=1, routed) 7.571 9.075 u_confreg/dip_sw_IBUF[17] SLICE_X18Y69 LUT5 (Prop_lut5_I4_O) 0.124 9.199 r u_confreg/s_rdata[17]_i_4/O net (fo=1, routed) 0.567 9.766 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 SLICE_X17Y69 LUT6 (Prop_lut6_I4_O) 0.124 9.890 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O net (fo=1, routed) 0.000 9.890 u_confreg/u_int_ctrl_n_14 SLICE_X17Y69 FDRE r u_confreg/s_rdata_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_confreg/sys_clk SLICE_X17Y69 FDRE r u_confreg/s_rdata_reg[17]/C Slack: inf Source: dip_sw[16] (input port) Destination: u_confreg/s_rdata_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.843ns (logic 1.748ns (17.759%) route 8.095ns (82.241%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K2 0.000 0.000 r dip_sw[16] (IN) net (fo=0) 0.000 0.000 dip_sw[16] K2 IBUF (Prop_ibuf_I_O) 1.500 1.500 r dip_sw_IBUF[16]_inst/O net (fo=1, routed) 7.647 9.147 u_confreg/dip_sw_IBUF[16] SLICE_X18Y68 LUT5 (Prop_lut5_I4_O) 0.124 9.271 r u_confreg/s_rdata[16]_i_4/O net (fo=1, routed) 0.448 9.719 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 SLICE_X14Y68 LUT6 (Prop_lut6_I4_O) 0.124 9.843 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O net (fo=1, routed) 0.000 9.843 u_confreg/u_int_ctrl_n_15 SLICE_X14Y68 FDRE r u_confreg/s_rdata_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.811 -2.017 u_confreg/sys_clk SLICE_X14Y68 FDRE r u_confreg/s_rdata_reg[16]/C Slack: inf Source: dip_sw[12] (input port) Destination: u_confreg/s_rdata_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.793ns (logic 1.717ns (17.533%) route 8.076ns (82.467%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.014ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M5 0.000 0.000 r dip_sw[12] (IN) net (fo=0) 0.000 0.000 dip_sw[12] M5 IBUF (Prop_ibuf_I_O) 1.469 1.469 r dip_sw_IBUF[12]_inst/O net (fo=1, routed) 7.524 8.994 u_confreg/dip_sw_IBUF[12] SLICE_X19Y69 LUT5 (Prop_lut5_I4_O) 0.124 9.118 r u_confreg/s_rdata[12]_i_4/O net (fo=1, routed) 0.552 9.669 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 SLICE_X17Y66 LUT6 (Prop_lut6_I4_O) 0.124 9.793 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O net (fo=1, routed) 0.000 9.793 u_confreg/u_int_ctrl_n_19 SLICE_X17Y66 FDRE r u_confreg/s_rdata_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.814 -2.014 u_confreg/sys_clk SLICE_X17Y66 FDRE r u_confreg/s_rdata_reg[12]/C Slack: inf Source: dip_sw[31] (input port) Destination: u_confreg/s_rdata_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.709ns (logic 1.742ns (17.938%) route 7.968ns (82.062%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R2 0.000 0.000 r dip_sw[31] (IN) net (fo=0) 0.000 0.000 dip_sw[31] R2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[31]_inst/O net (fo=1, routed) 7.403 8.897 u_confreg/dip_sw_IBUF[31] SLICE_X19Y68 LUT5 (Prop_lut5_I4_O) 0.124 9.021 r u_confreg/s_rdata[31]_i_6/O net (fo=1, routed) 0.564 9.585 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 SLICE_X17Y68 LUT6 (Prop_lut6_I4_O) 0.124 9.709 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O net (fo=1, routed) 0.000 9.709 u_confreg/u_int_ctrl_n_0 SLICE_X17Y68 FDRE r u_confreg/s_rdata_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.811 -2.017 u_confreg/sys_clk SLICE_X17Y68 FDRE r u_confreg/s_rdata_reg[31]/C Slack: inf Source: touch_btn[0] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.498ns (logic 1.499ns (15.782%) route 7.999ns (84.218%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -2.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.008ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T2 0.000 0.000 r touch_btn[0] (IN) net (fo=0) 0.000 0.000 touch_btn[0] T2 IBUF (Prop_ibuf_I_O) 1.499 1.499 r touch_btn_IBUF[0]_inst/O net (fo=1, routed) 7.999 9.498 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] SLICE_X10Y60 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.820 -2.008 u_confreg/u_int_ctrl/sys_clk SLICE_X10Y60 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C Slack: inf Source: dip_sw[25] (input port) Destination: u_confreg/s_rdata_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.334ns (logic 1.737ns (18.612%) route 7.597ns (81.388%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.014ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R3 0.000 0.000 r dip_sw[25] (IN) net (fo=0) 0.000 0.000 dip_sw[25] R3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[25]_inst/O net (fo=1, routed) 7.293 8.783 u_confreg/dip_sw_IBUF[25] SLICE_X19Y66 LUT5 (Prop_lut5_I4_O) 0.124 8.907 r u_confreg/s_rdata[25]_i_4/O net (fo=1, routed) 0.304 9.210 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 SLICE_X15Y66 LUT6 (Prop_lut6_I4_O) 0.124 9.334 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O net (fo=1, routed) 0.000 9.334 u_confreg/u_int_ctrl_n_6 SLICE_X15Y66 FDRE r u_confreg/s_rdata_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.814 -2.014 u_confreg/sys_clk SLICE_X15Y66 FDRE r u_confreg/s_rdata_reg[25]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.324ns (logic 1.954ns (20.960%) route 7.370ns (79.040%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1) Clock Path Skew: -2.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 6.682 8.156 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X31Y57 LUT2 (Prop_lut2_I1_O) 0.153 8.309 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O net (fo=2, routed) 0.688 8.997 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 SLICE_X31Y57 LUT6 (Prop_lut6_I2_O) 0.327 9.324 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O net (fo=1, routed) 0.000 9.324 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 SLICE_X31Y57 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.811 -2.017 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X31Y57 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.296ns (logic 1.949ns (20.970%) route 7.347ns (79.030%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) Clock Path Skew: -2.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 6.682 8.156 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X31Y57 LUT2 (Prop_lut2_I1_O) 0.153 8.309 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O net (fo=2, routed) 0.282 8.591 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 SLICE_X31Y57 LUT5 (Prop_lut5_I1_O) 0.322 8.913 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O net (fo=1, routed) 0.383 9.296 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 SLICE_X31Y57 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.811 -2.017 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X31Y57 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C Slack: inf Source: dip_sw[1] (input port) Destination: u_confreg/s_rdata_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.167ns (logic 1.746ns (19.044%) route 7.422ns (80.956%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J3 0.000 0.000 r dip_sw[1] (IN) net (fo=0) 0.000 0.000 dip_sw[1] J3 IBUF (Prop_ibuf_I_O) 1.498 1.498 r dip_sw_IBUF[1]_inst/O net (fo=1, routed) 6.757 8.254 u_confreg/dip_sw_IBUF[1] SLICE_X9Y60 LUT5 (Prop_lut5_I4_O) 0.124 8.378 r u_confreg/s_rdata[1]_i_4/O net (fo=1, routed) 0.665 9.043 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 SLICE_X9Y60 LUT6 (Prop_lut6_I4_O) 0.124 9.167 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O net (fo=1, routed) 0.000 9.167 u_confreg/u_int_ctrl_n_30 SLICE_X9Y60 FDRE r u_confreg/s_rdata_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.819 -2.009 u_confreg/sys_clk SLICE_X9Y60 FDRE r u_confreg/s_rdata_reg[1]/C Slack: inf Source: dip_sw[11] (input port) Destination: u_confreg/s_rdata_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.118ns (logic 1.719ns (18.855%) route 7.399ns (81.145%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.013ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L7 0.000 0.000 r dip_sw[11] (IN) net (fo=0) 0.000 0.000 dip_sw[11] L7 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[11]_inst/O net (fo=1, routed) 6.451 7.922 u_confreg/dip_sw_IBUF[11] SLICE_X19Y66 LUT5 (Prop_lut5_I4_O) 0.124 8.046 r u_confreg/s_rdata[11]_i_4/O net (fo=1, routed) 0.948 8.994 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 SLICE_X15Y65 LUT6 (Prop_lut6_I4_O) 0.124 9.118 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O net (fo=1, routed) 0.000 9.118 u_confreg/u_int_ctrl_n_20 SLICE_X15Y65 FDRE r u_confreg/s_rdata_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.815 -2.013 u_confreg/sys_clk SLICE_X15Y65 FDRE r u_confreg/s_rdata_reg[11]/C Slack: inf Source: dip_sw[10] (input port) Destination: u_confreg/s_rdata_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.049ns (logic 1.720ns (19.010%) route 7.329ns (80.990%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.011ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M7 0.000 0.000 r dip_sw[10] (IN) net (fo=0) 0.000 0.000 dip_sw[10] M7 IBUF (Prop_ibuf_I_O) 1.472 1.472 r dip_sw_IBUF[10]_inst/O net (fo=1, routed) 6.896 8.368 u_confreg/dip_sw_IBUF[10] SLICE_X13Y62 LUT5 (Prop_lut5_I4_O) 0.124 8.492 r u_confreg/s_rdata[10]_i_4/O net (fo=1, routed) 0.433 8.925 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 SLICE_X13Y62 LUT6 (Prop_lut6_I4_O) 0.124 9.049 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O net (fo=1, routed) 0.000 9.049 u_confreg/u_int_ctrl_n_21 SLICE_X13Y62 FDRE r u_confreg/s_rdata_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.817 -2.011 u_confreg/sys_clk SLICE_X13Y62 FDRE r u_confreg/s_rdata_reg[10]/C Slack: inf Source: dip_sw[8] (input port) Destination: u_confreg/s_rdata_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.799ns (logic 1.724ns (19.590%) route 7.075ns (80.410%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.013ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M6 0.000 0.000 r dip_sw[8] (IN) net (fo=0) 0.000 0.000 dip_sw[8] M6 IBUF (Prop_ibuf_I_O) 1.476 1.476 r dip_sw_IBUF[8]_inst/O net (fo=1, routed) 6.463 7.939 u_confreg/dip_sw_IBUF[8] SLICE_X20Y66 LUT5 (Prop_lut5_I4_O) 0.124 8.063 r u_confreg/s_rdata[8]_i_4/O net (fo=1, routed) 0.612 8.675 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 SLICE_X15Y65 LUT6 (Prop_lut6_I4_O) 0.124 8.799 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O net (fo=1, routed) 0.000 8.799 u_confreg/u_int_ctrl_n_23 SLICE_X15Y65 FDRE r u_confreg/s_rdata_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.815 -2.013 u_confreg/sys_clk SLICE_X15Y65 FDRE r u_confreg/s_rdata_reg[8]/C Slack: inf Source: dip_sw[20] (input port) Destination: u_confreg/s_rdata_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.689ns (logic 1.723ns (19.830%) route 6.966ns (80.170%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.022ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M4 0.000 0.000 r dip_sw[20] (IN) net (fo=0) 0.000 0.000 dip_sw[20] M4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r dip_sw_IBUF[20]_inst/O net (fo=1, routed) 6.286 7.761 u_confreg/dip_sw_IBUF[20] SLICE_X8Y73 LUT5 (Prop_lut5_I4_O) 0.124 7.885 r u_confreg/s_rdata[20]_i_4/O net (fo=1, routed) 0.680 8.565 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 SLICE_X8Y73 LUT6 (Prop_lut6_I4_O) 0.124 8.689 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O net (fo=1, routed) 0.000 8.689 u_confreg/u_int_ctrl_n_11 SLICE_X8Y73 FDRE r u_confreg/s_rdata_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.806 -2.022 u_confreg/sys_clk SLICE_X8Y73 FDRE r u_confreg/s_rdata_reg[20]/C Slack: inf Source: dip_sw[5] (input port) Destination: u_confreg/s_rdata_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.673ns (logic 1.718ns (19.814%) route 6.954ns (80.186%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.012ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L5 0.000 0.000 r dip_sw[5] (IN) net (fo=0) 0.000 0.000 dip_sw[5] L5 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[5]_inst/O net (fo=1, routed) 6.287 7.758 u_confreg/dip_sw_IBUF[5] SLICE_X13Y63 LUT5 (Prop_lut5_I4_O) 0.124 7.882 r u_confreg/s_rdata[5]_i_4/O net (fo=1, routed) 0.667 8.549 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 SLICE_X13Y63 LUT6 (Prop_lut6_I4_O) 0.124 8.673 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O net (fo=1, routed) 0.000 8.673 u_confreg/u_int_ctrl_n_26 SLICE_X13Y63 FDRE r u_confreg/s_rdata_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.816 -2.012 u_confreg/sys_clk SLICE_X13Y63 FDRE r u_confreg/s_rdata_reg[5]/C Slack: inf Source: dip_sw[19] (input port) Destination: u_confreg/s_rdata_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.479ns (logic 1.726ns (20.358%) route 6.753ns (79.642%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L4 0.000 0.000 r dip_sw[19] (IN) net (fo=0) 0.000 0.000 dip_sw[19] L4 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[19]_inst/O net (fo=1, routed) 6.602 8.080 u_confreg/dip_sw_IBUF[19] SLICE_X17Y69 LUT5 (Prop_lut5_I4_O) 0.124 8.204 r u_confreg/s_rdata[19]_i_4/O net (fo=1, routed) 0.151 8.355 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 SLICE_X17Y69 LUT6 (Prop_lut6_I4_O) 0.124 8.479 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O net (fo=1, routed) 0.000 8.479 u_confreg/u_int_ctrl_n_12 SLICE_X17Y69 FDRE r u_confreg/s_rdata_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_confreg/sys_clk SLICE_X17Y69 FDRE r u_confreg/s_rdata_reg[19]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.463ns (logic 1.598ns (18.885%) route 6.865ns (81.115%)) Logic Levels: 2 (IBUF=1 LUT5=1) Clock Path Skew: -2.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 6.865 8.339 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF SLICE_X35Y57 LUT5 (Prop_lut5_I2_O) 0.124 8.463 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O net (fo=1, routed) 0.000 8.463 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 SLICE_X35Y57 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X35Y57 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C Slack: inf Source: dip_sw[9] (input port) Destination: u_confreg/s_rdata_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.387ns (logic 1.718ns (20.481%) route 6.669ns (79.519%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.013ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N7 0.000 0.000 r dip_sw[9] (IN) net (fo=0) 0.000 0.000 dip_sw[9] N7 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[9]_inst/O net (fo=1, routed) 6.406 7.876 u_confreg/dip_sw_IBUF[9] SLICE_X15Y65 LUT5 (Prop_lut5_I4_O) 0.124 8.000 r u_confreg/s_rdata[9]_i_4/O net (fo=1, routed) 0.263 8.263 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 SLICE_X15Y65 LUT6 (Prop_lut6_I4_O) 0.124 8.387 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O net (fo=1, routed) 0.000 8.387 u_confreg/u_int_ctrl_n_22 SLICE_X15Y65 FDRE r u_confreg/s_rdata_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.815 -2.013 u_confreg/sys_clk SLICE_X15Y65 FDRE r u_confreg/s_rdata_reg[9]/C Slack: inf Source: dip_sw[13] (input port) Destination: u_confreg/s_rdata_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.376ns (logic 1.734ns (20.700%) route 6.642ns (79.300%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K3 0.000 0.000 r dip_sw[13] (IN) net (fo=0) 0.000 0.000 dip_sw[13] K3 IBUF (Prop_ibuf_I_O) 1.486 1.486 r dip_sw_IBUF[13]_inst/O net (fo=1, routed) 6.186 7.672 u_confreg/dip_sw_IBUF[13] SLICE_X20Y68 LUT5 (Prop_lut5_I4_O) 0.124 7.796 r u_confreg/s_rdata[13]_i_4/O net (fo=1, routed) 0.456 8.252 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 SLICE_X17Y68 LUT6 (Prop_lut6_I4_O) 0.124 8.376 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O net (fo=1, routed) 0.000 8.376 u_confreg/u_int_ctrl_n_18 SLICE_X17Y68 FDRE r u_confreg/s_rdata_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.811 -2.017 u_confreg/sys_clk SLICE_X17Y68 FDRE r u_confreg/s_rdata_reg[13]/C Slack: inf Source: dip_sw[4] (input port) Destination: u_confreg/s_rdata_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.322ns (logic 1.736ns (20.863%) route 6.586ns (79.137%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.934ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.934ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P4 0.000 0.000 r dip_sw[4] (IN) net (fo=0) 0.000 0.000 dip_sw[4] P4 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[4]_inst/O net (fo=1, routed) 5.919 7.407 u_confreg/dip_sw_IBUF[4] SLICE_X7Y63 LUT5 (Prop_lut5_I4_O) 0.124 7.531 r u_confreg/s_rdata[4]_i_4/O net (fo=1, routed) 0.667 8.198 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 SLICE_X7Y63 LUT6 (Prop_lut6_I4_O) 0.124 8.322 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O net (fo=1, routed) 0.000 8.322 u_confreg/u_int_ctrl_n_27 SLICE_X7Y63 FDRE r u_confreg/s_rdata_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.894 -1.934 u_confreg/sys_clk SLICE_X7Y63 FDRE r u_confreg/s_rdata_reg[4]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.280ns (logic 1.598ns (19.304%) route 6.682ns (80.696%)) Logic Levels: 2 (IBUF=1 LUT5=1) Clock Path Skew: -2.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 r UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 6.682 8.156 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X31Y57 LUT5 (Prop_lut5_I0_O) 0.124 8.280 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O net (fo=1, routed) 0.000 8.280 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 SLICE_X31Y57 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.811 -2.017 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X31Y57 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C Slack: inf Source: dip_sw[21] (input port) Destination: u_confreg/s_rdata_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.259ns (logic 1.736ns (21.021%) route 6.523ns (78.979%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.022ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N2 0.000 0.000 r dip_sw[21] (IN) net (fo=0) 0.000 0.000 dip_sw[21] N2 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[21]_inst/O net (fo=1, routed) 6.219 7.707 u_confreg/dip_sw_IBUF[21] SLICE_X9Y74 LUT5 (Prop_lut5_I4_O) 0.124 7.831 r u_confreg/s_rdata[21]_i_4/O net (fo=1, routed) 0.304 8.135 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 SLICE_X9Y73 LUT6 (Prop_lut6_I4_O) 0.124 8.259 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O net (fo=1, routed) 0.000 8.259 u_confreg/u_int_ctrl_n_10 SLICE_X9Y73 FDRE r u_confreg/s_rdata_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.806 -2.022 u_confreg/sys_clk SLICE_X9Y73 FDRE r u_confreg/s_rdata_reg[21]/C Slack: inf Source: dip_sw[26] (input port) Destination: u_confreg/s_rdata_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.223ns (logic 1.757ns (21.370%) route 6.466ns (78.630%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T4 0.000 0.000 r dip_sw[26] (IN) net (fo=0) 0.000 0.000 dip_sw[26] T4 IBUF (Prop_ibuf_I_O) 1.509 1.509 r dip_sw_IBUF[26]_inst/O net (fo=1, routed) 5.872 7.381 u_confreg/dip_sw_IBUF[26] SLICE_X9Y73 LUT5 (Prop_lut5_I4_O) 0.124 7.505 r u_confreg/s_rdata[26]_i_4/O net (fo=1, routed) 0.594 8.099 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 SLICE_X11Y71 LUT6 (Prop_lut6_I4_O) 0.124 8.223 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O net (fo=1, routed) 0.000 8.223 u_confreg/u_int_ctrl_n_5 SLICE_X11Y71 FDRE r u_confreg/s_rdata_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_confreg/sys_clk SLICE_X11Y71 FDRE r u_confreg/s_rdata_reg[26]/C Slack: inf Source: dip_sw[7] (input port) Destination: u_confreg/s_rdata_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.211ns (logic 1.719ns (20.939%) route 6.492ns (79.061%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N6 0.000 0.000 r dip_sw[7] (IN) net (fo=0) 0.000 0.000 dip_sw[7] N6 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[7]_inst/O net (fo=1, routed) 5.825 7.297 u_confreg/dip_sw_IBUF[7] SLICE_X8Y61 LUT5 (Prop_lut5_I4_O) 0.124 7.421 r u_confreg/s_rdata[7]_i_4/O net (fo=1, routed) 0.666 8.087 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 SLICE_X8Y61 LUT6 (Prop_lut6_I4_O) 0.124 8.211 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O net (fo=1, routed) 0.000 8.211 u_confreg/u_int_ctrl_n_24 SLICE_X8Y61 FDRE r u_confreg/s_rdata_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.818 -2.010 u_confreg/sys_clk SLICE_X8Y61 FDRE r u_confreg/s_rdata_reg[7]/C Slack: inf Source: dip_sw[0] (input port) Destination: u_confreg/s_rdata_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.118ns (logic 1.743ns (21.472%) route 6.375ns (78.528%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T3 0.000 0.000 r dip_sw[0] (IN) net (fo=0) 0.000 0.000 dip_sw[0] T3 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[0]_inst/O net (fo=1, routed) 5.809 7.304 u_confreg/dip_sw_IBUF[0] SLICE_X12Y62 LUT5 (Prop_lut5_I4_O) 0.124 7.428 r u_confreg/s_rdata[0]_i_4/O net (fo=1, routed) 0.566 7.994 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 SLICE_X12Y60 LUT6 (Prop_lut6_I4_O) 0.124 8.118 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O net (fo=1, routed) 0.000 8.118 u_confreg/u_int_ctrl_n_31 SLICE_X12Y60 FDRE r u_confreg/s_rdata_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.819 -2.009 u_confreg/sys_clk SLICE_X12Y60 FDRE r u_confreg/s_rdata_reg[0]/C Slack: inf Source: dip_sw[27] (input port) Destination: u_confreg/s_rdata_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.106ns (logic 1.753ns (21.625%) route 6.353ns (78.375%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R1 0.000 0.000 r dip_sw[27] (IN) net (fo=0) 0.000 0.000 dip_sw[27] R1 IBUF (Prop_ibuf_I_O) 1.505 1.505 r dip_sw_IBUF[27]_inst/O net (fo=1, routed) 5.404 6.909 u_confreg/dip_sw_IBUF[27] SLICE_X10Y74 LUT5 (Prop_lut5_I4_O) 0.124 7.033 r u_confreg/s_rdata[27]_i_4/O net (fo=1, routed) 0.949 7.982 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 SLICE_X11Y71 LUT6 (Prop_lut6_I4_O) 0.124 8.106 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O net (fo=1, routed) 0.000 8.106 u_confreg/u_int_ctrl_n_4 SLICE_X11Y71 FDRE r u_confreg/s_rdata_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_confreg/sys_clk SLICE_X11Y71 FDRE r u_confreg/s_rdata_reg[27]/C Slack: inf Source: dip_sw[14] (input port) Destination: u_confreg/s_rdata_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.945ns (logic 1.763ns (22.192%) route 6.182ns (77.808%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.012ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.012ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J1 0.000 0.000 r dip_sw[14] (IN) net (fo=0) 0.000 0.000 dip_sw[14] J1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r dip_sw_IBUF[14]_inst/O net (fo=1, routed) 6.027 7.542 u_confreg/dip_sw_IBUF[14] SLICE_X13Y63 LUT5 (Prop_lut5_I4_O) 0.124 7.666 r u_confreg/s_rdata[14]_i_4/O net (fo=1, routed) 0.154 7.821 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 SLICE_X13Y63 LUT6 (Prop_lut6_I4_O) 0.124 7.945 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O net (fo=1, routed) 0.000 7.945 u_confreg/u_int_ctrl_n_17 SLICE_X13Y63 FDRE r u_confreg/s_rdata_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.816 -2.012 u_confreg/sys_clk SLICE_X13Y63 FDRE r u_confreg/s_rdata_reg[14]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.864ns (logic 1.598ns (20.324%) route 6.266ns (79.676%)) Logic Levels: 2 (IBUF=1 LUT4=1) Clock Path Skew: -2.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 r UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 6.266 7.740 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_TX_IBUF SLICE_X31Y60 LUT4 (Prop_lut4_I2_O) 0.124 7.864 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O net (fo=1, routed) 0.000 7.864 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i SLICE_X31Y60 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk SLICE_X31Y60 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C Slack: inf Source: touch_btn[1] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.716ns (logic 1.515ns (19.635%) route 6.201ns (80.365%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -2.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.008ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M1 0.000 0.000 r touch_btn[1] (IN) net (fo=0) 0.000 0.000 touch_btn[1] M1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r touch_btn_IBUF[1]_inst/O net (fo=1, routed) 6.201 7.716 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] SLICE_X19Y58 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.820 -2.008 u_confreg/u_int_ctrl/sys_clk SLICE_X19Y58 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C Slack: inf Source: dip_sw[22] (input port) Destination: u_confreg/s_rdata_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.564ns (logic 1.710ns (22.610%) route 5.854ns (77.390%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.022ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P6 0.000 0.000 r dip_sw[22] (IN) net (fo=0) 0.000 0.000 dip_sw[22] P6 IBUF (Prop_ibuf_I_O) 1.462 1.462 r dip_sw_IBUF[22]_inst/O net (fo=1, routed) 5.551 7.013 u_confreg/dip_sw_IBUF[22] SLICE_X8Y74 LUT5 (Prop_lut5_I4_O) 0.124 7.137 r u_confreg/s_rdata[22]_i_4/O net (fo=1, routed) 0.303 7.440 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 SLICE_X8Y73 LUT6 (Prop_lut6_I4_O) 0.124 7.564 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O net (fo=1, routed) 0.000 7.564 u_confreg/u_int_ctrl_n_9 SLICE_X8Y73 FDRE r u_confreg/s_rdata_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.806 -2.022 u_confreg/sys_clk SLICE_X8Y73 FDRE r u_confreg/s_rdata_reg[22]/C Slack: inf Source: dip_sw[24] (input port) Destination: u_confreg/s_rdata_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.501ns (logic 1.714ns (22.855%) route 5.787ns (77.145%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.023ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.023ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P5 0.000 0.000 r dip_sw[24] (IN) net (fo=0) 0.000 0.000 dip_sw[24] P5 IBUF (Prop_ibuf_I_O) 1.466 1.466 r dip_sw_IBUF[24]_inst/O net (fo=1, routed) 5.335 6.802 u_confreg/dip_sw_IBUF[24] SLICE_X10Y74 LUT5 (Prop_lut5_I4_O) 0.124 6.926 r u_confreg/s_rdata[24]_i_4/O net (fo=1, routed) 0.452 7.377 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 SLICE_X10Y74 LUT6 (Prop_lut6_I4_O) 0.124 7.501 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O net (fo=1, routed) 0.000 7.501 u_confreg/u_int_ctrl_n_7 SLICE_X10Y74 FDRE r u_confreg/s_rdata_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.805 -2.023 u_confreg/sys_clk SLICE_X10Y74 FDRE r u_confreg/s_rdata_reg[24]/C Slack: inf Source: dip_sw[30] (input port) Destination: u_confreg/s_rdata_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.987ns (logic 1.707ns (24.431%) route 5.280ns (75.569%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R6 0.000 0.000 r dip_sw[30] (IN) net (fo=0) 0.000 0.000 dip_sw[30] R6 IBUF (Prop_ibuf_I_O) 1.459 1.459 r dip_sw_IBUF[30]_inst/O net (fo=1, routed) 4.609 6.068 u_confreg/dip_sw_IBUF[30] SLICE_X19Y68 LUT5 (Prop_lut5_I4_O) 0.124 6.192 r u_confreg/s_rdata[30]_i_4/O net (fo=1, routed) 0.672 6.863 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 SLICE_X14Y68 LUT6 (Prop_lut6_I4_O) 0.124 6.987 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O net (fo=1, routed) 0.000 6.987 u_confreg/u_int_ctrl_n_1 SLICE_X14Y68 FDRE r u_confreg/s_rdata_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.811 -2.017 u_confreg/sys_clk SLICE_X14Y68 FDRE r u_confreg/s_rdata_reg[30]/C Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED (internal pin) Destination: pll_clk.u_rst_sys/delay_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 6.336ns (logic 0.124ns (1.957%) route 6.212ns (98.043%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED net (fo=1, routed) 5.724 5.724 pll_clk.u_rst_sys/locked SLICE_X54Y97 LUT1 (Prop_lut1_I0_O) 0.124 5.848 f pll_clk.u_rst_sys/delay[1]_i_1/O net (fo=2, routed) 0.488 6.336 pll_clk.u_rst_sys/delay[1]_i_1_n_0 SLICE_X56Y97 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.718 -2.110 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED (internal pin) Destination: pll_clk.u_rst_sys/delay_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 6.336ns (logic 0.124ns (1.957%) route 6.212ns (98.043%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED net (fo=1, routed) 5.724 5.724 pll_clk.u_rst_sys/locked SLICE_X54Y97 LUT1 (Prop_lut1_I0_O) 0.124 5.848 f pll_clk.u_rst_sys/delay[1]_i_1/O net (fo=2, routed) 0.488 6.336 pll_clk.u_rst_sys/delay[1]_i_1_n_0 SLICE_X56Y97 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.718 -2.110 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[0] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[0] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[0] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_53 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[0] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.903 -1.926 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[10] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[10] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[10] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_43 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[10] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.903 -1.926 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[11] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[11] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[11] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_42 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[11] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.903 -1.926 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[12] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[12] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[12] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_41 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[12] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.903 -1.926 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[13] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[13] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[13] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_40 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[13] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.903 -1.926 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[14] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[14] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[14] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_39 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[14] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.903 -1.926 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[15] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[15] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[15] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_38 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[15] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.903 -1.926 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK