Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
<<<<<<< Updated upstream
| Date         : Fri Jul 10 04:15:09 2026
=======
| Date         : Sat Jul 11 09:21:05 2026
>>>>>>> Stashed changes
| Host         : fedora running 64-bit unknown
| Command      : report_design_analysis -timing -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_timing.rpt
| Design       : soc_top
| Device       : xc7a200t
| Design State : Routed
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Report Design Analysis

Table of Contents
-----------------
1. Setup Path Characteristics 1-1

1. Setup Path Characteristics 1-1
---------------------------------

<<<<<<< Updated upstream
+---------------------------+----------------------------------------------------------------------------------------+
|      Characteristics      |                                         Path #1                                        |
+---------------------------+----------------------------------------------------------------------------------------+
| Requirement               |                                                                                 20.000 |
| Path Delay                |                                                                                 15.529 |
| Logic Delay               | 6.868(45%)                                                                             |
| Net Delay                 | 8.661(55%)                                                                             |
| Clock Skew                |                                                                                 -3.955 |
| Slack                     |                                                                                  0.146 |
| Clock Relationship        | Safely Timed                                                                           |
| Logic Levels              |                                                                                     14 |
| Routes                    |                                                                                     12 |
| Logical Path              | FDCE LUT4 LUT5 LUT6 CARRY4 CARRY4 CARRY4 CARRY4 LUT4 CARRY4 CARRY4 LUT6 LUT6 LUT6 OBUF |
| Start Point Clock         | sys_clk                                                                                |
| End Point Clock           | sys_clk                                                                                |
| DSP Block                 | None                                                                                   |
| BRAM                      | None                                                                                   |
| IO Crossings              |                                                                                      3 |
| Config Crossings          |                                                                                      0 |
| SLR Crossings             |                                                                                      0 |
| PBlocks                   |                                                                                      0 |
| High Fanout               |                                                                                     80 |
| Dont Touch                |                                                                                      0 |
| Mark Debug                |                                                                                      0 |
| Start Point Pin Primitive | FDCE/C                                                                                 |
| End Point Pin Primitive   | base_ram_be_n[3]                                                                       |
| Start Point Pin           | ax_req_q_len_reg[3]/C                                                                  |
| End Point Pin             | base_ram_be_n[3]                                                                       |
+---------------------------+----------------------------------------------------------------------------------------+
=======
+---------------------------+-----------------------+
|      Characteristics      |        Path #1        |
+---------------------------+-----------------------+
| Requirement               |                13.000 |
| Path Delay                |                13.035 |
| Logic Delay               | 0.752(6%)             |
| Net Delay                 | 12.283(94%)           |
| Clock Skew                |                 0.135 |
| Slack                     |                 0.070 |
| Clock Relationship        | Safely Timed          |
| Logic Levels              |                     1 |
| Routes                    |                     1 |
| Logical Path              | FDRE MUXF7 FDCE       |
| Start Point Clock         | mlkem_clk             |
| End Point Clock           | mlkem_clk             |
| DSP Block                 | None                  |
| BRAM                      | None                  |
| IO Crossings              |                     0 |
| Config Crossings          |                     0 |
| SLR Crossings             |                     0 |
| PBlocks                   |                     0 |
| High Fanout               |                  1088 |
| Dont Touch                |                     0 |
| Mark Debug                |                     0 |
| Start Point Pin Primitive | FDRE/C                |
| End Point Pin Primitive   | FDCE/D                |
| Start Point Pin           | dj_wb_inz_reg/C       |
| End Point Pin             | dj_block_r_reg[732]/D |
+---------------------------+-----------------------+
>>>>>>> Stashed changes
* Bounding box calculated as % of dimensions for the target device (436, 500)