Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 <<<<<<< Updated upstream | Date : Fri Jul 10 04:14:54 2026 ======= | Date : Sat Jul 11 09:20:56 2026 >>>>>>> Stashed changes | Host : fedora running 64-bit unknown | Command : report_timing -delay_type min -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_hold_paths.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Report <<<<<<< Updated upstream Slack (MET) : 0.040ns (arrival time - required time) Source: u_matmul_axi_slave/m_in_b_reg[1][23]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.835%) route 0.302ns (68.165%)) Logic Levels: 0 Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.040ns ======= Slack (MET) : 0.024ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.174 -0.674 SLICE_X47Y102 FDRE 0.000 -0.674 r u_matmul_axi_slave/m_in_b_reg[1][23]/C SLICE_X47Y102 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_matmul_axi_slave/m_in_b_reg[1][23]/Q net (fo=1, routed) 0.302 -0.231 u_matmul_axi_slave/mult_inst[1].u_mult/Q[23] SLICE_X59Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D ======= 1.238 -0.610 SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 <<<<<<< Updated upstream clock pessimism 0.040 -0.341 SLICE_X59Y98 FDRE (Hold_fdre_C_D) 0.070 -0.271 u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23] ------------------------------------------------------------------- required time 0.271 arrival time -0.231 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: u_matmul_axi_slave/m_in_b_reg[1][23]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.835%) route 0.302ns (68.165%)) Logic Levels: 0 Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.040ns ======= clock pessimism -0.216 -0.597 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.287 arrival time -0.263 ------------------------------------------------------------------- slack 0.024 Slack (MET) : 0.024ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.174 -0.674 SLICE_X47Y102 FDRE 0.000 -0.674 r u_matmul_axi_slave/m_in_b_reg[1][23]/C SLICE_X47Y102 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_matmul_axi_slave/m_in_b_reg[1][23]/Q net (fo=1, routed) 0.302 -0.231 u_matmul_axi_slave/mult_inst[1].u_mult/Q[23] SLICE_X59Y98 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D ======= 1.238 -0.610 SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X56Y90 RAMD32 f axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 <<<<<<< Updated upstream clock pessimism 0.040 -0.341 SLICE_X59Y98 FDRE (Hold_fdre_C_D) 0.070 -0.271 u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23] ------------------------------------------------------------------- required time 0.271 arrival time -0.231 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.412ns (logic 0.187ns (45.442%) route 0.225ns (54.558%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.413ns Source Clock Delay (SCD): -0.639ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.209 -0.639 SLICE_X82Y77 FDCE 0.000 -0.639 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C SLICE_X82Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.498 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/Q net (fo=3, routed) 0.225 -0.274 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg_n_0_[11] SLICE_X85Y77 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/I2 SLICE_X85Y77 LUT3 (Prop_lut3_I2_O) 0.046 -0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/O net (fo=1, routed) 0.000 -0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1_n_0 SLICE_X85Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.534 -0.413 clock pessimism 0.037 -0.376 SLICE_X85Y77 FDCE (Hold_fdce_C_D) 0.107 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] ------------------------------------------------------------------- required time 0.269 arrival time -0.228 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.042ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.412ns (logic 0.187ns (45.442%) route 0.225ns (54.558%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.413ns Source Clock Delay (SCD): -0.639ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.209 -0.639 SLICE_X82Y77 FDCE 0.000 -0.639 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C SLICE_X82Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.498 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/Q net (fo=3, routed) 0.225 -0.274 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg_n_0_[11] SLICE_X85Y77 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/I2 SLICE_X85Y77 LUT3 (Prop_lut3_I2_O) 0.046 -0.228 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/O net (fo=1, routed) 0.000 -0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1_n_0 SLICE_X85Y77 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.534 -0.413 clock pessimism 0.037 -0.376 SLICE_X85Y77 FDCE (Hold_fdce_C_D) 0.107 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] ------------------------------------------------------------------- required time 0.269 arrival time -0.228 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.049ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) ======= clock pessimism -0.216 -0.597 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.287 arrival time -0.263 ------------------------------------------------------------------- slack 0.024 Slack (MET) : 0.024ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.238 -0.610 SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.216 -0.597 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.287 arrival time -0.263 ------------------------------------------------------------------- slack 0.024 Slack (MET) : 0.024ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.238 -0.610 SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X56Y90 RAMD32 f axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.216 -0.597 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.287 arrival time -0.263 ------------------------------------------------------------------- slack 0.024 Slack (MET) : 0.040ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_csr/csr_badv_reg[0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.405ns (logic 0.186ns (45.911%) route 0.219ns (54.089%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.274ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.175 -0.674 SLICE_X113Y150 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C SLICE_X113Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/Q net (fo=3, routed) 0.219 -0.314 u_cpu/wb_stage/ms_to_ws_bus_r_reg_n_0_[0] SLICE_X107Y149 r u_cpu/wb_stage/csr_badv[0]_i_1/I2 SLICE_X107Y149 LUT6 (Prop_lut6_I2_O) 0.045 -0.269 r u_cpu/wb_stage/csr_badv[0]_i_1/O net (fo=1, routed) 0.000 -0.269 u_cpu/u_csr/csr_badv_reg[31]_4[0] SLICE_X107Y149 FDRE r u_cpu/u_csr/csr_badv_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.502 -0.445 clock pessimism 0.045 -0.400 SLICE_X107Y149 FDRE (Hold_fdre_C_D) 0.091 -0.309 u_cpu/u_csr/csr_badv_reg[0] ------------------------------------------------------------------- required time 0.309 arrival time -0.269 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_csr/csr_badv_reg[0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.405ns (logic 0.186ns (45.911%) route 0.219ns (54.089%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.274ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.175 -0.674 SLICE_X113Y150 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C SLICE_X113Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/Q net (fo=3, routed) 0.219 -0.314 u_cpu/wb_stage/ms_to_ws_bus_r_reg_n_0_[0] SLICE_X107Y149 f u_cpu/wb_stage/csr_badv[0]_i_1/I2 SLICE_X107Y149 LUT6 (Prop_lut6_I2_O) 0.045 -0.269 f u_cpu/wb_stage/csr_badv[0]_i_1/O net (fo=1, routed) 0.000 -0.269 u_cpu/u_csr/csr_badv_reg[31]_4[0] SLICE_X107Y149 FDRE f u_cpu/u_csr/csr_badv_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.502 -0.445 clock pessimism 0.045 -0.400 SLICE_X107Y149 FDRE (Hold_fdre_C_D) 0.091 -0.309 u_cpu/u_csr/csr_badv_reg[0] ------------------------------------------------------------------- required time 0.309 arrival time -0.269 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.049ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) >>>>>>> Stashed changes Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) <<<<<<< Updated upstream Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X97Y50 FDRE 0.000 -0.612 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C SLICE_X97Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.471 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q net (fo=4, routed) 0.068 -0.403 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 SLICE_X96Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.216 -0.599 SLICE_X96Y50 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.452 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA ------------------------------------------------------------------- required time 0.452 arrival time -0.403 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X97Y50 FDRE 0.000 -0.612 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C SLICE_X97Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.471 f u_cpu/u_csr/csr_tlbelo0_reg[14]/Q net (fo=4, routed) 0.068 -0.403 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 SLICE_X96Y50 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.216 -0.599 SLICE_X96Y50 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.452 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA ------------------------------------------------------------------- required time 0.452 arrival time -0.403 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.382ns (logic 0.141ns (36.898%) route 0.241ns (63.102%)) Logic Levels: 0 Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.487ns Source Clock Delay (SCD): -0.710ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.139 -0.710 SLICE_X85Y170 FDCE 0.000 -0.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C SLICE_X85Y170 FDCE (Prop_fdce_C_Q) 0.141 -0.569 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/Q net (fo=14, routed) 0.241 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[9] SLICE_X81Y171 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.460 -0.487 clock pessimism 0.040 -0.447 SLICE_X81Y171 FDCE (Hold_fdce_C_D) 0.070 -0.377 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9] ------------------------------------------------------------------- required time 0.377 arrival time -0.328 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.382ns (logic 0.141ns (36.898%) route 0.241ns (63.102%)) Logic Levels: 0 Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.487ns Source Clock Delay (SCD): -0.710ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.139 -0.710 SLICE_X85Y170 FDCE 0.000 -0.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C SLICE_X85Y170 FDCE (Prop_fdce_C_Q) 0.141 -0.569 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/Q net (fo=14, routed) 0.241 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[9] SLICE_X81Y171 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.460 -0.487 clock pessimism 0.040 -0.447 SLICE_X81Y171 FDCE (Hold_fdce_C_D) 0.070 -0.377 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9] ------------------------------------------------------------------- required time 0.377 arrival time -0.328 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.051ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.211ns (logic 0.141ns (66.741%) route 0.070ns (33.259%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.233 -0.615 SLICE_X67Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C SLICE_X67Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q net (fo=4, routed) 0.070 -0.404 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.216 -0.602 SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.455 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA ------------------------------------------------------------------- required time 0.455 arrival time -0.404 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.051ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.211ns (logic 0.141ns (66.741%) route 0.070ns (33.259%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.233 -0.615 SLICE_X67Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C SLICE_X67Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_cpu/u_csr/csr_tlbelo1_reg[20]/Q net (fo=4, routed) 0.070 -0.404 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 SLICE_X66Y50 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.216 -0.602 SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.455 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA ------------------------------------------------------------------- required time 0.455 arrival time -0.404 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.056ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.508ns (logic 0.213ns (41.922%) route 0.295ns (58.078%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.345ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.294ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.246 -0.602 SLICE_X112Y55 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C SLICE_X112Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.438 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/Q net (fo=5, routed) 0.295 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[8] SLICE_X114Y49 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/I2 SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.049 -0.094 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/O net (fo=1, routed) 0.000 -0.094 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[8] SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.653 -0.294 clock pessimism 0.037 -0.257 SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8] ------------------------------------------------------------------- required time 0.150 arrival time -0.094 ------------------------------------------------------------------- slack 0.056 Slack (MET) : 0.056ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.508ns (logic 0.213ns (41.922%) route 0.295ns (58.078%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.345ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.294ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.246 -0.602 SLICE_X112Y55 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C SLICE_X112Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.438 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/Q net (fo=5, routed) 0.295 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[8] SLICE_X114Y49 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/I2 SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.049 -0.094 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/O net (fo=1, routed) 0.000 -0.094 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[8] SLICE_X114Y49 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.653 -0.294 clock pessimism 0.037 -0.257 SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8] ------------------------------------------------------------------- required time 0.150 arrival time -0.094 ------------------------------------------------------------------- slack 0.056 Slack (MET) : 0.061ns (arrival time - required time) Source: u_confreg/confreg_int_set_reg[11]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[11]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.376ns (logic 0.246ns (65.365%) route 0.130ns (34.635%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.335ns Source Clock Delay (SCD): -0.494ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.355 -0.494 SLICE_X8Y49 FDRE 0.000 -0.494 r u_confreg/confreg_int_set_reg[11]/C SLICE_X8Y49 FDRE (Prop_fdre_C_Q) 0.148 -0.346 r u_confreg/confreg_int_set_reg[11]/Q net (fo=2, routed) 0.130 -0.215 u_confreg/u_int_ctrl/edge_int_state_reg[31]_0[11] SLICE_X8Y51 r u_confreg/u_int_ctrl/edge_int_state[11]_i_1/I2 SLICE_X8Y51 LUT4 (Prop_lut4_I2_O) 0.098 -0.117 r u_confreg/u_int_ctrl/edge_int_state[11]_i_1/O net (fo=1, routed) 0.000 -0.117 u_confreg/u_int_ctrl/edge_int_state[11]_i_1_n_0 SLICE_X8Y51 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.612 -0.335 clock pessimism 0.037 -0.298 SLICE_X8Y51 FDCE (Hold_fdce_C_D) 0.120 -0.178 u_confreg/u_int_ctrl/edge_int_state_reg[11] ------------------------------------------------------------------- required time 0.178 arrival time -0.117 ------------------------------------------------------------------- slack 0.061 Slack (MET) : 0.061ns (arrival time - required time) Source: u_confreg/confreg_int_set_reg[11]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[11]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.376ns (logic 0.246ns (65.365%) route 0.130ns (34.635%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.335ns Source Clock Delay (SCD): -0.494ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.355 -0.494 SLICE_X8Y49 FDRE 0.000 -0.494 r u_confreg/confreg_int_set_reg[11]/C SLICE_X8Y49 FDRE (Prop_fdre_C_Q) 0.148 -0.346 f u_confreg/confreg_int_set_reg[11]/Q net (fo=2, routed) 0.130 -0.215 u_confreg/u_int_ctrl/edge_int_state_reg[31]_0[11] SLICE_X8Y51 f u_confreg/u_int_ctrl/edge_int_state[11]_i_1/I2 SLICE_X8Y51 LUT4 (Prop_lut4_I2_O) 0.098 -0.117 f u_confreg/u_int_ctrl/edge_int_state[11]_i_1/O net (fo=1, routed) 0.000 -0.117 u_confreg/u_int_ctrl/edge_int_state[11]_i_1_n_0 SLICE_X8Y51 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.612 -0.335 clock pessimism 0.037 -0.298 SLICE_X8Y51 FDCE (Hold_fdce_C_D) 0.120 -0.178 u_confreg/u_int_ctrl/edge_int_state_reg[11] ------------------------------------------------------------------- required time 0.178 arrival time -0.117 ------------------------------------------------------------------- slack 0.061 Slack (MET) : 0.074ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.526ns (logic 0.210ns (39.912%) route 0.316ns (60.088%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.345ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.294ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.246 -0.602 SLICE_X112Y53 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C SLICE_X112Y53 FDRE (Prop_fdre_C_Q) 0.164 -0.438 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/Q net (fo=5, routed) 0.316 -0.122 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[10] SLICE_X114Y49 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/I2 SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.046 -0.076 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/O net (fo=1, routed) 0.000 -0.076 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[10] SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.653 -0.294 clock pessimism 0.037 -0.257 SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10] ------------------------------------------------------------------- required time 0.150 arrival time -0.076 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.074ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.526ns (logic 0.210ns (39.912%) route 0.316ns (60.088%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.345ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.294ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.246 -0.602 SLICE_X112Y53 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C SLICE_X112Y53 FDRE (Prop_fdre_C_Q) 0.164 -0.438 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/Q net (fo=5, routed) 0.316 -0.122 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[10] SLICE_X114Y49 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/I2 SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.046 -0.076 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/O net (fo=1, routed) 0.000 -0.076 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[10] SLICE_X114Y49 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.653 -0.294 clock pessimism 0.037 -0.257 SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10] ------------------------------------------------------------------- required time 0.150 arrival time -0.076 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.076ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.313ns Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.302 -0.546 SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.634 -0.313 clock pessimism -0.192 -0.505 SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.196 arrival time -0.120 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.076ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.313ns Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.302 -0.546 SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X2Y66 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.634 -0.313 clock pessimism -0.192 -0.505 SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.196 arrival time -0.120 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.076ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.313ns Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.302 -0.546 SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.634 -0.313 clock pessimism -0.192 -0.505 SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.196 arrival time -0.120 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.076ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.313ns Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.302 -0.546 SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X2Y66 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.634 -0.313 clock pessimism -0.192 -0.505 SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.196 arrival time -0.120 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.084ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.349ns (logic 0.164ns (46.999%) route 0.185ns (53.001%)) Logic Levels: 0 Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.506ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.343 -0.506 SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 r u_cpu/u_csr/csr_tlbidx_reg[26]/Q net (fo=33, routed) 0.185 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] SLICE_X39Y52 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.600 -0.347 clock pessimism 0.037 -0.310 SLICE_X39Y52 FDRE (Hold_fdre_C_D) 0.070 -0.240 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2] ------------------------------------------------------------------- required time 0.240 arrival time -0.157 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.349ns (logic 0.164ns (46.999%) route 0.185ns (53.001%)) Logic Levels: 0 Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.506ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.343 -0.506 SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 f u_cpu/u_csr/csr_tlbidx_reg[26]/Q net (fo=33, routed) 0.185 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] SLICE_X39Y52 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.600 -0.347 clock pessimism 0.037 -0.310 SLICE_X39Y52 FDRE (Hold_fdre_C_D) 0.070 -0.240 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2] ------------------------------------------------------------------- required time 0.240 arrival time -0.157 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_cpu/axi_bridge/araddr_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.339ns (logic 0.128ns (37.707%) route 0.211ns (62.293%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.313 -0.536 SLICE_X47Y47 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[5]/C SLICE_X47Y47 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[5]/Q net (fo=1, routed) 0.211 -0.196 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIC1 SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.569 -0.378 clock pessimism 0.037 -0.341 SLICE_X44Y51 RAMD32 (Hold_ramd32_CLK_I) 0.061 -0.280 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1 ------------------------------------------------------------------- required time 0.280 arrival time -0.196 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_cpu/axi_bridge/araddr_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.339ns (logic 0.128ns (37.707%) route 0.211ns (62.293%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.313 -0.536 SLICE_X47Y47 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[5]/C SLICE_X47Y47 FDRE (Prop_fdre_C_Q) 0.128 -0.408 f u_cpu/axi_bridge/araddr_reg[5]/Q net (fo=1, routed) 0.211 -0.196 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIC1 SLICE_X44Y51 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.569 -0.378 clock pessimism 0.037 -0.341 SLICE_X44Y51 RAMD32 (Hold_ramd32_CLK_I) 0.061 -0.280 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1 ------------------------------------------------------------------- required time 0.280 arrival time -0.196 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_cpu/axi_bridge/wstrb_reg[2]/C (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.187ns (logic 0.128ns (68.397%) route 0.059ns (31.603%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.496ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.353 -0.496 SLICE_X15Y41 FDSE 0.000 -0.496 r u_cpu/axi_bridge/wstrb_reg[2]/C SLICE_X15Y41 FDSE (Prop_fdse_C_Q) 0.128 -0.368 r u_cpu/axi_bridge/wstrb_reg[2]/Q net (fo=1, routed) 0.059 -0.309 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0 SLICE_X14Y41 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.221 -0.483 SLICE_X14Y41 RAMD32 (Hold_ramd32_CLK_I) 0.090 -0.393 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC ------------------------------------------------------------------- required time 0.393 arrival time -0.309 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_cpu/axi_bridge/wstrb_reg[2]/C (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.187ns (logic 0.128ns (68.397%) route 0.059ns (31.603%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.496ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.353 -0.496 SLICE_X15Y41 FDSE 0.000 -0.496 r u_cpu/axi_bridge/wstrb_reg[2]/C SLICE_X15Y41 FDSE (Prop_fdse_C_Q) 0.128 -0.368 f u_cpu/axi_bridge/wstrb_reg[2]/Q net (fo=1, routed) 0.059 -0.309 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0 SLICE_X14Y41 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.221 -0.483 SLICE_X14Y41 RAMD32 (Hold_ramd32_CLK_I) 0.090 -0.393 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC ------------------------------------------------------------------- required time 0.393 arrival time -0.309 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.086ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbidx_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.347ns (logic 0.141ns (40.688%) route 0.206ns (59.312%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.504ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.345 -0.504 SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[27]/C SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_tlbidx_reg[27]/Q net (fo=33, routed) 0.206 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[8] SLICE_X37Y50 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.601 -0.346 clock pessimism 0.037 -0.309 SLICE_X37Y50 FDRE (Hold_fdre_C_D) 0.066 -0.243 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3] ------------------------------------------------------------------- required time 0.243 arrival time -0.157 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbidx_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.347ns (logic 0.141ns (40.688%) route 0.206ns (59.312%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.504ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.345 -0.504 SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[27]/C SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 f u_cpu/u_csr/csr_tlbidx_reg[27]/Q net (fo=33, routed) 0.206 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[8] SLICE_X37Y50 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.601 -0.346 clock pessimism 0.037 -0.309 SLICE_X37Y50 FDRE (Hold_fdre_C_D) 0.066 -0.243 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3] ------------------------------------------------------------------- required time 0.243 arrival time -0.157 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.087ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.192 -0.531 SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.221 arrival time -0.135 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X16Y61 RAMD32 f axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.192 -0.531 SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.221 arrival time -0.135 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.192 -0.531 SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.221 arrival time -0.135 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X16Y61 RAMD32 f axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.192 -0.531 SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.221 arrival time -0.135 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMS32 f u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMS32 f u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1 ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1 ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1 ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1 ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1 ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1 ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1 ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.383 -0.466 SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.717 -0.230 clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1 ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.089ns (arrival time - required time) Source: u_confreg/int_out_or_q1_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/int_out_or_q2_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.480ns (logic 0.141ns (29.360%) route 0.339ns (70.640%)) Logic Levels: 0 Clock Path Skew: 0.316ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.260ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.309 -0.539 SLICE_X4Y50 FDRE 0.000 -0.539 r u_confreg/int_out_or_q1_reg/C SLICE_X4Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/int_out_or_q1_reg/Q net (fo=1, routed) 0.339 -0.059 u_confreg/int_out_or_q1 SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.687 -0.260 clock pessimism 0.037 -0.223 SLICE_X9Y47 FDRE (Hold_fdre_C_D) 0.075 -0.148 u_confreg/int_out_or_q2_reg ------------------------------------------------------------------- required time 0.148 arrival time -0.059 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.089ns (arrival time - required time) Source: u_confreg/int_out_or_q1_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/int_out_or_q2_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.480ns (logic 0.141ns (29.360%) route 0.339ns (70.640%)) Logic Levels: 0 Clock Path Skew: 0.316ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.260ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.309 -0.539 SLICE_X4Y50 FDRE 0.000 -0.539 r u_confreg/int_out_or_q1_reg/C SLICE_X4Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_confreg/int_out_or_q1_reg/Q net (fo=1, routed) 0.339 -0.059 u_confreg/int_out_or_q1 SLICE_X9Y47 FDRE f u_confreg/int_out_or_q2_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.687 -0.260 clock pessimism 0.037 -0.223 SLICE_X9Y47 FDRE (Hold_fdre_C_D) 0.075 -0.148 u_confreg/int_out_or_q2_reg ------------------------------------------------------------------- required time 0.148 arrival time -0.059 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.090ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[22]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.252ns (logic 0.141ns (55.979%) route 0.111ns (44.021%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.615ns ======= Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.233 -0.615 SLICE_X69Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[22]/C SLICE_X69Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_cpu/u_csr/csr_tlbelo1_reg[22]/Q net (fo=4, routed) 0.111 -0.363 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIB0 SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I ======= 1.181 -0.667 SLICE_X117Y149 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C SLICE_X117Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q net (fo=4, routed) 0.068 -0.458 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 SLICE_X116Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.561 -0.386 clock pessimism -0.213 -0.599 SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.453 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB ------------------------------------------------------------------- required time 0.453 arrival time -0.363 ------------------------------------------------------------------- slack 0.090 Slack (MET) : 0.090ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[22]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.252ns (logic 0.141ns (55.979%) route 0.111ns (44.021%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.615ns ======= 1.506 -0.441 clock pessimism -0.213 -0.654 SLICE_X116Y149 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA ------------------------------------------------------------------- required time 0.507 arrival time -0.458 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.233 -0.615 SLICE_X69Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[22]/C SLICE_X69Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_cpu/u_csr/csr_tlbelo1_reg[22]/Q net (fo=4, routed) 0.111 -0.363 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIB0 SLICE_X66Y50 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I ======= 1.181 -0.667 SLICE_X117Y149 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C SLICE_X117Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.526 f u_cpu/u_csr/csr_tlbelo1_reg[20]/Q net (fo=4, routed) 0.068 -0.458 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 SLICE_X116Y149 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.561 -0.386 clock pessimism -0.213 -0.599 SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.453 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB ------------------------------------------------------------------- required time 0.453 arrival time -0.363 ------------------------------------------------------------------- slack 0.090 Slack (MET) : 0.090ns (arrival time - required time) Source: u_cpu/axi_bridge/araddr_reg[11]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.345ns (logic 0.128ns (37.132%) route 0.217ns (62.868%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns ======= 1.506 -0.441 clock pessimism -0.213 -0.654 SLICE_X116Y149 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA ------------------------------------------------------------------- required time 0.507 arrival time -0.458 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.057ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.276ns (logic 0.141ns (51.000%) route 0.135ns (49.000%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.178 -0.670 SLICE_X135Y114 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C SLICE_X135Y114 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/Q net (fo=7, routed) 0.135 -0.394 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[6] SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.502 -0.445 clock pessimism -0.189 -0.634 SLICE_X136Y113 SRL16E (Hold_srl16e_CLK_D) 0.183 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.451 arrival time -0.394 ------------------------------------------------------------------- slack 0.057 Slack (MET) : 0.057ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.276ns (logic 0.141ns (51.000%) route 0.135ns (49.000%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.178 -0.670 SLICE_X135Y114 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C SLICE_X135Y114 FDCE (Prop_fdce_C_Q) 0.141 -0.529 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/Q net (fo=7, routed) 0.135 -0.394 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[6] SLICE_X136Y113 SRL16E f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.502 -0.445 clock pessimism -0.189 -0.634 SLICE_X136Y113 SRL16E (Hold_srl16e_CLK_D) 0.183 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.451 arrival time -0.394 ------------------------------------------------------------------- slack 0.057 Slack (MET) : 0.058ns (arrival time - required time) Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.400ns (logic 0.164ns (40.951%) route 0.236ns (59.049%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.453ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): -0.045ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.313 -0.536 SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[11]/C SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[11]/Q net (fo=1, routed) 0.217 -0.191 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC1 SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I ======= 1.164 -0.685 SLICE_X98Y152 FDRE 0.000 -0.685 r u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C SLICE_X98Y152 FDRE (Prop_fdre_C_Q) 0.164 -0.521 r u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/Q net (fo=2, routed) 0.236 -0.284 u_cpu/wb_stage/ms_to_ws_bus[78] SLICE_X99Y148 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.569 -0.378 clock pessimism 0.037 -0.341 SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) 0.060 -0.281 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1 ------------------------------------------------------------------- required time 0.281 arrival time -0.191 ------------------------------------------------------------------- slack 0.090 Slack (MET) : 0.090ns (arrival time - required time) Source: u_cpu/axi_bridge/araddr_reg[11]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.345ns (logic 0.128ns (37.132%) route 0.217ns (62.868%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns ======= 1.494 -0.453 clock pessimism 0.045 -0.408 SLICE_X99Y148 FDRE (Hold_fdre_C_D) 0.066 -0.342 u_cpu/wb_stage/ms_to_ws_bus_r_reg[114] ------------------------------------------------------------------- required time 0.342 arrival time -0.284 ------------------------------------------------------------------- slack 0.058 Slack (MET) : 0.058ns (arrival time - required time) Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.400ns (logic 0.164ns (40.951%) route 0.236ns (59.049%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.453ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): -0.045ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.313 -0.536 SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[11]/C SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 f u_cpu/axi_bridge/araddr_reg[11]/Q net (fo=1, routed) 0.217 -0.191 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC1 SLICE_X44Y52 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I ======= 1.164 -0.685 SLICE_X98Y152 FDRE 0.000 -0.685 r u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C SLICE_X98Y152 FDRE (Prop_fdre_C_Q) 0.164 -0.521 f u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/Q net (fo=2, routed) 0.236 -0.284 u_cpu/wb_stage/ms_to_ws_bus[78] SLICE_X99Y148 FDRE f u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.569 -0.378 clock pessimism 0.037 -0.341 SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) 0.060 -0.281 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1 ------------------------------------------------------------------- required time 0.281 arrival time -0.191 ------------------------------------------------------------------- slack 0.090 Slack (MET) : 0.093ns (arrival time - required time) Source: u_cpu/axi_bridge/araddr_reg[9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.358ns (logic 0.128ns (35.706%) route 0.230ns (64.294%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.313 -0.536 SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[9]/C SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[9]/Q net (fo=1, routed) 0.230 -0.177 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIB1 SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.569 -0.378 clock pessimism 0.037 -0.341 SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) 0.071 -0.270 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1 ------------------------------------------------------------------- required time 0.270 arrival time -0.177 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.093ns (arrival time - required time) Source: u_cpu/axi_bridge/araddr_reg[9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.358ns (logic 0.128ns (35.706%) route 0.230ns (64.294%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.313 -0.536 SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[9]/C SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 f u_cpu/axi_bridge/araddr_reg[9]/Q net (fo=1, routed) 0.230 -0.177 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIB1 SLICE_X44Y52 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.569 -0.378 clock pessimism 0.037 -0.341 SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) 0.071 -0.270 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1 ------------------------------------------------------------------- required time 0.270 arrival time -0.177 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.093ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.233 -0.615 SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[2] RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.601 -0.347 clock pessimism -0.212 -0.559 RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.283 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.093ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.233 -0.615 SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[2] RAMB18_X6Y27 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.601 -0.347 clock pessimism -0.212 -0.559 RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.283 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.093ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.233 -0.615 SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[2] RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.601 -0.347 clock pessimism -0.212 -0.559 RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.283 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.093ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.233 -0.615 SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[2] RAMB18_X6Y26 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.601 -0.347 clock pessimism -0.212 -0.559 RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.283 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.094ns (arrival time - required time) Source: u_cpu/axi_bridge/awaddr_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.251ns (logic 0.141ns (56.174%) route 0.110ns (43.826%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.496ns Clock Pessimism Removal (CPR): 0.222ns ======= 1.494 -0.453 clock pessimism 0.045 -0.408 SLICE_X99Y148 FDRE (Hold_fdre_C_D) 0.066 -0.342 u_cpu/wb_stage/ms_to_ws_bus_r_reg[114] ------------------------------------------------------------------- required time 0.342 arrival time -0.284 ------------------------------------------------------------------- slack 0.058 Slack (MET) : 0.061ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.683ns Clock Pessimism Removal (CPR): 0.212ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.353 -0.496 SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 r u_cpu/axi_bridge/awaddr_reg[10]/Q net (fo=1, routed) 0.110 -0.245 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 SLICE_X16Y49 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I ======= 1.166 -0.683 SLICE_X103Y161 FDRE 0.000 -0.683 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C SLICE_X103Y161 FDRE (Prop_fdre_C_Q) 0.141 -0.542 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/Q net (fo=6, routed) 0.080 -0.462 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/DIA0 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.686 -0.261 clock pessimism -0.222 -0.483 SLICE_X16Y49 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- required time 0.339 arrival time -0.245 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.094ns (arrival time - required time) Source: u_cpu/axi_bridge/awaddr_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.251ns (logic 0.141ns (56.174%) route 0.110ns (43.826%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.496ns Clock Pessimism Removal (CPR): 0.222ns ======= 1.489 -0.458 clock pessimism -0.212 -0.670 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.523 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA ------------------------------------------------------------------- required time 0.523 arrival time -0.462 ------------------------------------------------------------------- slack 0.061 Slack (MET) : 0.061ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.683ns Clock Pessimism Removal (CPR): 0.212ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.353 -0.496 SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 f u_cpu/axi_bridge/awaddr_reg[10]/Q net (fo=1, routed) 0.110 -0.245 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 SLICE_X16Y49 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I ======= 1.166 -0.683 SLICE_X103Y161 FDRE 0.000 -0.683 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C SLICE_X103Y161 FDRE (Prop_fdre_C_Q) 0.141 -0.542 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/Q net (fo=6, routed) 0.080 -0.462 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/DIA0 SLICE_X102Y161 RAMD32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.686 -0.261 clock pessimism -0.222 -0.483 SLICE_X16Y49 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- required time 0.339 arrival time -0.245 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns ======= 1.489 -0.458 clock pessimism -0.212 -0.670 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.523 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA ------------------------------------------------------------------- required time 0.523 arrival time -0.462 ------------------------------------------------------------------- slack 0.061 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.355ns (logic 0.128ns (36.084%) route 0.227ns (63.916%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.677 SLICE_X105Y150 FDRE 0.000 -0.677 r u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C SLICE_X105Y150 FDRE (Prop_fdre_C_Q) 0.128 -0.549 r u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/Q net (fo=1, routed) 0.227 -0.322 u_cpu/mem_stage/D[126] SLICE_X106Y149 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.502 -0.445 clock pessimism 0.045 -0.400 SLICE_X106Y149 FDRE (Hold_fdre_C_D) 0.016 -0.384 u_cpu/mem_stage/es_to_ms_bus_r_reg[126] ------------------------------------------------------------------- required time 0.384 arrival time -0.322 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.355ns (logic 0.128ns (36.084%) route 0.227ns (63.916%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.677 SLICE_X105Y150 FDRE 0.000 -0.677 r u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C SLICE_X105Y150 FDRE (Prop_fdre_C_Q) 0.128 -0.549 f u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/Q net (fo=1, routed) 0.227 -0.322 u_cpu/mem_stage/D[126] SLICE_X106Y149 FDRE f u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.502 -0.445 clock pessimism 0.045 -0.400 SLICE_X106Y149 FDRE (Hold_fdre_C_D) 0.016 -0.384 u_cpu/mem_stage/es_to_ms_bus_r_reg[126] ------------------------------------------------------------------- required time 0.384 arrival time -0.322 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMS32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMS32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.487 -0.460 clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.455ns (logic 0.164ns (36.015%) route 0.291ns (63.985%)) Logic Levels: 0 Clock Path Skew: 0.334ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.375ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.179 -0.669 SLICE_X108Y101 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/Q net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[16] SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.572 -0.375 clock pessimism 0.040 -0.335 SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.059 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16] ------------------------------------------------------------------- required time 0.276 arrival time -0.214 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.455ns (logic 0.164ns (36.015%) route 0.291ns (63.985%)) Logic Levels: 0 Clock Path Skew: 0.334ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.375ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.179 -0.669 SLICE_X108Y101 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/Q net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[16] SLICE_X104Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.572 -0.375 clock pessimism 0.040 -0.335 SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.059 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16] ------------------------------------------------------------------- required time 0.276 arrival time -0.214 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.063ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.223ns (logic 0.141ns (63.098%) route 0.082ns (36.902%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.181 -0.667 SLICE_X121Y148 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo0_reg[26]/C SLICE_X121Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo0_reg[26]/Q net (fo=4, routed) 0.082 -0.444 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/DIA0 SLICE_X120Y148 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.506 -0.441 clock pessimism -0.213 -0.654 SLICE_X120Y148 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA ------------------------------------------------------------------- required time 0.507 arrival time -0.444 ------------------------------------------------------------------- slack 0.063 Slack (MET) : 0.063ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.223ns (logic 0.141ns (63.098%) route 0.082ns (36.902%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.181 -0.667 SLICE_X121Y148 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo0_reg[26]/C SLICE_X121Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.526 f u_cpu/u_csr/csr_tlbelo0_reg[26]/Q net (fo=4, routed) 0.082 -0.444 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/DIA0 SLICE_X120Y148 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.506 -0.441 clock pessimism -0.213 -0.654 SLICE_X120Y148 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA ------------------------------------------------------------------- required time 0.507 arrival time -0.444 ------------------------------------------------------------------- slack 0.063 Slack (MET) : 0.064ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.443ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.179 -0.669 SLICE_X109Y149 FDRE 0.000 -0.669 r u_cpu/u_csr/csr_tlbelo0_reg[5]/C SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 r u_cpu/u_csr/csr_tlbelo0_reg[5]/Q net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.504 -0.443 clock pessimism -0.213 -0.656 SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.512 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP ------------------------------------------------------------------- required time 0.512 arrival time -0.448 ------------------------------------------------------------------- slack 0.064 Slack (MET) : 0.064ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.443ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.179 -0.669 SLICE_X109Y149 FDRE 0.000 -0.669 r u_cpu/u_csr/csr_tlbelo0_reg[5]/C SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 f u_cpu/u_csr/csr_tlbelo0_reg[5]/Q net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D SLICE_X108Y149 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.504 -0.443 clock pessimism -0.213 -0.656 SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.512 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP ------------------------------------------------------------------- required time 0.512 arrival time -0.448 ------------------------------------------------------------------- slack 0.064 Slack (MET) : 0.066ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.226ns (logic 0.141ns (62.492%) route 0.085ns (37.508%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.181 -0.667 SLICE_X117Y147 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo1_reg[14]/C SLICE_X117Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[14]/Q net (fo=4, routed) 0.085 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIA0 SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.506 -0.441 clock pessimism -0.213 -0.654 SLICE_X116Y147 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA ------------------------------------------------------------------- required time 0.507 arrival time -0.441 ------------------------------------------------------------------- slack 0.066 Slack (MET) : 0.066ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.226ns (logic 0.141ns (62.492%) route 0.085ns (37.508%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.181 -0.667 SLICE_X117Y147 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo1_reg[14]/C SLICE_X117Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.526 f u_cpu/u_csr/csr_tlbelo1_reg[14]/Q net (fo=4, routed) 0.085 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIA0 SLICE_X116Y147 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.506 -0.441 clock pessimism -0.213 -0.654 SLICE_X116Y147 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA ------------------------------------------------------------------- required time 0.507 arrival time -0.441 ------------------------------------------------------------------- slack 0.066 Slack (MET) : 0.067ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[19]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[3] SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) 0.063 -0.269 r u_axi_uart_controller/uart0/regs/M_next_carry/O[3] net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] ------------------------------------------------------------------- required time 0.336 arrival time -0.269 ------------------------------------------------------------------- slack 0.067 Slack (MET) : 0.067ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[19]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[3] SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) 0.063 -0.269 r u_axi_uart_controller/uart0/regs/M_next_carry/O[3] net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] ------------------------------------------------------------------- required time 0.336 arrival time -0.269 ------------------------------------------------------------------- slack 0.067 Slack (MET) : 0.067ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[19]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[3] SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) 0.063 -0.269 r u_axi_uart_controller/uart0/regs/M_next_carry/O[3] net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] ------------------------------------------------------------------- required time 0.336 arrival time -0.269 ------------------------------------------------------------------- slack 0.067 Slack (MET) : 0.067ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[19]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[3] SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) 0.063 -0.269 r u_axi_uart_controller/uart0/regs/M_next_carry/O[3] net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] ------------------------------------------------------------------- required time 0.336 arrival time -0.269 ------------------------------------------------------------------- slack 0.067 Slack (MET) : 0.067ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[19]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[3] SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) 0.063 -0.269 f u_axi_uart_controller/uart0/regs/M_next_carry/O[3] net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] ------------------------------------------------------------------- required time 0.336 arrival time -0.269 ------------------------------------------------------------------- slack 0.067 Slack (MET) : 0.067ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[19]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[3] SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) 0.063 -0.269 f u_axi_uart_controller/uart0/regs/M_next_carry/O[3] net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] ------------------------------------------------------------------- required time 0.336 arrival time -0.269 ------------------------------------------------------------------- slack 0.067 Slack (MET) : 0.067ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[19]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[3] SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) 0.063 -0.269 f u_axi_uart_controller/uart0/regs/M_next_carry/O[3] net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] ------------------------------------------------------------------- required time 0.336 arrival time -0.269 ------------------------------------------------------------------- slack 0.067 Slack (MET) : 0.067ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[19]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[3] SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) 0.063 -0.269 f u_axi_uart_controller/uart0/regs/M_next_carry/O[3] net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] ------------------------------------------------------------------- required time 0.336 arrival time -0.269 ------------------------------------------------------------------- slack 0.067 Slack (MET) : 0.069ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.455ns (logic 0.164ns (36.017%) route 0.291ns (63.983%)) Logic Levels: 0 Clock Path Skew: 0.334ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.375ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.179 -0.669 SLICE_X108Y101 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/Q net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[17] SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.572 -0.375 clock pessimism 0.040 -0.335 SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.052 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17] ------------------------------------------------------------------- required time 0.283 arrival time -0.214 ------------------------------------------------------------------- slack 0.069 Slack (MET) : 0.069ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.455ns (logic 0.164ns (36.017%) route 0.291ns (63.983%)) Logic Levels: 0 Clock Path Skew: 0.334ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.375ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.179 -0.669 SLICE_X108Y101 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/Q net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[17] SLICE_X104Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.572 -0.375 clock pessimism 0.040 -0.335 SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.052 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17] ------------------------------------------------------------------- required time 0.283 arrival time -0.214 ------------------------------------------------------------------- slack 0.069 Slack (MET) : 0.071ns (arrival time - required time) Source: u_matmul_axi_slave/req_1_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/busy_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.362ns (logic 0.186ns (51.410%) route 0.176ns (48.590%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.241 -0.607 SLICE_X45Y99 FDRE 0.000 -0.607 r u_matmul_axi_slave/req_1_reg/C SLICE_X45Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.466 r u_matmul_axi_slave/req_1_reg/Q net (fo=19, routed) 0.176 -0.291 u_matmul_axi_slave/p_5_in[1] SLICE_X45Y100 r u_matmul_axi_slave/busy_i_1/I2 SLICE_X45Y100 LUT6 (Prop_lut6_I2_O) 0.045 -0.246 r u_matmul_axi_slave/busy_i_1/O net (fo=1, routed) 0.000 -0.246 u_matmul_axi_slave/busy_i_1_n_0 SLICE_X45Y100 FDRE r u_matmul_axi_slave/busy_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.040 -0.408 SLICE_X45Y100 FDRE (Hold_fdre_C_D) 0.091 -0.317 u_matmul_axi_slave/busy_reg ------------------------------------------------------------------- required time 0.317 arrival time -0.246 ------------------------------------------------------------------- slack 0.071 Slack (MET) : 0.071ns (arrival time - required time) Source: u_matmul_axi_slave/req_1_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/busy_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.362ns (logic 0.186ns (51.410%) route 0.176ns (48.590%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.241 -0.607 SLICE_X45Y99 FDRE 0.000 -0.607 r u_matmul_axi_slave/req_1_reg/C SLICE_X45Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.466 f u_matmul_axi_slave/req_1_reg/Q net (fo=19, routed) 0.176 -0.291 u_matmul_axi_slave/p_5_in[1] SLICE_X45Y100 f u_matmul_axi_slave/busy_i_1/I2 SLICE_X45Y100 LUT6 (Prop_lut6_I2_O) 0.045 -0.246 f u_matmul_axi_slave/busy_i_1/O net (fo=1, routed) 0.000 -0.246 u_matmul_axi_slave/busy_i_1_n_0 SLICE_X45Y100 FDRE f u_matmul_axi_slave/busy_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.040 -0.408 SLICE_X45Y100 FDRE (Hold_fdre_C_D) 0.091 -0.317 u_matmul_axi_slave/busy_reg ------------------------------------------------------------------- required time 0.317 arrival time -0.246 ------------------------------------------------------------------- slack 0.071 Slack (MET) : 0.073ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.393ns (logic 0.227ns (57.716%) route 0.166ns (42.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.453ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X63Y98 FDRE 0.000 -0.612 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C SLICE_X63Y98 FDRE (Prop_fdre_C_Q) 0.128 -0.484 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/Q net (fo=7, routed) 0.166 -0.318 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[1] SLICE_X62Y100 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/I1 SLICE_X62Y100 LUT6 (Prop_lut6_I1_O) 0.099 -0.219 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/O net (fo=1, routed) 0.000 -0.219 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/p_1_in[2] SLICE_X62Y100 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.494 -0.453 clock pessimism 0.040 -0.413 SLICE_X62Y100 FDRE (Hold_fdre_C_D) 0.121 -0.292 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2] ------------------------------------------------------------------- required time 0.292 arrival time -0.219 ------------------------------------------------------------------- slack 0.073 Slack (MET) : 0.073ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.393ns (logic 0.227ns (57.716%) route 0.166ns (42.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.453ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X63Y98 FDRE 0.000 -0.612 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C SLICE_X63Y98 FDRE (Prop_fdre_C_Q) 0.128 -0.484 f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/Q net (fo=7, routed) 0.166 -0.318 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[1] SLICE_X62Y100 f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/I1 SLICE_X62Y100 LUT6 (Prop_lut6_I1_O) 0.099 -0.219 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/O net (fo=1, routed) 0.000 -0.219 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/p_1_in[2] SLICE_X62Y100 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.494 -0.453 clock pessimism 0.040 -0.413 SLICE_X62Y100 FDRE (Hold_fdre_C_D) 0.121 -0.292 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2] ------------------------------------------------------------------- required time 0.292 arrival time -0.219 ------------------------------------------------------------------- slack 0.073 Slack (MET) : 0.073ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.393ns (logic 0.227ns (57.716%) route 0.166ns (42.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.453ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X63Y98 FDRE 0.000 -0.612 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C SLICE_X63Y98 FDRE (Prop_fdre_C_Q) 0.128 -0.484 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/Q net (fo=7, routed) 0.166 -0.318 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[1] SLICE_X62Y100 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/I1 SLICE_X62Y100 LUT6 (Prop_lut6_I1_O) 0.099 -0.219 f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/O net (fo=1, routed) 0.000 -0.219 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/p_1_in[2] SLICE_X62Y100 FDRE f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.494 -0.453 clock pessimism 0.040 -0.413 SLICE_X62Y100 FDRE (Hold_fdre_C_D) 0.121 -0.292 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2] ------------------------------------------------------------------- required time 0.292 arrival time -0.219 ------------------------------------------------------------------- slack 0.073 Slack (MET) : 0.073ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.393ns (logic 0.227ns (57.716%) route 0.166ns (42.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.453ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X63Y98 FDRE 0.000 -0.612 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C SLICE_X63Y98 FDRE (Prop_fdre_C_Q) 0.128 -0.484 f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/Q net (fo=7, routed) 0.166 -0.318 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[1] SLICE_X62Y100 f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/I1 SLICE_X62Y100 LUT6 (Prop_lut6_I1_O) 0.099 -0.219 f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/O net (fo=1, routed) 0.000 -0.219 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/p_1_in[2] SLICE_X62Y100 FDRE f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.494 -0.453 clock pessimism 0.040 -0.413 SLICE_X62Y100 FDRE (Hold_fdre_C_D) 0.121 -0.292 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2] ------------------------------------------------------------------- required time 0.292 arrival time -0.219 ------------------------------------------------------------------- slack 0.073 Slack (MET) : 0.073ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.437ns (logic 0.189ns (43.230%) route 0.248ns (56.770%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.257ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.486ns Source Clock Delay (SCD): -0.703ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.145 -0.703 SLICE_X87Y130 FDRE 0.000 -0.703 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/Q net (fo=21, routed) 0.248 -0.314 u_Axi_CDC/wFifo/Q[27] SLICE_X82Y126 r u_Axi_CDC/wFifo/reg_datai_32[19]_i_1/I2 SLICE_X82Y126 LUT4 (Prop_lut4_I2_O) 0.048 -0.266 r u_Axi_CDC/wFifo/reg_datai_32[19]_i_1/O net (fo=1, routed) 0.000 -0.266 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[19] SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.461 -0.486 clock pessimism 0.040 -0.446 SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.107 -0.339 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19] ------------------------------------------------------------------- required time 0.339 arrival time -0.266 ------------------------------------------------------------------- slack 0.073 Slack (MET) : 0.073ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.437ns (logic 0.189ns (43.230%) route 0.248ns (56.770%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.257ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.486ns Source Clock Delay (SCD): -0.703ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.145 -0.703 SLICE_X87Y130 FDRE 0.000 -0.703 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 f u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/Q net (fo=21, routed) 0.248 -0.314 u_Axi_CDC/wFifo/Q[27] SLICE_X82Y126 f u_Axi_CDC/wFifo/reg_datai_32[19]_i_1/I2 SLICE_X82Y126 LUT4 (Prop_lut4_I2_O) 0.048 -0.266 f u_Axi_CDC/wFifo/reg_datai_32[19]_i_1/O net (fo=1, routed) 0.000 -0.266 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[19] SLICE_X82Y126 FDRE f u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.461 -0.486 clock pessimism 0.040 -0.446 SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.107 -0.339 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19] ------------------------------------------------------------------- required time 0.339 arrival time -0.266 ------------------------------------------------------------------- slack 0.073 Slack (MET) : 0.074ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[0] SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) 0.070 -0.262 r u_axi_uart_controller/uart0/regs/M_next_carry/O[0] net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] ------------------------------------------------------------------- required time 0.336 arrival time -0.262 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.074ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[16]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[0] SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) 0.070 -0.262 r u_axi_uart_controller/uart0/regs/M_next_carry/O[0] net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] ------------------------------------------------------------------- required time 0.336 arrival time -0.262 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.074ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[0] SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) 0.070 -0.262 r u_axi_uart_controller/uart0/regs/M_next_carry/O[0] net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] ------------------------------------------------------------------- required time 0.336 arrival time -0.262 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.074ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[16]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[0] SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) 0.070 -0.262 r u_axi_uart_controller/uart0/regs/M_next_carry/O[0] net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] ------------------------------------------------------------------- required time 0.336 arrival time -0.262 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.074ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[0] SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) 0.070 -0.262 f u_axi_uart_controller/uart0/regs/M_next_carry/O[0] net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] ------------------------------------------------------------------- required time 0.336 arrival time -0.262 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.074ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[16]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[0] SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) 0.070 -0.262 f u_axi_uart_controller/uart0/regs/M_next_carry/O[0] net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] ------------------------------------------------------------------- required time 0.336 arrival time -0.262 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.074ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[0] SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) 0.070 -0.262 f u_axi_uart_controller/uart0/regs/M_next_carry/O[0] net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] ------------------------------------------------------------------- required time 0.336 arrival time -0.262 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.074ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[16]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[0] SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) 0.070 -0.262 f u_axi_uart_controller/uart0/regs/M_next_carry/O[0] net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] ------------------------------------------------------------------- required time 0.336 arrival time -0.262 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.074ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.425ns (logic 0.209ns (49.172%) route 0.216ns (50.828%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.259ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.486ns Source Clock Delay (SCD): -0.705ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.143 -0.705 SLICE_X84Y128 FDRE 0.000 -0.705 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C SLICE_X84Y128 FDRE (Prop_fdre_C_Q) 0.164 -0.541 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/Q net (fo=23, routed) 0.216 -0.325 u_Axi_CDC/wFifo/Q[19] SLICE_X82Y126 r u_Axi_CDC/wFifo/reg_datai_32[3]_i_1/I3 SLICE_X82Y126 LUT6 (Prop_lut6_I3_O) 0.045 -0.280 r u_Axi_CDC/wFifo/reg_datai_32[3]_i_1/O net (fo=1, routed) 0.000 -0.280 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[3] SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.461 -0.486 clock pessimism 0.040 -0.446 SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.092 -0.354 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3] ------------------------------------------------------------------- required time 0.354 arrival time -0.280 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.074ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.425ns (logic 0.209ns (49.172%) route 0.216ns (50.828%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.259ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.486ns Source Clock Delay (SCD): -0.705ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.143 -0.705 SLICE_X84Y128 FDRE 0.000 -0.705 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C SLICE_X84Y128 FDRE (Prop_fdre_C_Q) 0.164 -0.541 f u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/Q net (fo=23, routed) 0.216 -0.325 u_Axi_CDC/wFifo/Q[19] SLICE_X82Y126 f u_Axi_CDC/wFifo/reg_datai_32[3]_i_1/I3 SLICE_X82Y126 LUT6 (Prop_lut6_I3_O) 0.045 -0.280 f u_Axi_CDC/wFifo/reg_datai_32[3]_i_1/O net (fo=1, routed) 0.000 -0.280 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[3] SLICE_X82Y126 FDRE f u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.461 -0.486 clock pessimism 0.040 -0.446 SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.092 -0.354 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3] ------------------------------------------------------------------- required time 0.354 arrival time -0.280 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.080ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/ier_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.436ns (logic 0.209ns (47.943%) route 0.227ns (52.057%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.476ns Source Clock Delay (SCD): -0.700ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.148 -0.700 SLICE_X84Y133 FDRE 0.000 -0.700 r u_axi_uart_controller/uart0/regs/ier_reg[3]/C SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 r u_axi_uart_controller/uart0/regs/ier_reg[3]/Q net (fo=3, routed) 0.227 -0.309 u_axi_uart_controller/uart0/regs/transmitter/Q[0] SLICE_X83Y135 r u_axi_uart_controller/uart0/regs/transmitter/ms_int_pnd_i_1/I1 SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.264 r u_axi_uart_controller/uart0/regs/transmitter/ms_int_pnd_i_1/O net (fo=1, routed) 0.000 -0.264 u_axi_uart_controller/uart0/regs/transmitter_n_1 SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.471 -0.476 clock pessimism 0.040 -0.436 SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ms_int_pnd_reg ------------------------------------------------------------------- required time 0.344 arrival time -0.264 ------------------------------------------------------------------- slack 0.080 Slack (MET) : 0.080ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/ier_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.436ns (logic 0.209ns (47.943%) route 0.227ns (52.057%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.476ns Source Clock Delay (SCD): -0.700ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.148 -0.700 SLICE_X84Y133 FDRE 0.000 -0.700 r u_axi_uart_controller/uart0/regs/ier_reg[3]/C SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 f u_axi_uart_controller/uart0/regs/ier_reg[3]/Q net (fo=3, routed) 0.227 -0.309 u_axi_uart_controller/uart0/regs/transmitter/Q[0] SLICE_X83Y135 f u_axi_uart_controller/uart0/regs/transmitter/ms_int_pnd_i_1/I1 SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.264 f u_axi_uart_controller/uart0/regs/transmitter/ms_int_pnd_i_1/O net (fo=1, routed) 0.000 -0.264 u_axi_uart_controller/uart0/regs/transmitter_n_1 SLICE_X83Y135 FDRE f u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.471 -0.476 clock pessimism 0.040 -0.436 SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ms_int_pnd_reg ------------------------------------------------------------------- required time 0.344 arrival time -0.264 ------------------------------------------------------------------- slack 0.080 Slack (MET) : 0.081ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.186ns (40.004%) route 0.279ns (59.996%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.705ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.143 -0.705 SLICE_X85Y128 FDRE 0.000 -0.705 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C SLICE_X85Y128 FDRE (Prop_fdre_C_Q) 0.141 -0.564 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/Q net (fo=20, routed) 0.279 -0.285 u_Axi_CDC/wFifo/Q[14] SLICE_X80Y128 r u_Axi_CDC/wFifo/reg_datai_32[14]_i_1/I4 SLICE_X80Y128 LUT5 (Prop_lut5_I4_O) 0.045 -0.240 r u_Axi_CDC/wFifo/reg_datai_32[14]_i_1/O net (fo=1, routed) 0.000 -0.240 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[14] SLICE_X80Y128 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X80Y128 FDRE (Hold_fdre_C_D) 0.120 -0.321 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14] ------------------------------------------------------------------- required time 0.321 arrival time -0.240 ------------------------------------------------------------------- slack 0.081 Slack (MET) : 0.081ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.186ns (40.004%) route 0.279ns (59.996%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.705ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.143 -0.705 SLICE_X85Y128 FDRE 0.000 -0.705 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C SLICE_X85Y128 FDRE (Prop_fdre_C_Q) 0.141 -0.564 f u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/Q net (fo=20, routed) 0.279 -0.285 u_Axi_CDC/wFifo/Q[14] SLICE_X80Y128 f u_Axi_CDC/wFifo/reg_datai_32[14]_i_1/I4 SLICE_X80Y128 LUT5 (Prop_lut5_I4_O) 0.045 -0.240 f u_Axi_CDC/wFifo/reg_datai_32[14]_i_1/O net (fo=1, routed) 0.000 -0.240 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[14] SLICE_X80Y128 FDRE f u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X80Y128 FDRE (Hold_fdre_C_D) 0.120 -0.321 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14] ------------------------------------------------------------------- required time 0.321 arrival time -0.240 ------------------------------------------------------------------- slack 0.081 Slack (MET) : 0.083ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/ier_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.439ns (logic 0.209ns (47.634%) route 0.230ns (52.366%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.476ns Source Clock Delay (SCD): -0.700ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.148 -0.700 SLICE_X84Y133 FDRE 0.000 -0.700 r u_axi_uart_controller/uart0/regs/ier_reg[0]/C SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 r u_axi_uart_controller/uart0/regs/ier_reg[0]/Q net (fo=6, routed) 0.230 -0.306 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/Q[0] SLICE_X83Y135 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/ti_int_pnd_i_1/I1 SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.261 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/ti_int_pnd_i_1/O net (fo=1, routed) 0.000 -0.261 u_axi_uart_controller/uart0/regs/receiver_n_1 SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.471 -0.476 clock pessimism 0.040 -0.436 SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ti_int_pnd_reg ------------------------------------------------------------------- required time 0.344 arrival time -0.261 ------------------------------------------------------------------- slack 0.083 Slack (MET) : 0.083ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/ier_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.439ns (logic 0.209ns (47.634%) route 0.230ns (52.366%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.476ns Source Clock Delay (SCD): -0.700ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.148 -0.700 SLICE_X84Y133 FDRE 0.000 -0.700 r u_axi_uart_controller/uart0/regs/ier_reg[0]/C SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 f u_axi_uart_controller/uart0/regs/ier_reg[0]/Q net (fo=6, routed) 0.230 -0.306 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/Q[0] SLICE_X83Y135 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/ti_int_pnd_i_1/I1 SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.261 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/ti_int_pnd_i_1/O net (fo=1, routed) 0.000 -0.261 u_axi_uart_controller/uart0/regs/receiver_n_1 SLICE_X83Y135 FDRE f u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.471 -0.476 clock pessimism 0.040 -0.436 SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ti_int_pnd_reg ------------------------------------------------------------------- required time 0.344 arrival time -0.261 ------------------------------------------------------------------- slack 0.083 Slack (MET) : 0.084ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.233 -0.615 SLICE_X43Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/Q[7] RAMB18_X2Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.602 -0.346 clock pessimism -0.213 -0.559 RAMB18_X2Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.292 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.233 -0.615 SLICE_X43Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/Q[7] RAMB18_X2Y26 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.602 -0.346 clock pessimism -0.213 -0.559 RAMB18_X2Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.292 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.233 -0.615 SLICE_X43Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/Q[7] RAMB18_X2Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.602 -0.346 clock pessimism -0.213 -0.559 RAMB18_X2Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.292 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.233 -0.615 SLICE_X43Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/Q[7] RAMB18_X2Y27 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.602 -0.346 clock pessimism -0.213 -0.559 RAMB18_X2Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.292 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.403ns (logic 0.164ns (40.684%) route 0.239ns (59.316%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): -0.679ns Clock Pessimism Removal (CPR): -0.045ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 ======= 1.169 -0.679 SLICE_X98Y148 FDRE 0.000 -0.679 r u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C SLICE_X98Y148 FDRE (Prop_fdre_C_Q) 0.164 -0.515 r u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/Q net (fo=2, routed) 0.239 -0.276 u_cpu/wb_stage/ms_to_ws_bus[69] SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ======= 1.490 -0.457 clock pessimism 0.045 -0.412 SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.052 -0.360 u_cpu/wb_stage/ms_to_ws_bus_r_reg[105] ------------------------------------------------------------------- required time 0.360 arrival time -0.276 >>>>>>> Stashed changes ------------------------------------------------------------------- slack 0.084 <<<<<<< Updated upstream Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns ======= Slack (MET) : 0.084ns (arrival time - required time) Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.403ns (logic 0.164ns (40.684%) route 0.239ns (59.316%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): -0.679ns Clock Pessimism Removal (CPR): -0.045ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 ======= 1.169 -0.679 SLICE_X98Y148 FDRE 0.000 -0.679 r u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C SLICE_X98Y148 FDRE (Prop_fdre_C_Q) 0.164 -0.515 f u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/Q net (fo=2, routed) 0.239 -0.276 u_cpu/wb_stage/ms_to_ws_bus[69] SLICE_X100Y150 FDRE f u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ======= 1.490 -0.457 clock pessimism 0.045 -0.412 SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.052 -0.360 u_cpu/wb_stage/ms_to_ws_bus_r_reg[105] ------------------------------------------------------------------- required time 0.360 arrival time -0.276 >>>>>>> Stashed changes ------------------------------------------------------------------- slack 0.084 <<<<<<< Updated upstream Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1 ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1 ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMS32 f u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1 ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMS32 f u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1 ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.097ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.804%) route 0.302ns (68.196%)) Logic Levels: 0 Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.619ns ======= Slack (MET) : 0.085ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.479ns (logic 0.141ns (29.406%) route 0.338ns (70.594%)) Logic Levels: 0 Clock Path Skew: 0.275ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.444ns Source Clock Delay (SCD): -0.674ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.619 SLICE_X157Y150 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C SLICE_X157Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/Q net (fo=14, routed) 0.302 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[13] SLICE_X159Y138 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism 0.045 -0.343 SLICE_X159Y138 FDCE (Hold_fdce_C_D) 0.070 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13] ------------------------------------------------------------------- required time 0.273 arrival time -0.176 ------------------------------------------------------------------- slack 0.097 Slack (MET) : 0.097ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.804%) route 0.302ns (68.196%)) Logic Levels: 0 Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.619ns ======= (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.175 -0.674 SLICE_X115Y150 FDRE 0.000 -0.674 r u_cpu/u_csr/csr_tlbelo1_reg[27]/C SLICE_X115Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q net (fo=4, routed) 0.338 -0.194 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 SLICE_X112Y141 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.503 -0.444 clock pessimism 0.045 -0.399 SLICE_X112Y141 RAMD32 (Hold_ramd32_CLK_I) 0.120 -0.279 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 ------------------------------------------------------------------- required time 0.279 arrival time -0.194 ------------------------------------------------------------------- slack 0.085 Slack (MET) : 0.085ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.479ns (logic 0.141ns (29.406%) route 0.338ns (70.594%)) Logic Levels: 0 Clock Path Skew: 0.275ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.444ns Source Clock Delay (SCD): -0.674ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.619 SLICE_X157Y150 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C SLICE_X157Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/Q net (fo=14, routed) 0.302 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[13] SLICE_X159Y138 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D ======= (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.175 -0.674 SLICE_X115Y150 FDRE 0.000 -0.674 r u_cpu/u_csr/csr_tlbelo1_reg[27]/C SLICE_X115Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/u_csr/csr_tlbelo1_reg[27]/Q net (fo=4, routed) 0.338 -0.194 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 SLICE_X112Y141 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.503 -0.444 clock pessimism 0.045 -0.399 SLICE_X112Y141 RAMD32 (Hold_ramd32_CLK_I) 0.120 -0.279 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 ------------------------------------------------------------------- required time 0.279 arrival time -0.194 ------------------------------------------------------------------- slack 0.085 Slack (MET) : 0.085ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.281ns (logic 0.141ns (50.089%) route 0.140ns (49.911%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.211ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.178 -0.670 SLICE_X133Y115 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/Q net (fo=6, routed) 0.140 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[7] SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.559 -0.388 clock pessimism 0.045 -0.343 SLICE_X159Y138 FDCE (Hold_fdce_C_D) 0.070 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13] ------------------------------------------------------------------- required time 0.273 arrival time -0.176 ------------------------------------------------------------------- slack 0.097 Slack (MET) : 0.098ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns ======= 1.501 -0.446 clock pessimism -0.211 -0.657 SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) 0.183 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.474 arrival time -0.388 ------------------------------------------------------------------- slack 0.085 Slack (MET) : 0.085ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.281ns (logic 0.141ns (50.089%) route 0.140ns (49.911%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.211ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.178 -0.670 SLICE_X133Y115 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/Q net (fo=6, routed) 0.140 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[7] SLICE_X132Y115 SRL16E f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.501 -0.446 clock pessimism -0.211 -0.657 SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) 0.183 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.474 arrival time -0.388 ------------------------------------------------------------------- slack 0.085 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.470 -0.477 clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.434ns (logic 0.186ns (42.838%) route 0.248ns (57.162%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.257ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.486ns Source Clock Delay (SCD): -0.703ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.145 -0.703 SLICE_X87Y130 FDRE 0.000 -0.703 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/Q net (fo=21, routed) 0.248 -0.314 u_Axi_CDC/wFifo/Q[27] SLICE_X82Y126 r u_Axi_CDC/wFifo/reg_datai_32[11]_i_1/I2 SLICE_X82Y126 LUT5 (Prop_lut5_I2_O) 0.045 -0.269 r u_Axi_CDC/wFifo/reg_datai_32[11]_i_1/O net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[11] SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.461 -0.486 clock pessimism 0.040 -0.446 SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.091 -0.355 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11] ------------------------------------------------------------------- required time 0.355 arrival time -0.269 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.434ns (logic 0.186ns (42.838%) route 0.248ns (57.162%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.257ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.486ns Source Clock Delay (SCD): -0.703ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.145 -0.703 SLICE_X87Y130 FDRE 0.000 -0.703 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 f u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/Q net (fo=21, routed) 0.248 -0.314 u_Axi_CDC/wFifo/Q[27] SLICE_X82Y126 f u_Axi_CDC/wFifo/reg_datai_32[11]_i_1/I2 SLICE_X82Y126 LUT5 (Prop_lut5_I2_O) 0.045 -0.269 f u_Axi_CDC/wFifo/reg_datai_32[11]_i_1/O net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[11] SLICE_X82Y126 FDRE f u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.461 -0.486 clock pessimism 0.040 -0.446 SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.091 -0.355 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11] ------------------------------------------------------------------- required time 0.355 arrival time -0.269 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.087ns (arrival time - required time) Source: u_matmul_axi_slave/req_0_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/req_0_reg_rep__0/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.378ns (logic 0.186ns (49.193%) route 0.192ns (50.807%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.241 -0.607 SLICE_X45Y99 FDRE 0.000 -0.607 r u_matmul_axi_slave/req_0_reg/C SLICE_X45Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.466 r u_matmul_axi_slave/req_0_reg/Q net (fo=96, routed) 0.192 -0.274 u_matmul_axi_slave/p_5_in[0] SLICE_X45Y100 r u_matmul_axi_slave/req_0_rep_i_1__0/I4 SLICE_X45Y100 LUT6 (Prop_lut6_I4_O) 0.045 -0.229 r u_matmul_axi_slave/req_0_rep_i_1__0/O net (fo=1, routed) 0.000 -0.229 u_matmul_axi_slave/req_0_rep_i_1__0_n_0 SLICE_X45Y100 FDRE r u_matmul_axi_slave/req_0_reg_rep__0/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.040 -0.408 SLICE_X45Y100 FDRE (Hold_fdre_C_D) 0.092 -0.316 u_matmul_axi_slave/req_0_reg_rep__0 ------------------------------------------------------------------- required time 0.316 arrival time -0.229 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_matmul_axi_slave/req_0_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/req_0_reg_rep__0/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.378ns (logic 0.186ns (49.193%) route 0.192ns (50.807%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.241 -0.607 SLICE_X45Y99 FDRE 0.000 -0.607 r u_matmul_axi_slave/req_0_reg/C SLICE_X45Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.466 f u_matmul_axi_slave/req_0_reg/Q net (fo=96, routed) 0.192 -0.274 u_matmul_axi_slave/p_5_in[0] SLICE_X45Y100 f u_matmul_axi_slave/req_0_rep_i_1__0/I4 SLICE_X45Y100 LUT6 (Prop_lut6_I4_O) 0.045 -0.229 f u_matmul_axi_slave/req_0_rep_i_1__0/O net (fo=1, routed) 0.000 -0.229 u_matmul_axi_slave/req_0_rep_i_1__0_n_0 SLICE_X45Y100 FDRE f u_matmul_axi_slave/req_0_reg_rep__0/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.040 -0.408 SLICE_X45Y100 FDRE (Hold_fdre_C_D) 0.092 -0.316 u_matmul_axi_slave/req_0_reg_rep__0 ------------------------------------------------------------------- required time 0.316 arrival time -0.229 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/enable_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.186ns (42.057%) route 0.256ns (57.943%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.478ns >>>>>>> Stashed changes Source Clock Delay (SCD): -0.701ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.148 -0.701 SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 SLICE_X87Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/I3 SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/O net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1_n_0 SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D ======= 1.147 -0.701 SLICE_X86Y132 FDRE 0.000 -0.701 r u_axi_uart_controller/uart0/regs/enable_reg/C SLICE_X86Y132 FDRE (Prop_fdre_C_Q) 0.141 -0.560 r u_axi_uart_controller/uart0/regs/enable_reg/Q net (fo=12, routed) 0.256 -0.304 u_axi_uart_controller/uart0/regs/enable SLICE_X83Y133 r u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/I1 SLICE_X83Y133 LUT4 (Prop_lut4_I1_O) 0.045 -0.259 r u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/O net (fo=1, routed) 0.000 -0.259 u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1_n_0 SLICE_X83Y133 FDRE r u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.472 -0.475 clock pessimism 0.040 -0.435 SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.092 -0.343 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4] ------------------------------------------------------------------- required time 0.343 arrival time -0.245 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns ======= 1.469 -0.478 clock pessimism 0.040 -0.438 SLICE_X83Y133 FDRE (Hold_fdre_C_D) 0.092 -0.346 u_axi_uart_controller/uart0/regs/sclk_en_reg_reg ------------------------------------------------------------------- required time 0.346 arrival time -0.259 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/enable_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.186ns (42.057%) route 0.256ns (57.943%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.478ns >>>>>>> Stashed changes Source Clock Delay (SCD): -0.701ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.148 -0.701 SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 SLICE_X87Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/I3 SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/O net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1_n_0 SLICE_X87Y152 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D ======= 1.147 -0.701 SLICE_X86Y132 FDRE 0.000 -0.701 r u_axi_uart_controller/uart0/regs/enable_reg/C SLICE_X86Y132 FDRE (Prop_fdre_C_Q) 0.141 -0.560 f u_axi_uart_controller/uart0/regs/enable_reg/Q net (fo=12, routed) 0.256 -0.304 u_axi_uart_controller/uart0/regs/enable SLICE_X83Y133 f u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/I1 SLICE_X83Y133 LUT4 (Prop_lut4_I1_O) 0.045 -0.259 r u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/O net (fo=1, routed) 0.000 -0.259 u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1_n_0 SLICE_X83Y133 FDRE r u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.472 -0.475 clock pessimism 0.040 -0.435 SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.092 -0.343 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4] ------------------------------------------------------------------- required time 0.343 arrival time -0.245 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.099ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns ======= 1.469 -0.478 clock pessimism 0.040 -0.438 SLICE_X83Y133 FDRE (Hold_fdre_C_D) 0.092 -0.346 u_axi_uart_controller/uart0/regs/sclk_en_reg_reg ------------------------------------------------------------------- required time 0.346 arrival time -0.259 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/enable_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.186ns (42.057%) route 0.256ns (57.943%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.478ns >>>>>>> Stashed changes Source Clock Delay (SCD): -0.701ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.148 -0.701 SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 SLICE_X87Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/I3 SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/O net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1_n_0 SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D ======= 1.147 -0.701 SLICE_X86Y132 FDRE 0.000 -0.701 r u_axi_uart_controller/uart0/regs/enable_reg/C SLICE_X86Y132 FDRE (Prop_fdre_C_Q) 0.141 -0.560 r u_axi_uart_controller/uart0/regs/enable_reg/Q net (fo=12, routed) 0.256 -0.304 u_axi_uart_controller/uart0/regs/enable SLICE_X83Y133 r u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/I1 SLICE_X83Y133 LUT4 (Prop_lut4_I1_O) 0.045 -0.259 f u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/O net (fo=1, routed) 0.000 -0.259 u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1_n_0 SLICE_X83Y133 FDRE f u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.472 -0.475 clock pessimism 0.040 -0.435 SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.091 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3] ------------------------------------------------------------------- required time 0.344 arrival time -0.245 ------------------------------------------------------------------- slack 0.099 Slack (MET) : 0.099ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns ======= 1.469 -0.478 clock pessimism 0.040 -0.438 SLICE_X83Y133 FDRE (Hold_fdre_C_D) 0.092 -0.346 u_axi_uart_controller/uart0/regs/sclk_en_reg_reg ------------------------------------------------------------------- required time 0.346 arrival time -0.259 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/enable_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.186ns (42.057%) route 0.256ns (57.943%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.478ns >>>>>>> Stashed changes Source Clock Delay (SCD): -0.701ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.148 -0.701 SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 SLICE_X87Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/I3 SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/O net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1_n_0 SLICE_X87Y152 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D ======= 1.147 -0.701 SLICE_X86Y132 FDRE 0.000 -0.701 r u_axi_uart_controller/uart0/regs/enable_reg/C SLICE_X86Y132 FDRE (Prop_fdre_C_Q) 0.141 -0.560 f u_axi_uart_controller/uart0/regs/enable_reg/Q net (fo=12, routed) 0.256 -0.304 u_axi_uart_controller/uart0/regs/enable SLICE_X83Y133 f u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/I1 SLICE_X83Y133 LUT4 (Prop_lut4_I1_O) 0.045 -0.259 f u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/O net (fo=1, routed) 0.000 -0.259 u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1_n_0 SLICE_X83Y133 FDRE f u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.472 -0.475 clock pessimism 0.040 -0.435 SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.091 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3] ------------------------------------------------------------------- required time 0.344 arrival time -0.245 ------------------------------------------------------------------- slack 0.099 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.366ns (logic 0.164ns (44.815%) route 0.202ns (55.185%)) Logic Levels: 0 Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.506ns Clock Pessimism Removal (CPR): -0.037ns ======= 1.469 -0.478 clock pessimism 0.040 -0.438 SLICE_X83Y133 FDRE (Hold_fdre_C_D) 0.092 -0.346 u_axi_uart_controller/uart0/regs/sclk_en_reg_reg ------------------------------------------------------------------- required time 0.346 arrival time -0.259 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.089ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[5] RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.374 clock pessimism 0.040 -0.333 RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.061 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.089ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[5] RAMB18_X7Y40 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.374 clock pessimism 0.040 -0.333 RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.061 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.089ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[5] RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.374 clock pessimism 0.040 -0.333 RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.061 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.089ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[5] RAMB18_X7Y41 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.374 clock pessimism 0.040 -0.333 RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.061 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.089ns (arrival time - required time) Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.415ns (logic 0.141ns (33.953%) route 0.274ns (66.047%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): -0.679ns Clock Pessimism Removal (CPR): -0.045ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.343 -0.506 SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 r u_cpu/u_csr/csr_tlbidx_reg[26]/Q net (fo=33, routed) 0.202 -0.140 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] SLICE_X37Y51 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D ======= 1.169 -0.679 SLICE_X97Y148 FDRE 0.000 -0.679 r u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C SLICE_X97Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.538 r u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/Q net (fo=2, routed) 0.274 -0.264 u_cpu/wb_stage/ms_to_ws_bus[68] SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.601 -0.346 clock pessimism 0.037 -0.309 SLICE_X37Y51 FDRE (Hold_fdre_C_D) 0.070 -0.239 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2] ------------------------------------------------------------------- required time 0.239 arrival time -0.140 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.366ns (logic 0.164ns (44.815%) route 0.202ns (55.185%)) Logic Levels: 0 Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.506ns Clock Pessimism Removal (CPR): -0.037ns ======= 1.490 -0.457 clock pessimism 0.045 -0.412 SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.059 -0.353 u_cpu/wb_stage/ms_to_ws_bus_r_reg[104] ------------------------------------------------------------------- required time 0.353 arrival time -0.264 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.089ns (arrival time - required time) Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.415ns (logic 0.141ns (33.953%) route 0.274ns (66.047%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): -0.679ns Clock Pessimism Removal (CPR): -0.045ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.343 -0.506 SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 f u_cpu/u_csr/csr_tlbidx_reg[26]/Q net (fo=33, routed) 0.202 -0.140 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] SLICE_X37Y51 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D ======= 1.169 -0.679 SLICE_X97Y148 FDRE 0.000 -0.679 r u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C SLICE_X97Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.538 f u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/Q net (fo=2, routed) 0.274 -0.264 u_cpu/wb_stage/ms_to_ws_bus[68] SLICE_X100Y150 FDRE f u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.601 -0.346 clock pessimism 0.037 -0.309 SLICE_X37Y51 FDRE (Hold_fdre_C_D) 0.070 -0.239 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2] ------------------------------------------------------------------- required time 0.239 arrival time -0.140 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns ======= 1.490 -0.457 clock pessimism 0.045 -0.412 SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.059 -0.353 u_cpu/wb_stage/ms_to_ws_bus_r_reg[104] ------------------------------------------------------------------- required time 0.353 arrival time -0.264 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.091ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.443ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.179 -0.669 SLICE_X109Y149 FDRE 0.000 -0.669 r u_cpu/u_csr/csr_tlbelo0_reg[5]/C SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 r u_cpu/u_csr/csr_tlbelo0_reg[5]/Q net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.504 -0.443 clock pessimism -0.213 -0.656 SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) 0.117 -0.539 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP ------------------------------------------------------------------- required time 0.539 arrival time -0.448 ------------------------------------------------------------------- slack 0.091 Slack (MET) : 0.091ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.443ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.179 -0.669 SLICE_X109Y149 FDRE 0.000 -0.669 r u_cpu/u_csr/csr_tlbelo0_reg[5]/C SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 f u_cpu/u_csr/csr_tlbelo0_reg[5]/Q net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D SLICE_X108Y149 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.504 -0.443 clock pessimism -0.213 -0.656 SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) 0.117 -0.539 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP ------------------------------------------------------------------- required time 0.539 arrival time -0.448 ------------------------------------------------------------------- slack 0.091 Slack (MET) : 0.093ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.809ns (logic 0.367ns (45.351%) route 0.442ns (54.649%)) Logic Levels: 0 Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.499ns Source Clock Delay (SCD): -2.113ns Clock Pessimism Removal (CPR): -0.407ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -5.674 -5.674 propagated clock network latency 3.561 -2.113 SLICE_X57Y90 FDCE 0.000 -2.113 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.442 -1.304 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.777 -2.499 clock pessimism 0.407 -2.091 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.694 -1.397 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 1.397 arrival time -1.304 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.093ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.809ns (logic 0.367ns (45.351%) route 0.442ns (54.649%)) Logic Levels: 0 Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.499ns Source Clock Delay (SCD): -2.113ns Clock Pessimism Removal (CPR): -0.407ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -5.674 -5.674 propagated clock network latency 3.561 -2.113 SLICE_X57Y90 FDCE 0.000 -2.113 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.442 -1.304 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X56Y90 RAMD32 f axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.777 -2.499 clock pessimism 0.407 -2.091 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.694 -1.397 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 1.397 arrival time -1.304 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.093ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.809ns (logic 0.367ns (45.351%) route 0.442ns (54.649%)) Logic Levels: 0 Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.499ns Source Clock Delay (SCD): -2.113ns Clock Pessimism Removal (CPR): -0.407ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -5.674 -5.674 propagated clock network latency 3.561 -2.113 SLICE_X57Y90 FDCE 0.000 -2.113 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.442 -1.304 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.777 -2.499 clock pessimism 0.407 -2.091 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.694 -1.397 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 1.397 arrival time -1.304 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.093ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.809ns (logic 0.367ns (45.351%) route 0.442ns (54.649%)) Logic Levels: 0 Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.499ns Source Clock Delay (SCD): -2.113ns Clock Pessimism Removal (CPR): -0.407ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -5.674 -5.674 propagated clock network latency 3.561 -2.113 SLICE_X57Y90 FDCE 0.000 -2.113 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.442 -1.304 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X56Y90 RAMD32 f axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.777 -2.499 clock pessimism 0.407 -2.091 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.694 -1.397 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 1.397 arrival time -1.304 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_csr/csr_cntc_reg[1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.802%) route 0.302ns (68.198%)) Logic Levels: 0 Clock Path Skew: 0.278ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.684ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.165 -0.684 SLICE_X101Y154 FDRE 0.000 -0.684 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/C SLICE_X101Y154 FDRE (Prop_fdre_C_Q) 0.141 -0.543 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/Q net (fo=21, routed) 0.302 -0.241 u_cpu/u_csr/wr_csr_data[1] SLICE_X101Y149 FDRE r u_cpu/u_csr/csr_cntc_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism 0.045 -0.406 SLICE_X101Y149 FDRE (Hold_fdre_C_D) 0.070 -0.336 u_cpu/u_csr/csr_cntc_reg[1] ------------------------------------------------------------------- required time 0.336 arrival time -0.241 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_csr/csr_cntc_reg[1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.802%) route 0.302ns (68.198%)) Logic Levels: 0 Clock Path Skew: 0.278ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.684ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.165 -0.684 SLICE_X101Y154 FDRE 0.000 -0.684 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/C SLICE_X101Y154 FDRE (Prop_fdre_C_Q) 0.141 -0.543 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/Q net (fo=21, routed) 0.302 -0.241 u_cpu/u_csr/wr_csr_data[1] SLICE_X101Y149 FDRE f u_cpu/u_csr/csr_cntc_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism 0.045 -0.406 SLICE_X101Y149 FDRE (Hold_fdre_C_D) 0.070 -0.336 u_cpu/u_csr/csr_cntc_reg[1] ------------------------------------------------------------------- required time 0.336 arrival time -0.241 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.096ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.281ns (logic 0.141ns (50.221%) route 0.140ns (49.779%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.447ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.175 -0.674 SLICE_X115Y150 FDRE 0.000 -0.674 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C SLICE_X115Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q net (fo=4, routed) 0.140 -0.393 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/DIA0 SLICE_X116Y151 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.500 -0.447 clock pessimism -0.189 -0.636 SLICE_X116Y151 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.489 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA ------------------------------------------------------------------- required time 0.489 arrival time -0.393 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.281ns (logic 0.141ns (50.221%) route 0.140ns (49.779%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.447ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.175 -0.674 SLICE_X115Y150 FDRE 0.000 -0.674 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C SLICE_X115Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/u_csr/csr_tlbelo1_reg[26]/Q net (fo=4, routed) 0.140 -0.393 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/DIA0 SLICE_X116Y151 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.500 -0.447 clock pessimism -0.189 -0.636 SLICE_X116Y151 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.489 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA ------------------------------------------------------------------- required time 0.489 arrival time -0.393 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.258ns (logic 0.141ns (54.698%) route 0.117ns (45.302%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.671ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.177 -0.671 SLICE_X106Y147 FDRE 0.000 -0.671 r u_cpu/u_csr/csr_tlbelo1_reg[2]/C SLICE_X106Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.530 r u_cpu/u_csr/csr_tlbelo1_reg[2]/Q net (fo=7, routed) 0.117 -0.413 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/D SLICE_X104Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.502 -0.445 clock pessimism -0.210 -0.655 SLICE_X104Y147 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.509 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP ------------------------------------------------------------------- required time 0.509 arrival time -0.413 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.258ns (logic 0.141ns (54.698%) route 0.117ns (45.302%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.671ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.177 -0.671 SLICE_X106Y147 FDRE 0.000 -0.671 r u_cpu/u_csr/csr_tlbelo1_reg[2]/C SLICE_X106Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.530 f u_cpu/u_csr/csr_tlbelo1_reg[2]/Q net (fo=7, routed) 0.117 -0.413 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/D SLICE_X104Y147 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.502 -0.445 clock pessimism -0.210 -0.655 SLICE_X104Y147 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.509 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP ------------------------------------------------------------------- required time 0.509 arrival time -0.413 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[18]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.256ns (logic 0.141ns (55.072%) route 0.115ns (44.928%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.181 -0.667 SLICE_X118Y147 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo1_reg[18]/C SLICE_X118Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[18]/Q net (fo=4, routed) 0.115 -0.411 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIC0 SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.506 -0.441 clock pessimism -0.210 -0.651 SLICE_X116Y147 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC ------------------------------------------------------------------- required time 0.507 arrival time -0.411 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[18]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.256ns (logic 0.141ns (55.072%) route 0.115ns (44.928%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.181 -0.667 SLICE_X118Y147 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo1_reg[18]/C SLICE_X118Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.526 f u_cpu/u_csr/csr_tlbelo1_reg[18]/Q net (fo=4, routed) 0.115 -0.411 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIC0 SLICE_X116Y147 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.506 -0.441 clock pessimism -0.210 -0.651 SLICE_X116Y147 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC ------------------------------------------------------------------- required time 0.507 arrival time -0.411 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.238 -0.610 SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.128 -0.482 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.236 -0.246 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.216 -0.597 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR1) 0.255 -0.342 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.342 arrival time -0.246 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.238 -0.610 SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.128 -0.482 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.236 -0.246 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X56Y90 RAMD32 f axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.216 -0.597 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR1) 0.255 -0.342 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.342 arrival time -0.246 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.238 -0.610 SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.128 -0.482 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.236 -0.246 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.216 -0.597 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR1) 0.255 -0.342 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.342 arrival time -0.246 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.238 -0.610 SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.128 -0.482 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.236 -0.246 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X56Y90 RAMD32 f axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.216 -0.597 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR1) 0.255 -0.342 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.342 arrival time -0.246 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[24]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.258ns (logic 0.141ns (54.609%) route 0.117ns (45.391%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.442ns Source Clock Delay (SCD): -0.668ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 ======= 1.180 -0.668 SLICE_X114Y149 FDRE 0.000 -0.668 r u_cpu/u_csr/csr_tlbelo0_reg[24]/C SLICE_X114Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.527 r u_cpu/u_csr/csr_tlbelo0_reg[24]/Q net (fo=4, routed) 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIC0 SLICE_X112Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC/I >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns ======= 1.505 -0.442 clock pessimism -0.210 -0.652 SLICE_X112Y149 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.508 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC ------------------------------------------------------------------- required time 0.508 arrival time -0.410 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[24]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.258ns (logic 0.141ns (54.609%) route 0.117ns (45.391%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.442ns Source Clock Delay (SCD): -0.668ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 ======= 1.180 -0.668 SLICE_X114Y149 FDRE 0.000 -0.668 r u_cpu/u_csr/csr_tlbelo0_reg[24]/C SLICE_X114Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.527 f u_cpu/u_csr/csr_tlbelo0_reg[24]/Q net (fo=4, routed) 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIC0 SLICE_X112Y149 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC/I >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.332 -0.517 SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.660 -0.287 clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.101ns (arrival time - required time) Source: u_matmul_axi_slave/m_in_a_reg[1][28]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D ======= 1.505 -0.442 clock pessimism -0.210 -0.652 SLICE_X112Y149 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.508 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC ------------------------------------------------------------------- required time 0.508 arrival time -0.410 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.100ns (arrival time - required time) Source: u_matmul_axi_slave/m_in_a_reg[1][14]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14]/D >>>>>>> Stashed changes (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.496ns (logic 0.164ns (33.088%) route 0.332ns (66.911%)) Logic Levels: 0 Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.675ns ======= Data Path Delay: 0.368ns (logic 0.141ns (38.301%) route 0.227ns (61.699%)) Logic Levels: 0 Clock Path Skew: 0.198ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.411ns Source Clock Delay (SCD): -0.569ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.173 -0.675 SLICE_X44Y105 FDRE 0.000 -0.675 r u_matmul_axi_slave/m_in_a_reg[1][28]/C SLICE_X44Y105 FDRE (Prop_fdre_C_Q) 0.164 -0.511 r u_matmul_axi_slave/m_in_a_reg[1][28]/Q net (fo=1, routed) 0.332 -0.179 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[28] SLICE_X56Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D ======= 1.279 -0.569 SLICE_X23Y99 FDRE 0.000 -0.569 r u_matmul_axi_slave/m_in_a_reg[1][14]/C SLICE_X23Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.428 r u_matmul_axi_slave/m_in_a_reg[1][14]/Q net (fo=1, routed) 0.227 -0.201 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[14] SLICE_X23Y107 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X56Y98 FDRE (Hold_fdre_C_D) 0.059 -0.280 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28] ------------------------------------------------------------------- required time 0.280 arrival time -0.179 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_matmul_axi_slave/m_in_a_reg[1][28]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D ======= 1.536 -0.411 clock pessimism 0.040 -0.371 SLICE_X23Y107 FDRE (Hold_fdre_C_D) 0.070 -0.301 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14] ------------------------------------------------------------------- required time 0.301 arrival time -0.201 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_matmul_axi_slave/m_in_a_reg[1][14]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14]/D >>>>>>> Stashed changes (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.496ns (logic 0.164ns (33.088%) route 0.332ns (66.911%)) Logic Levels: 0 Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.675ns Clock Pessimism Removal (CPR): -0.040ns ======= Data Path Delay: 0.368ns (logic 0.141ns (38.301%) route 0.227ns (61.699%)) Logic Levels: 0 Clock Path Skew: 0.198ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.411ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X23Y99 FDRE 0.000 -0.569 r u_matmul_axi_slave/m_in_a_reg[1][14]/C SLICE_X23Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.428 f u_matmul_axi_slave/m_in_a_reg[1][14]/Q net (fo=1, routed) 0.227 -0.201 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[14] SLICE_X23Y107 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.536 -0.411 clock pessimism 0.040 -0.371 SLICE_X23Y107 FDRE (Hold_fdre_C_D) 0.070 -0.301 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14] ------------------------------------------------------------------- required time 0.301 arrival time -0.201 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.453ns (logic 0.186ns (41.032%) route 0.267ns (58.968%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.262ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.480ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X87Y131 FDRE 0.000 -0.702 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C SLICE_X87Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/Q net (fo=20, routed) 0.267 -0.294 u_Axi_CDC/wFifo/Q[6] SLICE_X81Y129 r u_Axi_CDC/wFifo/reg_datai_32[6]_i_1/I5 SLICE_X81Y129 LUT6 (Prop_lut6_I5_O) 0.045 -0.249 r u_Axi_CDC/wFifo/reg_datai_32[6]_i_1/O net (fo=1, routed) 0.000 -0.249 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[6] SLICE_X81Y129 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.467 -0.480 clock pessimism 0.040 -0.440 SLICE_X81Y129 FDRE (Hold_fdre_C_D) 0.091 -0.349 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6] ------------------------------------------------------------------- required time 0.349 arrival time -0.249 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.453ns (logic 0.186ns (41.032%) route 0.267ns (58.968%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.262ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.480ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.146 -0.702 SLICE_X87Y131 FDRE 0.000 -0.702 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C SLICE_X87Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/Q net (fo=20, routed) 0.267 -0.294 u_Axi_CDC/wFifo/Q[6] SLICE_X81Y129 f u_Axi_CDC/wFifo/reg_datai_32[6]_i_1/I5 SLICE_X81Y129 LUT6 (Prop_lut6_I5_O) 0.045 -0.249 f u_Axi_CDC/wFifo/reg_datai_32[6]_i_1/O net (fo=1, routed) 0.000 -0.249 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[6] SLICE_X81Y129 FDRE f u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.467 -0.480 clock pessimism 0.040 -0.440 SLICE_X81Y129 FDRE (Hold_fdre_C_D) 0.091 -0.349 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6] ------------------------------------------------------------------- required time 0.349 arrival time -0.249 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.102ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.455ns (logic 0.186ns (40.841%) route 0.269ns (59.159%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.482ns Source Clock Delay (SCD): -0.703ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.145 -0.703 SLICE_X86Y130 FDRE 0.000 -0.703 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C SLICE_X86Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/Q net (fo=20, routed) 0.269 -0.293 u_Axi_CDC/wFifo/Q[0] SLICE_X79Y127 r u_Axi_CDC/wFifo/reg_datai_32[0]_i_1/I5 SLICE_X79Y127 LUT6 (Prop_lut6_I5_O) 0.045 -0.248 r u_Axi_CDC/wFifo/reg_datai_32[0]_i_1/O net (fo=1, routed) 0.000 -0.248 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[0] SLICE_X79Y127 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.465 -0.482 clock pessimism 0.040 -0.442 SLICE_X79Y127 FDRE (Hold_fdre_C_D) 0.092 -0.350 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0] ------------------------------------------------------------------- required time 0.350 arrival time -0.248 ------------------------------------------------------------------- slack 0.102 Slack (MET) : 0.102ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.455ns (logic 0.186ns (40.841%) route 0.269ns (59.159%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.482ns Source Clock Delay (SCD): -0.703ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.145 -0.703 SLICE_X86Y130 FDRE 0.000 -0.703 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C SLICE_X86Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 f u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/Q net (fo=20, routed) 0.269 -0.293 u_Axi_CDC/wFifo/Q[0] SLICE_X79Y127 f u_Axi_CDC/wFifo/reg_datai_32[0]_i_1/I5 SLICE_X79Y127 LUT6 (Prop_lut6_I5_O) 0.045 -0.248 f u_Axi_CDC/wFifo/reg_datai_32[0]_i_1/O net (fo=1, routed) 0.000 -0.248 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[0] SLICE_X79Y127 FDRE f u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.465 -0.482 clock pessimism 0.040 -0.442 SLICE_X79Y127 FDRE (Hold_fdre_C_D) 0.092 -0.350 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0] ------------------------------------------------------------------- required time 0.350 arrival time -0.248 ------------------------------------------------------------------- slack 0.102 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMA ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 f u_cpu/btb/ras_reg_0_7_12_17/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMA ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1 ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 f u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1 ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMB ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 f u_cpu/btb/ras_reg_0_7_12_17/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMB ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1 ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 f u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1 ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMC ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 f u_cpu/btb/ras_reg_0_7_12_17/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMC ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1 ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 f u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1 ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMS32 r u_cpu/btb/ras_reg_0_7_12_17/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMD ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMS32 f u_cpu/btb/ras_reg_0_7_12_17/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMD ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMS32 r u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1 ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMS32 f u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.496 -0.451 clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1 ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.233ns (logic 0.141ns (60.420%) route 0.092ns (39.580%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.211ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.178 -0.670 SLICE_X133Y115 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/Q net (fo=7, routed) 0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[2] SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.501 -0.446 clock pessimism -0.211 -0.657 SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) 0.117 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.540 arrival time -0.437 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.233ns (logic 0.141ns (60.420%) route 0.092ns (39.580%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.211ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.173 -0.675 SLICE_X44Y105 FDRE 0.000 -0.675 r u_matmul_axi_slave/m_in_a_reg[1][28]/C SLICE_X44Y105 FDRE (Prop_fdre_C_Q) 0.164 -0.511 f u_matmul_axi_slave/m_in_a_reg[1][28]/Q net (fo=1, routed) 0.332 -0.179 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[28] SLICE_X56Y98 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D ======= 1.178 -0.670 SLICE_X133Y115 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/Q net (fo=7, routed) 0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[2] SLICE_X132Y115 SRL16E f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X56Y98 FDRE (Hold_fdre_C_D) 0.059 -0.280 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28] ------------------------------------------------------------------- required time 0.280 arrival time -0.179 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[4]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.286ns (logic 0.141ns (49.244%) route 0.145ns (50.756%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.537ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.312 -0.537 SLICE_X50Y43 FDRE 0.000 -0.537 r u_cpu/u_csr/csr_tlbelo0_reg[4]/C SLICE_X50Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_cpu/u_csr/csr_tlbelo0_reg[4]/Q net (fo=7, routed) 0.145 -0.250 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/D SLICE_X48Y43 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.643 -0.304 clock pessimism -0.196 -0.500 SLICE_X48Y43 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.354 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP ------------------------------------------------------------------- required time 0.354 arrival time -0.250 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[4]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.286ns (logic 0.141ns (49.244%) route 0.145ns (50.756%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.537ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.312 -0.537 SLICE_X50Y43 FDRE 0.000 -0.537 r u_cpu/u_csr/csr_tlbelo0_reg[4]/C SLICE_X50Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.396 f u_cpu/u_csr/csr_tlbelo0_reg[4]/Q net (fo=7, routed) 0.145 -0.250 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/D SLICE_X48Y43 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.643 -0.304 clock pessimism -0.196 -0.500 SLICE_X48Y43 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.354 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP ------------------------------------------------------------------- required time 0.354 arrival time -0.250 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/axi_bridge/araddr_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.141ns (31.876%) route 0.301ns (68.124%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.313 -0.536 SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[10]/C SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_cpu/axi_bridge/araddr_reg[10]/Q net (fo=1, routed) 0.301 -0.093 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC0 SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.569 -0.378 clock pessimism 0.037 -0.341 SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.197 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- required time 0.197 arrival time -0.093 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/axi_bridge/araddr_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.141ns (31.876%) route 0.301ns (68.124%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.313 -0.536 SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[10]/C SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.395 f u_cpu/axi_bridge/araddr_reg[10]/Q net (fo=1, routed) 0.301 -0.093 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC0 SLICE_X44Y52 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.569 -0.378 clock pessimism 0.037 -0.341 SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.197 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- required time 0.197 arrival time -0.093 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.451ns (logic 0.141ns (31.244%) route 0.310ns (68.756%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.619 SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/Q net (fo=15, routed) 0.310 -0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[18] SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.045 -0.342 SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.070 -0.272 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18] ------------------------------------------------------------------- required time 0.272 arrival time -0.168 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.451ns (logic 0.141ns (31.244%) route 0.310ns (68.756%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.619 SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/Q net (fo=15, routed) 0.310 -0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[18] SLICE_X159Y140 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.045 -0.342 SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.070 -0.272 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18] ------------------------------------------------------------------- required time 0.272 arrival time -0.168 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.233 -0.615 SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[4] RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.601 -0.347 clock pessimism -0.212 -0.559 RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.270 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.233 -0.615 SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[4] RAMB18_X6Y27 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.601 -0.347 clock pessimism -0.212 -0.559 RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.270 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.233 -0.615 SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[4] RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.601 -0.347 clock pessimism -0.212 -0.559 RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.270 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.233 -0.615 SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[4] RAMB18_X6Y26 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.601 -0.347 clock pessimism -0.212 -0.559 RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.270 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.449ns (logic 0.141ns (31.381%) route 0.308ns (68.619%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.619 SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/Q net (fo=15, routed) 0.308 -0.170 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[17] SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.045 -0.342 SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.066 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17] ------------------------------------------------------------------- required time 0.276 arrival time -0.170 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.449ns (logic 0.141ns (31.381%) route 0.308ns (68.619%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.619 SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/Q net (fo=15, routed) 0.308 -0.170 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[17] SLICE_X159Y140 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.045 -0.342 SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.066 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17] ------------------------------------------------------------------- required time 0.276 arrival time -0.170 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.108ns (arrival time - required time) Source: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/buf_addr_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.425ns (logic 0.186ns (43.780%) route 0.239ns (56.220%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.336ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X13Y45 FDRE 0.000 -0.495 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.354 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/Q net (fo=13, routed) 0.239 -0.115 u_Axi_CDC/arFifo/_zz_ram_port1[2] SLICE_X16Y51 r u_Axi_CDC/arFifo/buf_addr[2]_i_1/I1 SLICE_X16Y51 LUT5 (Prop_lut5_I1_O) 0.045 -0.070 r u_Axi_CDC/arFifo/buf_addr[2]_i_1/O net (fo=1, routed) 0.000 -0.070 u_confreg/buf_addr_reg[15]_0[2] SLICE_X16Y51 FDRE r u_confreg/buf_addr_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.611 -0.336 clock pessimism 0.037 -0.299 SLICE_X16Y51 FDRE (Hold_fdre_C_D) 0.121 -0.178 u_confreg/buf_addr_reg[2] ------------------------------------------------------------------- required time 0.178 arrival time -0.070 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/buf_addr_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.425ns (logic 0.186ns (43.780%) route 0.239ns (56.220%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.336ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X13Y45 FDRE 0.000 -0.495 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.354 f u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/Q net (fo=13, routed) 0.239 -0.115 u_Axi_CDC/arFifo/_zz_ram_port1[2] SLICE_X16Y51 f u_Axi_CDC/arFifo/buf_addr[2]_i_1/I1 SLICE_X16Y51 LUT5 (Prop_lut5_I1_O) 0.045 -0.070 f u_Axi_CDC/arFifo/buf_addr[2]_i_1/O net (fo=1, routed) 0.000 -0.070 u_confreg/buf_addr_reg[15]_0[2] SLICE_X16Y51 FDRE f u_confreg/buf_addr_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.611 -0.336 clock pessimism 0.037 -0.299 SLICE_X16Y51 FDRE (Hold_fdre_C_D) 0.121 -0.178 u_confreg/buf_addr_reg[2] ------------------------------------------------------------------- required time 0.178 arrival time -0.070 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.111ns (arrival time - required time) Source: u_confreg/digital_data_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.353ns (logic 0.141ns (39.954%) route 0.212ns (60.046%)) Logic Levels: 0 Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.384 -0.465 SLICE_X0Y49 FDRE 0.000 -0.465 r u_confreg/digital_data_reg[1]/C SLICE_X0Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.324 r u_confreg/digital_data_reg[1]/Q net (fo=2, routed) 0.212 -0.112 u_confreg/u_digitaltube_controller/dpy1_data_reg[3]_0[1] SLICE_X0Y54 FDRE r u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism 0.037 -0.269 SLICE_X0Y54 FDRE (Hold_fdre_C_D) 0.047 -0.222 u_confreg/u_digitaltube_controller/dpy0_data_reg[1] ------------------------------------------------------------------- required time 0.222 arrival time -0.112 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_confreg/digital_data_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.353ns (logic 0.141ns (39.954%) route 0.212ns (60.046%)) Logic Levels: 0 Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.384 -0.465 SLICE_X0Y49 FDRE 0.000 -0.465 r u_confreg/digital_data_reg[1]/C SLICE_X0Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.324 f u_confreg/digital_data_reg[1]/Q net (fo=2, routed) 0.212 -0.112 u_confreg/u_digitaltube_controller/dpy1_data_reg[3]_0[1] SLICE_X0Y54 FDRE f u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.641 -0.306 clock pessimism 0.037 -0.269 SLICE_X0Y54 FDRE (Hold_fdre_C_D) 0.047 -0.222 u_confreg/u_digitaltube_controller/dpy0_data_reg[1] ------------------------------------------------------------------- required time 0.222 arrival time -0.112 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.410ns (logic 0.209ns (50.949%) route 0.201ns (49.051%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.192ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.371ns Source Clock Delay (SCD): -0.527ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.322 -0.527 SLICE_X116Y49 FDRE 0.000 -0.527 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C SLICE_X116Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.363 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/Q net (fo=5, routed) 0.201 -0.162 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[3] SLICE_X118Y50 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/I2 SLICE_X118Y50 LUT3 (Prop_lut3_I2_O) 0.045 -0.117 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/O net (fo=1, routed) 0.000 -0.117 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[3] SLICE_X118Y50 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.576 -0.371 clock pessimism 0.037 -0.334 SLICE_X118Y50 FDRE (Hold_fdre_C_D) 0.107 -0.227 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3] ------------------------------------------------------------------- required time 0.227 arrival time -0.117 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.410ns (logic 0.209ns (50.949%) route 0.201ns (49.051%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.192ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.371ns Source Clock Delay (SCD): -0.527ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.322 -0.527 SLICE_X116Y49 FDRE 0.000 -0.527 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C SLICE_X116Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.363 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/Q net (fo=5, routed) 0.201 -0.162 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[3] SLICE_X118Y50 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/I2 SLICE_X118Y50 LUT3 (Prop_lut3_I2_O) 0.045 -0.117 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/O net (fo=1, routed) 0.000 -0.117 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[3] SLICE_X118Y50 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.576 -0.371 clock pessimism 0.037 -0.334 SLICE_X118Y50 FDRE (Hold_fdre_C_D) 0.107 -0.227 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3] ------------------------------------------------------------------- required time 0.227 arrival time -0.117 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbidx_reg[24]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.376ns (logic 0.141ns (37.453%) route 0.235ns (62.547%)) Logic Levels: 0 Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.345ns Source Clock Delay (SCD): -0.504ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.345 -0.504 SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[24]/C SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_tlbidx_reg[24]/Q net (fo=33, routed) 0.235 -0.127 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[5] SLICE_X32Y53 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.602 -0.345 clock pessimism 0.037 -0.308 SLICE_X32Y53 FDRE (Hold_fdre_C_D) 0.070 -0.238 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0] ------------------------------------------------------------------- required time 0.238 arrival time -0.127 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbidx_reg[24]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.376ns (logic 0.141ns (37.453%) route 0.235ns (62.547%)) Logic Levels: 0 Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.345ns Source Clock Delay (SCD): -0.504ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.345 -0.504 SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[24]/C SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 f u_cpu/u_csr/csr_tlbidx_reg[24]/Q net (fo=33, routed) 0.235 -0.127 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[5] SLICE_X32Y53 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.602 -0.345 clock pessimism 0.037 -0.308 SLICE_X32Y53 FDRE (Hold_fdre_C_D) 0.070 -0.238 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0] ------------------------------------------------------------------- required time 0.238 arrival time -0.127 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.112ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.928%) route 0.287ns (67.072%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.490ns Source Clock Delay (SCD): -0.711ns ======= 1.501 -0.446 clock pessimism -0.211 -0.657 SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) 0.117 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.540 arrival time -0.437 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD/ADR4 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMS32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD/ADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMS32 (Hold_rams32_CLK_ADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD/ADR4 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMS32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD/ADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMS32 (Hold_rams32_CLK_ADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1/ADR4 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMS32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1/ADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMS32 (Hold_rams32_CLK_ADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1/ADR4 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMS32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1/ADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMS32 (Hold_rams32_CLK_ADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1 ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1 ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1 ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1 ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1 ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1 ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMS32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1 ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMS32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1 ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.106ns (arrival time - required time) Source: u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.240ns (logic 0.186ns (77.466%) route 0.054ns (22.534%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.456ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.682 SLICE_X63Y110 FDRE 0.000 -0.682 r u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/C SLICE_X63Y110 FDRE (Prop_fdre_C_Q) 0.141 -0.541 r u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/Q net (fo=1, routed) 0.054 -0.487 u_cdma_matmul_bridge/bank_dst_addr_reg[1]_3[20] SLICE_X62Y110 r u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1/I0 SLICE_X62Y110 LUT6 (Prop_lut6_I0_O) 0.045 -0.442 r u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1/O net (fo=1, routed) 0.000 -0.442 u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1_n_0 SLICE_X62Y110 FDRE r u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.491 -0.456 clock pessimism -0.213 -0.669 SLICE_X62Y110 FDRE (Hold_fdre_C_D) 0.121 -0.548 u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20] ------------------------------------------------------------------- required time 0.548 arrival time -0.442 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.106ns (arrival time - required time) Source: u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.240ns (logic 0.186ns (77.466%) route 0.054ns (22.534%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.456ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.682 SLICE_X63Y110 FDRE 0.000 -0.682 r u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/C SLICE_X63Y110 FDRE (Prop_fdre_C_Q) 0.141 -0.541 f u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/Q net (fo=1, routed) 0.054 -0.487 u_cdma_matmul_bridge/bank_dst_addr_reg[1]_3[20] SLICE_X62Y110 f u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1/I0 SLICE_X62Y110 LUT6 (Prop_lut6_I0_O) 0.045 -0.442 f u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1/O net (fo=1, routed) 0.000 -0.442 u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1_n_0 SLICE_X62Y110 FDRE f u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.491 -0.456 clock pessimism -0.213 -0.669 SLICE_X62Y110 FDRE (Hold_fdre_C_D) 0.121 -0.548 u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20] ------------------------------------------------------------------- required time 0.548 arrival time -0.442 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.107ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[22]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.269ns (logic 0.141ns (52.500%) route 0.128ns (47.500%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.442ns Source Clock Delay (SCD): -0.668ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.180 -0.668 SLICE_X115Y149 FDRE 0.000 -0.668 r u_cpu/u_csr/csr_tlbelo0_reg[22]/C SLICE_X115Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.527 r u_cpu/u_csr/csr_tlbelo0_reg[22]/Q net (fo=4, routed) 0.128 -0.399 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIB0 SLICE_X112Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.505 -0.442 clock pessimism -0.210 -0.652 SLICE_X112Y149 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.506 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB ------------------------------------------------------------------- required time 0.506 arrival time -0.399 ------------------------------------------------------------------- slack 0.107 Slack (MET) : 0.107ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[22]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.269ns (logic 0.141ns (52.500%) route 0.128ns (47.500%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.442ns Source Clock Delay (SCD): -0.668ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.180 -0.668 SLICE_X115Y149 FDRE 0.000 -0.668 r u_cpu/u_csr/csr_tlbelo0_reg[22]/C SLICE_X115Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.527 f u_cpu/u_csr/csr_tlbelo0_reg[22]/Q net (fo=4, routed) 0.128 -0.399 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIB0 SLICE_X112Y149 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.505 -0.442 clock pessimism -0.210 -0.652 SLICE_X112Y149 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.506 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB ------------------------------------------------------------------- required time 0.506 arrival time -0.399 ------------------------------------------------------------------- slack 0.107 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/u_csr/timer_64_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.677 SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] SLICE_X106Y146 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/A1 SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.501 -0.446 clock pessimism 0.045 -0.401 SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP ------------------------------------------------------------------- required time 0.092 arrival time 0.016 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/u_csr/timer_64_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.677 SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 f u_cpu/u_csr/timer_64_reg[1]/Q net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] SLICE_X106Y146 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/A1 SLICE_X104Y145 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.501 -0.446 clock pessimism 0.045 -0.401 SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP ------------------------------------------------------------------- required time 0.092 arrival time 0.016 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/u_csr/timer_64_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.677 SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] SLICE_X106Y146 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/A1 SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.501 -0.446 clock pessimism 0.045 -0.401 SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP ------------------------------------------------------------------- required time 0.092 arrival time 0.016 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/u_csr/timer_64_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.677 SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 f u_cpu/u_csr/timer_64_reg[1]/Q net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] SLICE_X106Y146 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/A1 SLICE_X104Y145 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.501 -0.446 clock pessimism 0.045 -0.401 SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP ------------------------------------------------------------------- required time 0.092 arrival time 0.016 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/u_csr/timer_64_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.677 SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] SLICE_X106Y146 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/A1 SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.501 -0.446 clock pessimism 0.045 -0.401 SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP ------------------------------------------------------------------- required time 0.092 arrival time 0.016 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/u_csr/timer_64_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.677 SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 f u_cpu/u_csr/timer_64_reg[1]/Q net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] SLICE_X106Y146 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/A1 SLICE_X104Y145 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.501 -0.446 clock pessimism 0.045 -0.401 SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP ------------------------------------------------------------------- required time 0.092 arrival time 0.016 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/u_csr/timer_64_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.677 SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] SLICE_X106Y146 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/A1 SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.501 -0.446 clock pessimism 0.045 -0.401 SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP ------------------------------------------------------------------- required time 0.092 arrival time 0.016 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/u_csr/timer_64_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.677 SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 f u_cpu/u_csr/timer_64_reg[1]/Q net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] SLICE_X106Y146 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/A1 SLICE_X104Y145 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.501 -0.446 clock pessimism 0.045 -0.401 SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP ------------------------------------------------------------------- required time 0.092 arrival time 0.016 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.495 -0.452 clock pessimism -0.210 -0.662 SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMA ------------------------------------------------------------------- required time 0.352 arrival time -0.244 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 SLICE_X132Y165 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.495 -0.452 clock pessimism -0.210 -0.662 SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMA ------------------------------------------------------------------- required time 0.352 arrival time -0.244 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.495 -0.452 clock pessimism -0.210 -0.662 SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 ------------------------------------------------------------------- required time 0.352 arrival time -0.244 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 SLICE_X132Y165 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.495 -0.452 clock pessimism -0.210 -0.662 SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 ------------------------------------------------------------------- required time 0.352 arrival time -0.244 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.495 -0.452 clock pessimism -0.210 -0.662 SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMB ------------------------------------------------------------------- required time 0.352 arrival time -0.244 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 SLICE_X132Y165 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.495 -0.452 clock pessimism -0.210 -0.662 SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMB ------------------------------------------------------------------- required time 0.352 arrival time -0.244 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.495 -0.452 clock pessimism -0.210 -0.662 SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 ------------------------------------------------------------------- required time 0.352 arrival time -0.244 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.676 SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 SLICE_X132Y165 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.495 -0.452 clock pessimism -0.210 -0.662 SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 ------------------------------------------------------------------- required time 0.352 arrival time -0.244 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.540ns (logic 0.186ns (34.444%) route 0.354ns (65.556%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.340ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.683ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.165 -0.683 SLICE_X71Y100 FDRE 0.000 -0.683 r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C SLICE_X71Y100 FDRE (Prop_fdre_C_Q) 0.141 -0.542 r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/Q net (fo=8, routed) 0.354 -0.188 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/_zz_ram_port1_reg[49][1] SLICE_X63Y97 r u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/ar_id_reg[1]_i_1/I5 SLICE_X63Y97 LUT6 (Prop_lut6_I5_O) 0.045 -0.143 r u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/ar_id_reg[1]_i_1/O net (fo=2, routed) 0.000 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/I172[3] SLICE_X63Y97 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism 0.040 -0.343 SLICE_X63Y97 FDRE (Hold_fdre_C_D) 0.092 -0.251 u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1] ------------------------------------------------------------------- required time 0.251 arrival time -0.143 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.540ns (logic 0.186ns (34.444%) route 0.354ns (65.556%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.340ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.683ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.165 -0.683 SLICE_X71Y100 FDRE 0.000 -0.683 r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C SLICE_X71Y100 FDRE (Prop_fdre_C_Q) 0.141 -0.542 f u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/Q net (fo=8, routed) 0.354 -0.188 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/_zz_ram_port1_reg[49][1] SLICE_X63Y97 f u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/ar_id_reg[1]_i_1/I5 SLICE_X63Y97 LUT6 (Prop_lut6_I5_O) 0.045 -0.143 f u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/ar_id_reg[1]_i_1/O net (fo=2, routed) 0.000 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/I172[3] SLICE_X63Y97 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism 0.040 -0.343 SLICE_X63Y97 FDRE (Hold_fdre_C_D) 0.092 -0.251 u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1] ------------------------------------------------------------------- required time 0.251 arrival time -0.143 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.110ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.478ns (logic 0.292ns (61.119%) route 0.186ns (38.881%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[0] SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[1]) 0.106 -0.226 r u_axi_uart_controller/uart0/regs/M_next_carry/O[1] net (fo=1, routed) 0.000 -0.226 u_axi_uart_controller/uart0/regs/M_next[1] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[1] ------------------------------------------------------------------- required time 0.336 arrival time -0.226 ------------------------------------------------------------------- slack 0.110 Slack (MET) : 0.110ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.478ns (logic 0.292ns (61.119%) route 0.186ns (38.881%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.704 SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[0] SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[1]) 0.106 -0.226 r u_axi_uart_controller/uart0/regs/M_next_carry/O[1] net (fo=1, routed) 0.000 -0.226 u_axi_uart_controller/uart0/regs/M_next[1] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[1] ------------------------------------------------------------------- required time 0.336 arrival time -0.226 ------------------------------------------------------------------- slack 0.110 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[7] RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.374 clock pessimism 0.040 -0.333 RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.040 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[7] RAMB18_X7Y40 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.374 clock pessimism 0.040 -0.333 RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.040 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[7] RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.374 clock pessimism 0.040 -0.333 RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.040 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[7] RAMB18_X7Y41 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.374 clock pessimism 0.040 -0.333 RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.040 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.303ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/Q[6] RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.645 -0.303 clock pessimism -0.214 -0.517 RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg ------------------------------------------------------------------- required time 0.334 arrival time -0.223 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.303ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/Q[6] RAMB18_X7Y39 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.645 -0.303 clock pessimism -0.214 -0.517 RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg ------------------------------------------------------------------- required time 0.334 arrival time -0.223 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.303ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/Q[6] RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.645 -0.303 clock pessimism -0.214 -0.517 RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg ------------------------------------------------------------------- required time 0.334 arrival time -0.223 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.303ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/Q[6] RAMB18_X7Y38 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.645 -0.303 clock pessimism -0.214 -0.517 RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg ------------------------------------------------------------------- required time 0.334 arrival time -0.223 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.373ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.246 -0.602 SLICE_X115Y95 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/Q net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[19] SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.373 clock pessimism -0.229 -0.602 SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.078 -0.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19] ------------------------------------------------------------------- required time 0.524 arrival time -0.405 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.373ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.246 -0.602 SLICE_X115Y95 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/Q net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[19] SLICE_X115Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.373 clock pessimism -0.229 -0.602 SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.078 -0.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19] ------------------------------------------------------------------- required time 0.524 arrival time -0.405 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.301ns (logic 0.141ns (46.859%) route 0.160ns (53.141%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.238 -0.610 SLICE_X57Y91 FDRE 0.000 -0.610 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C SLICE_X57Y91 FDRE (Prop_fdre_C_Q) 0.141 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/Q net (fo=1, routed) 0.160 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIC0 SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.192 -0.573 SLICE_X52Y90 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.429 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC ------------------------------------------------------------------- required time 0.429 arrival time -0.309 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.301ns (logic 0.141ns (46.859%) route 0.160ns (53.141%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.238 -0.610 SLICE_X57Y91 FDRE 0.000 -0.610 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C SLICE_X57Y91 FDRE (Prop_fdre_C_Q) 0.141 -0.469 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/Q net (fo=1, routed) 0.160 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIC0 SLICE_X52Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.192 -0.573 SLICE_X52Y90 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.429 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC ------------------------------------------------------------------- required time 0.429 arrival time -0.309 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.410ns (logic 0.186ns (45.405%) route 0.224ns (54.595%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.198ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.442ns Source Clock Delay (SCD): -0.600ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.248 -0.600 SLICE_X118Y99 FDCE 0.000 -0.600 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C SLICE_X118Y99 FDCE (Prop_fdce_C_Q) 0.141 -0.459 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/Q net (fo=29, routed) 0.224 -0.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0[0] SLICE_X114Y100 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/I1 SLICE_X114Y100 LUT6 (Prop_lut6_I1_O) 0.045 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/O net (fo=1, routed) 0.000 -0.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_next0[5] SLICE_X114Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.505 -0.442 clock pessimism 0.040 -0.402 SLICE_X114Y100 FDCE (Hold_fdce_C_D) 0.091 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5] ------------------------------------------------------------------- required time 0.311 arrival time -0.191 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.410ns (logic 0.186ns (45.405%) route 0.224ns (54.595%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.198ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.442ns Source Clock Delay (SCD): -0.600ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.248 -0.600 SLICE_X118Y99 FDCE 0.000 -0.600 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C SLICE_X118Y99 FDCE (Prop_fdce_C_Q) 0.141 -0.459 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/Q net (fo=29, routed) 0.224 -0.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0[0] SLICE_X114Y100 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/I1 SLICE_X114Y100 LUT6 (Prop_lut6_I1_O) 0.045 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/O net (fo=1, routed) 0.000 -0.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_next0[5] SLICE_X114Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.505 -0.442 clock pessimism 0.040 -0.402 SLICE_X114Y100 FDCE (Hold_fdce_C_D) 0.091 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5] ------------------------------------------------------------------- required time 0.311 arrival time -0.191 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.410ns (logic 0.186ns (45.405%) route 0.224ns (54.595%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.198ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.442ns Source Clock Delay (SCD): -0.600ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.248 -0.600 SLICE_X118Y99 FDCE 0.000 -0.600 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C SLICE_X118Y99 FDCE (Prop_fdce_C_Q) 0.141 -0.459 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/Q net (fo=29, routed) 0.224 -0.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0[0] SLICE_X114Y100 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/I1 SLICE_X114Y100 LUT6 (Prop_lut6_I1_O) 0.045 -0.191 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/O net (fo=1, routed) 0.000 -0.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_next0[5] SLICE_X114Y100 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.505 -0.442 clock pessimism 0.040 -0.402 SLICE_X114Y100 FDCE (Hold_fdce_C_D) 0.091 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5] ------------------------------------------------------------------- required time 0.311 arrival time -0.191 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.410ns (logic 0.186ns (45.405%) route 0.224ns (54.595%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.198ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.442ns Source Clock Delay (SCD): -0.600ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.248 -0.600 SLICE_X118Y99 FDCE 0.000 -0.600 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C SLICE_X118Y99 FDCE (Prop_fdce_C_Q) 0.141 -0.459 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/Q net (fo=29, routed) 0.224 -0.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0[0] SLICE_X114Y100 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/I1 SLICE_X114Y100 LUT6 (Prop_lut6_I1_O) 0.045 -0.191 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/O net (fo=1, routed) 0.000 -0.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_next0[5] SLICE_X114Y100 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.505 -0.442 clock pessimism 0.040 -0.402 SLICE_X114Y100 FDCE (Hold_fdce_C_D) 0.091 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5] ------------------------------------------------------------------- required time 0.311 arrival time -0.191 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) Logic Levels: 0 Clock Path Skew: 0.401ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.665ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.183 -0.665 SLICE_X138Y100 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg_0[4] RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.644 -0.304 clock pessimism 0.040 -0.263 RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg ------------------------------------------------------------------- required time 0.080 arrival time 0.040 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) Logic Levels: 0 Clock Path Skew: 0.401ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.665ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.183 -0.665 SLICE_X138Y100 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg_0[4] RAMB18_X7Y39 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.644 -0.304 clock pessimism 0.040 -0.263 RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg ------------------------------------------------------------------- required time 0.080 arrival time 0.040 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) Logic Levels: 0 Clock Path Skew: 0.401ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.665ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.183 -0.665 SLICE_X138Y100 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg_0[4] RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.644 -0.304 clock pessimism 0.040 -0.263 RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg ------------------------------------------------------------------- required time 0.080 arrival time 0.040 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) Logic Levels: 0 Clock Path Skew: 0.401ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.665ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.183 -0.665 SLICE_X138Y100 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg_0[4] RAMB18_X7Y38 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.644 -0.304 clock pessimism 0.040 -0.263 RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg ------------------------------------------------------------------- required time 0.080 arrival time 0.040 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.373ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.246 -0.602 SLICE_X115Y95 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/Q net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[18] SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.373 clock pessimism -0.229 -0.602 SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.076 -0.526 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18] ------------------------------------------------------------------- required time 0.526 arrival time -0.405 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.373ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.246 -0.602 SLICE_X115Y95 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/Q net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[18] SLICE_X115Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.373 clock pessimism -0.229 -0.602 SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.076 -0.526 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18] ------------------------------------------------------------------- required time 0.526 arrival time -0.405 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.138 -0.711 SLICE_X85Y171 FDCE 0.000 -0.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C SLICE_X85Y171 FDCE (Prop_fdce_C_Q) 0.141 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/Q net (fo=14, routed) 0.287 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[12] SLICE_X81Y173 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.457 -0.490 clock pessimism 0.040 -0.450 SLICE_X81Y173 FDCE (Hold_fdce_C_D) 0.055 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12] ------------------------------------------------------------------- required time 0.395 arrival time -0.283 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.928%) route 0.287ns (67.072%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.490ns Source Clock Delay (SCD): -0.711ns ======= (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[1] RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.374 clock pessimism 0.040 -0.333 RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.029 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.138 -0.711 SLICE_X85Y171 FDCE 0.000 -0.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C SLICE_X85Y171 FDCE (Prop_fdce_C_Q) 0.141 -0.570 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/Q net (fo=14, routed) 0.287 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[12] SLICE_X81Y173 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.457 -0.490 clock pessimism 0.040 -0.450 SLICE_X81Y173 FDCE (Hold_fdce_C_D) 0.055 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12] ------------------------------------------------------------------- required time 0.395 arrival time -0.283 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.642 -0.305 clock pessimism -0.217 -0.522 SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA ------------------------------------------------------------------- required time 0.212 arrival time -0.099 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.642 -0.305 clock pessimism -0.217 -0.522 SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA ------------------------------------------------------------------- required time 0.212 arrival time -0.099 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.642 -0.305 clock pessimism -0.217 -0.522 SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1 ------------------------------------------------------------------- required time 0.212 arrival time -0.099 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.642 -0.305 clock pessimism -0.217 -0.522 SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1 ------------------------------------------------------------------- required time 0.212 arrival time -0.099 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.642 -0.305 clock pessimism -0.217 -0.522 SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB ------------------------------------------------------------------- required time 0.212 arrival time -0.099 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.642 -0.305 clock pessimism -0.217 -0.522 SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB ------------------------------------------------------------------- required time 0.212 arrival time -0.099 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.642 -0.305 clock pessimism -0.217 -0.522 SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1 ------------------------------------------------------------------- required time 0.212 arrival time -0.099 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.310 -0.539 SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.642 -0.305 clock pessimism -0.217 -0.522 SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1 ------------------------------------------------------------------- required time 0.212 arrival time -0.099 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.114ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.488ns (logic 0.231ns (47.314%) route 0.257ns (52.686%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.399ns Source Clock Delay (SCD): -0.629ns Clock Pessimism Removal (CPR): -0.037ns ======= (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[1] RAMB18_X7Y40 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.374 clock pessimism 0.040 -0.333 RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.029 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[1] RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.374 clock pessimism 0.040 -0.333 RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.029 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[1] RAMB18_X7Y41 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.374 clock pessimism 0.040 -0.333 RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.029 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1 ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1 ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1 ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1 ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1 ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1 ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMS32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1 ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.618 SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMS32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1 ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X59Y91 FDCE 0.000 -0.612 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C SLICE_X59Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[0] SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.229 -0.612 SLICE_X59Y91 FDCE (Hold_fdce_C_D) 0.075 -0.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.537 arrival time -0.415 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X59Y91 FDCE 0.000 -0.612 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C SLICE_X59Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.471 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[0] SLICE_X59Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.229 -0.612 SLICE_X59Y91 FDCE (Hold_fdce_C_D) 0.075 -0.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.537 arrival time -0.415 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X67Y95 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[1] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.229 -0.616 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.075 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.541 arrival time -0.419 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X67Y95 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[1] SLICE_X67Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.229 -0.616 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.075 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.541 arrival time -0.419 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X69Y91 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C SLICE_X69Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[2] SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.229 -0.617 SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.542 arrival time -0.420 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X69Y91 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C SLICE_X69Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[2] SLICE_X69Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.229 -0.617 SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.542 arrival time -0.420 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.454ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/Q net (fo=1, routed) 0.056 -0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0 SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.493 -0.454 clock pessimism -0.226 -0.680 SLICE_X65Y102 FDCE (Hold_fdce_C_D) 0.075 -0.605 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg ------------------------------------------------------------------- required time 0.605 arrival time -0.483 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.454ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/Q net (fo=1, routed) 0.056 -0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0 SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.493 -0.454 clock pessimism -0.226 -0.680 SLICE_X65Y102 FDCE (Hold_fdce_C_D) 0.075 -0.605 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg ------------------------------------------------------------------- required time 0.605 arrival time -0.483 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.124ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.200ns (logic 0.141ns (70.589%) route 0.059ns (29.411%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X50Y83 FDCE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.059 -0.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.226 -0.613 SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.076 -0.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.537 arrival time -0.414 ------------------------------------------------------------------- slack 0.124 Slack (MET) : 0.124ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.200ns (logic 0.141ns (70.589%) route 0.059ns (29.411%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X50Y83 FDCE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.059 -0.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X50Y83 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.226 -0.613 SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.076 -0.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.537 arrival time -0.414 ------------------------------------------------------------------- slack 0.124 Slack (MET) : 0.125ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.577ns (logic 0.231ns (40.066%) route 0.346ns (59.934%)) Logic Levels: 2 (LUT3=1 LUT6=1) Clock Path Skew: 0.345ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.290ns Source Clock Delay (SCD): -0.598ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.250 -0.598 SLICE_X135Y50 FDCE 0.000 -0.598 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/C SLICE_X135Y50 FDCE (Prop_fdce_C_Q) 0.141 -0.457 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/Q net (fo=2, routed) 0.126 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/data31[9] SLICE_X135Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[753]_i_2/I0 SLICE_X135Y48 LUT6 (Prop_lut6_I0_O) 0.045 -0.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[753]_i_2/O net (fo=1, routed) 0.220 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[493] SLICE_X135Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[753]_i_1/I1 SLICE_X135Y48 LUT3 (Prop_lut3_I1_O) 0.045 -0.022 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[753]_i_1/O net (fo=1, routed) 0.000 -0.022 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[753] SLICE_X135Y48 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.657 -0.290 clock pessimism 0.037 -0.253 SLICE_X135Y48 FDCE (Hold_fdce_C_D) 0.107 -0.146 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753] ------------------------------------------------------------------- required time 0.146 arrival time -0.022 ------------------------------------------------------------------- slack 0.125 Slack (MET) : 0.125ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.577ns (logic 0.231ns (40.066%) route 0.346ns (59.934%)) Logic Levels: 2 (LUT3=1 LUT6=1) Clock Path Skew: 0.345ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.290ns Source Clock Delay (SCD): -0.598ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.250 -0.598 SLICE_X135Y50 FDCE 0.000 -0.598 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/C SLICE_X135Y50 FDCE (Prop_fdce_C_Q) 0.141 -0.457 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/Q net (fo=2, routed) 0.126 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/data31[9] SLICE_X135Y48 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[753]_i_2/I0 SLICE_X135Y48 LUT6 (Prop_lut6_I0_O) 0.045 -0.287 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[753]_i_2/O net (fo=1, routed) 0.220 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[493] SLICE_X135Y48 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[753]_i_1/I1 SLICE_X135Y48 LUT3 (Prop_lut3_I1_O) 0.045 -0.022 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[753]_i_1/O net (fo=1, routed) 0.000 -0.022 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[753] SLICE_X135Y48 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.657 -0.290 clock pessimism 0.037 -0.253 SLICE_X135Y48 FDCE (Hold_fdce_C_D) 0.107 -0.146 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753] ------------------------------------------------------------------- required time 0.146 arrival time -0.022 ------------------------------------------------------------------- slack 0.125 Slack (MET) : 0.125ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.512ns (logic 0.164ns (32.024%) route 0.348ns (67.976%)) Logic Levels: 0 Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.179 -0.669 SLICE_X108Y100 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/C SLICE_X108Y100 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/Q net (fo=1, routed) 0.348 -0.157 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[15] SLICE_X103Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X103Y99 FDCE (Hold_fdce_C_D) 0.057 -0.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15] ------------------------------------------------------------------- required time 0.282 arrival time -0.157 ------------------------------------------------------------------- slack 0.125 Slack (MET) : 0.125ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.512ns (logic 0.164ns (32.024%) route 0.348ns (67.976%)) Logic Levels: 0 Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.179 -0.669 SLICE_X108Y100 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/C SLICE_X108Y100 FDCE (Prop_fdce_C_Q) 0.164 -0.505 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/Q net (fo=1, routed) 0.348 -0.157 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[15] SLICE_X103Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X103Y99 FDCE (Hold_fdce_C_D) 0.057 -0.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15] ------------------------------------------------------------------- required time 0.282 arrival time -0.157 ------------------------------------------------------------------- slack 0.125 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X59Y91 FDCE 0.000 -0.612 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C SLICE_X59Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[2] SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.229 -0.612 SLICE_X59Y91 FDCE (Hold_fdce_C_D) 0.071 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.541 arrival time -0.415 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X59Y91 FDCE 0.000 -0.612 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C SLICE_X59Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.471 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[2] SLICE_X59Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.229 -0.612 SLICE_X59Y91 FDCE (Hold_fdce_C_D) 0.071 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.541 arrival time -0.415 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.373ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.246 -0.602 SLICE_X115Y95 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/C SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/Q net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[17] SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.373 clock pessimism -0.229 -0.602 SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.071 -0.531 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17] ------------------------------------------------------------------- required time 0.531 arrival time -0.405 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.373ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.246 -0.602 SLICE_X115Y95 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/C SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/Q net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[17] SLICE_X115Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.373 clock pessimism -0.229 -0.602 SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.071 -0.531 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17] ------------------------------------------------------------------- required time 0.531 arrival time -0.405 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.603ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.245 -0.603 SLICE_X115Y91 FDCE 0.000 -0.603 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/C SLICE_X115Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.462 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/Q net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[1] SLICE_X115Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.573 -0.374 clock pessimism -0.229 -0.603 SLICE_X115Y91 FDCE (Hold_fdce_C_D) 0.071 -0.532 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1] ------------------------------------------------------------------- required time 0.532 arrival time -0.406 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.603ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.245 -0.603 SLICE_X115Y91 FDCE 0.000 -0.603 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/C SLICE_X115Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.462 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/Q net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[1] SLICE_X115Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.573 -0.374 clock pessimism -0.229 -0.603 SLICE_X115Y91 FDCE (Hold_fdce_C_D) 0.071 -0.532 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1] ------------------------------------------------------------------- required time 0.532 arrival time -0.406 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.373ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.246 -0.602 SLICE_X115Y96 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/C SLICE_X115Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/Q net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[21] SLICE_X115Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.373 clock pessimism -0.229 -0.602 SLICE_X115Y96 FDCE (Hold_fdce_C_D) 0.071 -0.531 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21] ------------------------------------------------------------------- required time 0.531 arrival time -0.405 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.373ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.246 -0.602 SLICE_X115Y96 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/C SLICE_X115Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.461 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/Q net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[21] SLICE_X115Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.574 -0.373 clock pessimism -0.229 -0.602 SLICE_X115Y96 FDCE (Hold_fdce_C_D) 0.071 -0.531 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21] ------------------------------------------------------------------- required time 0.531 arrival time -0.405 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.127ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[5] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.711ns (logic 0.141ns (19.823%) route 0.570ns (80.177%)) Logic Levels: 0 Clock Path Skew: 0.401ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.665ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.183 -0.665 SLICE_X137Y102 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C SLICE_X137Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/Q net (fo=10, routed) 0.570 0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg_0[1] RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[5] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.644 -0.304 clock pessimism 0.040 -0.263 RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[5]) 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg ------------------------------------------------------------------- required time 0.080 arrival time 0.046 ------------------------------------------------------------------- slack 0.127 Slack (MET) : 0.127ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[5] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.711ns (logic 0.141ns (19.823%) route 0.570ns (80.177%)) Logic Levels: 0 Clock Path Skew: 0.401ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.665ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.183 -0.665 SLICE_X137Y102 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C SLICE_X137Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.524 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/Q net (fo=10, routed) 0.570 0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg_0[1] RAMB18_X7Y39 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[5] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.644 -0.304 clock pessimism 0.040 -0.263 RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[5]) 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg ------------------------------------------------------------------- required time 0.080 arrival time 0.046 ------------------------------------------------------------------- slack 0.127 Slack (MET) : 0.127ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[5] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.711ns (logic 0.141ns (19.823%) route 0.570ns (80.177%)) Logic Levels: 0 Clock Path Skew: 0.401ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.665ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.183 -0.665 SLICE_X137Y102 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C SLICE_X137Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/Q net (fo=10, routed) 0.570 0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg_0[1] RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[5] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.644 -0.304 clock pessimism 0.040 -0.263 RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[5]) 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg ------------------------------------------------------------------- required time 0.080 arrival time 0.046 ------------------------------------------------------------------- slack 0.127 Slack (MET) : 0.127ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[5] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.711ns (logic 0.141ns (19.823%) route 0.570ns (80.177%)) Logic Levels: 0 Clock Path Skew: 0.401ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.665ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.183 -0.665 SLICE_X137Y102 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C SLICE_X137Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.524 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/Q net (fo=10, routed) 0.570 0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg_0[1] RAMB18_X7Y38 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[5] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.644 -0.304 clock pessimism 0.040 -0.263 RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[5]) 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg ------------------------------------------------------------------- required time 0.080 arrival time 0.046 ------------------------------------------------------------------- slack 0.127 Slack (MET) : 0.128ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X50Y83 FDCE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q net (fo=1, routed) 0.058 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[1] SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.226 -0.613 SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.071 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.542 arrival time -0.415 ------------------------------------------------------------------- slack 0.128 Slack (MET) : 0.128ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X50Y83 FDCE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q net (fo=1, routed) 0.058 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[1] SLICE_X50Y83 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.226 -0.613 SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.071 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.542 arrival time -0.415 ------------------------------------------------------------------- slack 0.128 Slack (MET) : 0.129ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.255ns (logic 0.141ns (55.379%) route 0.114ns (44.621%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.443ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.178 -0.670 SLICE_X123Y110 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/C SLICE_X123Y110 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/Q net (fo=7, routed) 0.114 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r[3] SLICE_X120Y109 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.504 -0.443 clock pessimism -0.210 -0.653 SLICE_X120Y109 SRL16E (Hold_srl16e_CLK_D) 0.109 -0.544 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.544 arrival time -0.415 ------------------------------------------------------------------- slack 0.129 Slack (MET) : 0.129ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.255ns (logic 0.141ns (55.379%) route 0.114ns (44.621%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.443ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.178 -0.670 SLICE_X123Y110 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/C SLICE_X123Y110 FDCE (Prop_fdce_C_Q) 0.141 -0.529 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/Q net (fo=7, routed) 0.114 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r[3] SLICE_X120Y109 SRL16E f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.504 -0.443 clock pessimism -0.210 -0.653 SLICE_X120Y109 SRL16E (Hold_srl16e_CLK_D) 0.109 -0.544 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.544 arrival time -0.415 ------------------------------------------------------------------- slack 0.129 Slack (MET) : 0.130ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.282ns (logic 0.141ns (49.987%) route 0.141ns (50.013%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.179 -0.669 SLICE_X134Y112 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/C SLICE_X134Y112 FDCE (Prop_fdce_C_Q) 0.141 -0.528 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/Q net (fo=5, routed) 0.141 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[0] SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.502 -0.445 clock pessimism -0.189 -0.634 SLICE_X136Y113 SRL16E (Hold_srl16e_CLK_D) 0.117 -0.517 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.517 arrival time -0.387 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.130ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.282ns (logic 0.141ns (49.987%) route 0.141ns (50.013%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.179 -0.669 SLICE_X134Y112 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/C SLICE_X134Y112 FDCE (Prop_fdce_C_Q) 0.141 -0.528 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/Q net (fo=5, routed) 0.141 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[0] SLICE_X136Y113 SRL16E f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.502 -0.445 clock pessimism -0.189 -0.634 SLICE_X136Y113 SRL16E (Hold_srl16e_CLK_D) 0.117 -0.517 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.517 arrival time -0.387 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.130ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.313ns (logic 0.141ns (45.032%) route 0.172ns (54.968%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.238 -0.610 SLICE_X57Y91 FDRE 0.000 -0.610 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/C SLICE_X57Y91 FDRE (Prop_fdre_C_Q) 0.141 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/Q net (fo=1, routed) 0.172 -0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIB0 SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.192 -0.573 SLICE_X52Y90 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.427 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB ------------------------------------------------------------------- required time 0.427 arrival time -0.297 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.130ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.313ns (logic 0.141ns (45.032%) route 0.172ns (54.968%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.238 -0.610 SLICE_X57Y91 FDRE 0.000 -0.610 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/C SLICE_X57Y91 FDRE (Prop_fdre_C_Q) 0.141 -0.469 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/Q net (fo=1, routed) 0.172 -0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIB0 SLICE_X52Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.192 -0.573 SLICE_X52Y90 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.427 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB ------------------------------------------------------------------- required time 0.427 arrival time -0.297 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.130ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.544ns (logic 0.141ns (25.911%) route 0.403ns (74.090%)) Logic Levels: 0 Clock Path Skew: 0.343ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.371ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y102 FDCE 0.000 -0.674 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/C SLICE_X103Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.533 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/Q net (fo=1, routed) 0.403 -0.130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0_n_0 SLICE_X117Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.576 -0.371 clock pessimism 0.040 -0.331 SLICE_X117Y99 FDCE (Hold_fdce_C_D) 0.071 -0.260 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1 ------------------------------------------------------------------- required time 0.260 arrival time -0.130 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.130ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.544ns (logic 0.141ns (25.911%) route 0.403ns (74.090%)) Logic Levels: 0 Clock Path Skew: 0.343ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.371ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.174 -0.674 SLICE_X103Y102 FDCE 0.000 -0.674 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/C SLICE_X103Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.533 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/Q net (fo=1, routed) 0.403 -0.130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0_n_0 SLICE_X117Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.576 -0.371 clock pessimism 0.040 -0.331 SLICE_X117Y99 FDCE (Hold_fdce_C_D) 0.071 -0.260 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1 ------------------------------------------------------------------- required time 0.260 arrival time -0.130 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.131ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X50Y83 FDCE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.065 -0.407 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.226 -0.613 SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.075 -0.538 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.538 arrival time -0.407 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X50Y83 FDCE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.065 -0.407 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X50Y83 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.226 -0.613 SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.075 -0.538 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.538 arrival time -0.407 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.382ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.237 -0.611 SLICE_X54Y88 FDCE 0.000 -0.611 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C SLICE_X54Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.470 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q net (fo=1, routed) 0.065 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[1] SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.565 -0.382 clock pessimism -0.229 -0.611 SLICE_X54Y88 FDCE (Hold_fdce_C_D) 0.075 -0.536 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.536 arrival time -0.405 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.382ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.237 -0.611 SLICE_X54Y88 FDCE 0.000 -0.611 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C SLICE_X54Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.470 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q net (fo=1, routed) 0.065 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[1] SLICE_X54Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.565 -0.382 clock pessimism -0.229 -0.611 SLICE_X54Y88 FDCE (Hold_fdce_C_D) 0.075 -0.536 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.536 arrival time -0.405 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.132ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.237ns (logic 0.186ns (78.504%) route 0.051ns (21.496%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X54Y85 FDRE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C SLICE_X54Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/Q net (fo=1, routed) 0.051 -0.421 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_burst_reg[1]_0[14] SLICE_X55Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1/I0 SLICE_X55Y85 LUT4 (Prop_lut4_I0_O) 0.045 -0.376 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1/O net (fo=1, routed) 0.000 -0.376 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1_n_0 SLICE_X55Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.215 -0.600 SLICE_X55Y85 FDRE (Hold_fdre_C_D) 0.092 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14] ------------------------------------------------------------------- required time 0.508 arrival time -0.376 ------------------------------------------------------------------- slack 0.132 Slack (MET) : 0.132ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.237ns (logic 0.186ns (78.504%) route 0.051ns (21.496%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X54Y85 FDRE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C SLICE_X54Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.472 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/Q net (fo=1, routed) 0.051 -0.421 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_burst_reg[1]_0[14] SLICE_X55Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1/I0 SLICE_X55Y85 LUT4 (Prop_lut4_I0_O) 0.045 -0.376 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1/O net (fo=1, routed) 0.000 -0.376 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1_n_0 SLICE_X55Y85 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.215 -0.600 SLICE_X55Y85 FDRE (Hold_fdre_C_D) 0.092 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14] ------------------------------------------------------------------- required time 0.508 arrival time -0.376 ------------------------------------------------------------------- slack 0.132 Slack (MET) : 0.133ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.530ns (logic 0.141ns (26.621%) route 0.389ns (73.379%)) Logic Levels: 0 Clock Path Skew: 0.338ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.370ns Source Clock Delay (SCD): -0.668ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.180 -0.668 SLICE_X122Y105 FDCE 0.000 -0.668 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/C SLICE_X122Y105 FDCE (Prop_fdce_C_Q) 0.141 -0.527 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/Q net (fo=14, routed) 0.389 -0.138 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[23]_1[16] SLICE_X128Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.577 -0.370 clock pessimism 0.040 -0.330 SLICE_X128Y99 FDCE (Hold_fdce_C_D) 0.059 -0.271 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16] ------------------------------------------------------------------- required time 0.271 arrival time -0.138 ------------------------------------------------------------------- slack 0.133 Slack (MET) : 0.133ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.530ns (logic 0.141ns (26.621%) route 0.389ns (73.379%)) Logic Levels: 0 Clock Path Skew: 0.338ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.370ns Source Clock Delay (SCD): -0.668ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.180 -0.668 SLICE_X122Y105 FDCE 0.000 -0.668 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/C SLICE_X122Y105 FDCE (Prop_fdce_C_Q) 0.141 -0.527 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/Q net (fo=14, routed) 0.389 -0.138 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[23]_1[16] SLICE_X128Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.577 -0.370 clock pessimism 0.040 -0.330 SLICE_X128Y99 FDCE (Hold_fdce_C_D) 0.059 -0.271 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16] ------------------------------------------------------------------- required time 0.271 arrival time -0.138 ------------------------------------------------------------------- slack 0.133 Slack (MET) : 0.573ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.019ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.229 -0.619 SLICE_X67Y87 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.213 -0.600 SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.667 arrival time -0.094 ------------------------------------------------------------------- slack 0.573 Slack (MET) : 0.573ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.019ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.229 -0.619 SLICE_X67Y87 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.213 -0.600 SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.667 arrival time -0.094 ------------------------------------------------------------------- slack 0.573 Slack (MET) : 0.573ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.019ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.229 -0.619 SLICE_X67Y87 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.213 -0.600 SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.667 arrival time -0.094 ------------------------------------------------------------------- slack 0.573 Slack (MET) : 0.658ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.923ns (logic 0.227ns (24.583%) route 0.696ns (75.417%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.332ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.414 0.243 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X72Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism 0.040 -0.348 SLICE_X72Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.415 arrival time 0.243 ------------------------------------------------------------------- slack 0.658 Slack (MET) : 0.681ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.596ns (logic 0.246ns (41.259%) route 0.350ns (58.741%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.007ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.293 -0.089 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X93Y122 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.478 -0.469 clock pessimism -0.209 -0.678 SLICE_X93Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.770 arrival time -0.089 ------------------------------------------------------------------- slack 0.681 Slack (MET) : 0.692ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.480 -0.467 clock pessimism -0.189 -0.656 SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.723 arrival time -0.031 ------------------------------------------------------------------- slack 0.692 Slack (MET) : 0.692ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.480 -0.467 clock pessimism -0.189 -0.656 SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.723 arrival time -0.031 ------------------------------------------------------------------- slack 0.692 Slack (MET) : 0.692ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.480 -0.467 clock pessimism -0.189 -0.656 SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.723 arrival time -0.031 ------------------------------------------------------------------- slack 0.692 Slack (MET) : 0.692ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.480 -0.467 clock pessimism -0.189 -0.656 SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.723 arrival time -0.031 ------------------------------------------------------------------- slack 0.692 Slack (MET) : 0.750ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.007ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.478 -0.469 clock pessimism -0.209 -0.678 SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.770 arrival time -0.020 ------------------------------------------------------------------- slack 0.750 Slack (MET) : 0.750ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.007ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.478 -0.469 clock pessimism -0.209 -0.678 SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.770 arrival time -0.020 ------------------------------------------------------------------- slack 0.750 Slack (MET) : 0.750ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.007ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.478 -0.469 clock pessimism -0.209 -0.678 SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.770 arrival time -0.020 ------------------------------------------------------------------- slack 0.750 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.486 -0.461 clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.486 -0.461 clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.486 -0.461 clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.486 -0.461 clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.486 -0.461 clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.796ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.557 -0.390 clock pessimism 0.040 -0.350 SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.417 arrival time 0.379 ------------------------------------------------------------------- slack 0.796 Slack (MET) : 0.796ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.557 -0.390 clock pessimism 0.040 -0.350 SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.417 arrival time 0.379 ------------------------------------------------------------------- slack 0.796 Slack (MET) : 0.796ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.557 -0.390 clock pessimism 0.040 -0.350 SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.417 arrival time 0.379 ------------------------------------------------------------------- slack 0.796 Slack (MET) : 0.796ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.557 -0.390 clock pessimism 0.040 -0.350 SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.417 arrival time 0.379 ------------------------------------------------------------------- slack 0.796 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.479 -0.468 clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.479 -0.468 clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.479 -0.468 clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.479 -0.468 clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.479 -0.468 clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.479 -0.468 clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.807ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.556 -0.391 clock pessimism 0.040 -0.351 SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.418 arrival time 0.389 ------------------------------------------------------------------- slack 0.807 Slack (MET) : 0.807ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.556 -0.391 clock pessimism 0.040 -0.351 SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.418 arrival time 0.389 ------------------------------------------------------------------- slack 0.807 Slack (MET) : 0.807ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.556 -0.391 clock pessimism 0.040 -0.351 SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.418 arrival time 0.389 ------------------------------------------------------------------- slack 0.807 Slack (MET) : 0.807ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.556 -0.391 clock pessimism 0.040 -0.351 SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.418 arrival time 0.389 ------------------------------------------------------------------- slack 0.807 Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism -0.209 -0.667 SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.734 arrival time 0.074 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism -0.209 -0.667 SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.734 arrival time 0.074 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism -0.209 -0.667 SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.734 arrival time 0.074 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism -0.209 -0.667 SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.734 arrival time 0.074 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism -0.209 -0.667 SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.734 arrival time 0.074 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.163 -0.685 SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism -0.209 -0.667 SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.734 arrival time 0.074 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.556 -0.391 clock pessimism 0.040 -0.351 SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.443 arrival time 0.389 ------------------------------------------------------------------- slack 0.832 Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.556 -0.391 clock pessimism 0.040 -0.351 SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.443 arrival time 0.389 ------------------------------------------------------------------- slack 0.832 Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.556 -0.391 clock pessimism 0.040 -0.351 SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.443 arrival time 0.389 ------------------------------------------------------------------- slack 0.832 Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.556 -0.391 clock pessimism 0.040 -0.351 SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.443 arrival time 0.389 ------------------------------------------------------------------- slack 0.832 Slack (MET) : 0.837ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.812ns (logic 0.227ns (27.961%) route 0.585ns (72.039%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.192ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.219 -0.629 SLICE_X83Y93 FDCE 0.000 -0.629 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C SLICE_X83Y93 FDCE (Prop_fdce_C_Q) 0.128 -0.501 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/Q net (fo=118, routed) 0.257 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10_n_0 SLICE_X85Y98 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/I0 SLICE_X85Y98 LUT2 (Prop_lut2_I0_O) 0.103 -0.141 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/O net (fo=1, routed) 0.000 -0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1_n_0 SLICE_X85Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D ======= 1.229 -0.619 SLICE_X67Y87 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.445 0.192 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X64Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.548 -0.399 clock pessimism 0.037 -0.362 SLICE_X85Y98 FDCE (Hold_fdce_C_D) 0.107 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360] ------------------------------------------------------------------- required time 0.255 arrival time -0.141 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.114ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.488ns (logic 0.231ns (47.314%) route 0.257ns (52.686%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.399ns Source Clock Delay (SCD): -0.629ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.219 -0.629 SLICE_X83Y93 FDCE 0.000 -0.629 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C SLICE_X83Y93 FDCE (Prop_fdce_C_Q) 0.128 -0.501 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/Q net (fo=118, routed) 0.257 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10_n_0 SLICE_X85Y98 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/I0 SLICE_X85Y98 LUT2 (Prop_lut2_I0_O) 0.103 -0.141 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/O net (fo=1, routed) 0.000 -0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1_n_0 SLICE_X85Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.548 -0.399 clock pessimism 0.037 -0.362 SLICE_X85Y98 FDCE (Hold_fdce_C_D) 0.107 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360] ------------------------------------------------------------------- required time 0.255 arrival time -0.141 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.115ns (arrival time - required time) Source: u_confreg/confreg_int_edge_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.384 -0.465 SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 r u_confreg/confreg_int_edge_reg[3]/Q net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] SLICE_X3Y50 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0 SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 SLICE_X3Y50 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.642 -0.305 clock pessimism 0.037 -0.268 SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] ------------------------------------------------------------------- required time 0.177 arrival time -0.063 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.115ns (arrival time - required time) Source: u_confreg/confreg_int_edge_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): -0.037ns ======= 1.562 -0.385 clock pessimism -0.192 -0.577 SLICE_X64Y95 FDCE (Remov_fdce_C_CLR) -0.067 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.644 arrival time 0.192 ------------------------------------------------------------------- slack 0.837 Slack (MET) : 0.871ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.822ns (logic 0.227ns (27.605%) route 0.595ns (72.395%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.192ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.384 -0.465 SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 f u_confreg/confreg_int_edge_reg[3]/Q net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] SLICE_X3Y50 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0 SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 SLICE_X3Y50 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[3]/D ======= 1.229 -0.619 SLICE_X67Y87 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.456 0.203 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X65Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.642 -0.305 clock pessimism 0.037 -0.268 SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] ------------------------------------------------------------------- required time 0.177 arrival time -0.063 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.115ns (arrival time - required time) Source: u_confreg/confreg_int_edge_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.384 -0.465 SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 r u_confreg/confreg_int_edge_reg[3]/Q net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] SLICE_X3Y50 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0 SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 SLICE_X3Y50 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.642 -0.305 clock pessimism 0.037 -0.268 SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] ------------------------------------------------------------------- required time 0.177 arrival time -0.063 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.115ns (arrival time - required time) Source: u_confreg/confreg_int_edge_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.384 -0.465 SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 f u_confreg/confreg_int_edge_reg[3]/Q net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] SLICE_X3Y50 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0 SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 SLICE_X3Y50 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.642 -0.305 clock pessimism 0.037 -0.268 SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] ------------------------------------------------------------------- required time 0.177 arrival time -0.063 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.115ns (arrival time - required time) Source: u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.387ns (logic 0.141ns (36.445%) route 0.246ns (63.555%)) Logic Levels: 0 Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): -0.037ns ======= 1.563 -0.384 clock pessimism -0.192 -0.576 SLICE_X65Y99 FDCE (Remov_fdce_C_CLR) -0.092 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.668 arrival time 0.203 ------------------------------------------------------------------- slack 0.871 Slack (MET) : 0.871ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.822ns (logic 0.227ns (27.605%) route 0.595ns (72.395%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.192ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.384 -0.465 SLICE_X1Y49 FDCE 0.000 -0.465 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C SLICE_X1Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/Q net (fo=3, routed) 0.246 -0.078 u_confreg/u_int_ctrl/int_in_sync_d2[5] SLICE_X3Y51 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D ======= 1.229 -0.619 SLICE_X67Y87 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.456 0.203 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X65Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.642 -0.305 clock pessimism 0.037 -0.268 SLICE_X3Y51 FDCE (Hold_fdce_C_D) 0.075 -0.193 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5] ------------------------------------------------------------------- required time 0.193 arrival time -0.078 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.115ns (arrival time - required time) Source: u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.387ns (logic 0.141ns (36.445%) route 0.246ns (63.555%)) Logic Levels: 0 Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.384 -0.465 SLICE_X1Y49 FDCE 0.000 -0.465 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C SLICE_X1Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/Q net (fo=3, routed) 0.246 -0.078 u_confreg/u_int_ctrl/int_in_sync_d2[5] SLICE_X3Y51 FDCE f u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.642 -0.305 clock pessimism 0.037 -0.268 SLICE_X3Y51 FDCE (Hold_fdce_C_D) 0.075 -0.193 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5] ------------------------------------------------------------------- required time 0.193 arrival time -0.078 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.141ns (30.326%) route 0.324ns (69.674%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.619 SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/Q net (fo=15, routed) 0.324 -0.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[19] SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.045 -0.342 SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.072 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19] ------------------------------------------------------------------- required time 0.270 arrival time -0.154 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.141ns (30.326%) route 0.324ns (69.674%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.230 -0.619 SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/Q net (fo=15, routed) 0.324 -0.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[19] SLICE_X159Y140 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.045 -0.342 SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.072 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19] ------------------------------------------------------------------- required time 0.270 arrival time -0.154 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1 ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1 ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ======= 1.563 -0.384 clock pessimism -0.192 -0.576 SLICE_X65Y99 FDCE (Remov_fdce_C_CLR) -0.092 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.668 arrival time 0.203 ------------------------------------------------------------------- slack 0.871 Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism 0.040 -0.345 SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.437 arrival time 0.447 ------------------------------------------------------------------- slack 0.884 Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism 0.040 -0.345 SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.437 arrival time 0.447 ------------------------------------------------------------------- slack 0.884 Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism 0.040 -0.345 SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.437 arrival time 0.447 ------------------------------------------------------------------- slack 0.884 Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism 0.040 -0.345 SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.437 arrival time 0.447 ------------------------------------------------------------------- slack 0.884 Slack (MET) : 0.906ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.080ns (logic 0.226ns (20.934%) route 0.854ns (79.066%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.683 0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.040 -0.347 SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15] ------------------------------------------------------------------- required time 0.506 arrival time 0.400 ------------------------------------------------------------------- slack 0.906 Slack (MET) : 0.906ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.080ns (logic 0.226ns (20.934%) route 0.854ns (79.066%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.683 0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.040 -0.347 SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53] ------------------------------------------------------------------- required time 0.506 arrival time 0.400 ------------------------------------------------------------------- slack 0.906 Slack (MET) : 0.912ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C >>>>>>> Stashed changes (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns ======= Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 ======= 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ======= 1.470 -0.477 clock pessimism -0.189 -0.666 SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.733 arrival time 0.179 ------------------------------------------------------------------- slack 0.912 Slack (MET) : 0.912ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C >>>>>>> Stashed changes (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns ======= Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 ======= 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ======= 1.470 -0.477 clock pessimism -0.189 -0.666 SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.733 arrival time 0.179 ------------------------------------------------------------------- slack 0.912 Slack (MET) : 0.912ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C >>>>>>> Stashed changes (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns ======= Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 ======= 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1 ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ======= 1.470 -0.477 clock pessimism -0.189 -0.666 SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.733 arrival time 0.179 ------------------------------------------------------------------- slack 0.912 Slack (MET) : 0.912ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C >>>>>>> Stashed changes (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns ======= Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 ======= 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1 ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ======= 1.470 -0.477 clock pessimism -0.189 -0.666 SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 0.733 arrival time 0.179 ------------------------------------------------------------------- slack 0.912 Slack (MET) : 0.919ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.023ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.486 -0.461 clock pessimism -0.209 -0.670 SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.737 arrival time 0.182 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.919ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.023ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.486 -0.461 clock pessimism -0.209 -0.670 SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.737 arrival time 0.182 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.919ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.023ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.486 -0.461 clock pessimism -0.209 -0.670 SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.737 arrival time 0.182 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.919ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.023ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.486 -0.461 clock pessimism -0.209 -0.670 SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.737 arrival time 0.182 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.927ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.040 -0.341 SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16] ------------------------------------------------------------------- required time 0.475 arrival time 0.452 ------------------------------------------------------------------- slack 0.927 Slack (MET) : 0.927ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.040 -0.341 SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17] ------------------------------------------------------------------- required time 0.475 arrival time 0.452 ------------------------------------------------------------------- slack 0.927 Slack (MET) : 0.927ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.040 -0.341 SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18] ------------------------------------------------------------------- required time 0.475 arrival time 0.452 ------------------------------------------------------------------- slack 0.927 Slack (MET) : 0.927ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.040 -0.341 SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19] ------------------------------------------------------------------- required time 0.475 arrival time 0.452 ------------------------------------------------------------------- slack 0.927 Slack (MET) : 0.931ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.105ns (logic 0.206ns (18.647%) route 0.899ns (81.353%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.683 0.425 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.040 -0.347 SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15] ------------------------------------------------------------------- required time 0.506 arrival time 0.425 ------------------------------------------------------------------- slack 0.931 Slack (MET) : 0.931ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.105ns (logic 0.206ns (18.647%) route 0.899ns (81.353%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.683 0.425 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.040 -0.347 SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53] ------------------------------------------------------------------- required time 0.506 arrival time 0.425 ------------------------------------------------------------------- slack 0.931 Slack (MET) : 0.931ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0] ------------------------------------------------------------------- required time 0.473 arrival time 0.458 ------------------------------------------------------------------- slack 0.931 Slack (MET) : 0.931ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16] ------------------------------------------------------------------- required time 0.473 arrival time 0.458 ------------------------------------------------------------------- slack 0.931 Slack (MET) : 0.931ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17] ------------------------------------------------------------------- required time 0.473 arrival time 0.458 ------------------------------------------------------------------- slack 0.931 Slack (MET) : 0.931ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18] ------------------------------------------------------------------- required time 0.473 arrival time 0.458 ------------------------------------------------------------------- slack 0.931 Slack (MET) : 0.931ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[19]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[19] ------------------------------------------------------------------- required time 0.473 arrival time 0.458 ------------------------------------------------------------------- slack 0.931 Slack (MET) : 0.935ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[12]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[12]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.040 -0.341 SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[12] ------------------------------------------------------------------- required time 0.475 arrival time 0.460 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[13]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.040 -0.341 SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[13] ------------------------------------------------------------------- required time 0.475 arrival time 0.460 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[14]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[14]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.040 -0.341 SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[14] ------------------------------------------------------------------- required time 0.475 arrival time 0.460 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[15]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.040 -0.341 SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[15] ------------------------------------------------------------------- required time 0.475 arrival time 0.460 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.936ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.113ns (logic 0.226ns (20.298%) route 0.887ns (79.702%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.717 0.433 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X99Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.563 -0.384 clock pessimism 0.040 -0.344 SLICE_X99Y96 FDCE (Remov_fdce_C_CLR) -0.159 -0.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep ------------------------------------------------------------------- required time 0.503 arrival time 0.433 ------------------------------------------------------------------- slack 0.936 Slack (MET) : 0.936ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep__2/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.113ns (logic 0.226ns (20.298%) route 0.887ns (79.702%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.717 0.433 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X99Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep__2/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.563 -0.384 clock pessimism 0.040 -0.344 SLICE_X99Y96 FDCE (Remov_fdce_C_CLR) -0.159 -0.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep__2 ------------------------------------------------------------------- required time 0.503 arrival time 0.433 ------------------------------------------------------------------- slack 0.936 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C >>>>>>> Stashed changes (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns ======= Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 ======= 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ======= 1.470 -0.477 clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C >>>>>>> Stashed changes (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns ======= Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 ======= 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ======= 1.470 -0.477 clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C >>>>>>> Stashed changes (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns ======= Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 ======= 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1 ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ======= 1.470 -0.477 clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C >>>>>>> Stashed changes (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns ======= Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 ======= 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1 ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ======= 1.470 -0.477 clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C >>>>>>> Stashed changes (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns ======= Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 ======= 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ======= 1.470 -0.477 clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C >>>>>>> Stashed changes (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns ======= Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMS32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 ======= 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ======= 1.470 -0.477 clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C >>>>>>> Stashed changes (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns ======= Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 ======= 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1 ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ======= 1.470 -0.477 clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C >>>>>>> Stashed changes (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns ======= Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency <<<<<<< Updated upstream 1.354 -0.495 SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMS32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 ======= 1.155 -0.693 SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency <<<<<<< Updated upstream 1.610 -0.337 clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1 ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.118ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.475ns (logic 0.209ns (44.013%) route 0.266ns (55.987%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.420ns Source Clock Delay (SCD): -0.640ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.208 -0.640 SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q net (fo=127, routed) 0.266 -0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 SLICE_X151Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/I1 SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.165 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/O net (fo=1, routed) 0.000 -0.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1_n_0 SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.527 -0.420 clock pessimism 0.045 -0.375 SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.092 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8] ------------------------------------------------------------------- required time 0.283 arrival time -0.165 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.118ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.475ns (logic 0.209ns (44.013%) route 0.266ns (55.987%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.420ns Source Clock Delay (SCD): -0.640ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.208 -0.640 SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q net (fo=127, routed) 0.266 -0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 SLICE_X151Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/I1 SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.165 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/O net (fo=1, routed) 0.000 -0.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1_n_0 SLICE_X151Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.527 -0.420 clock pessimism 0.045 -0.375 SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.092 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8] ------------------------------------------------------------------- required time 0.283 arrival time -0.165 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.475ns (logic 0.209ns (44.040%) route 0.266ns (55.960%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.403ns Source Clock Delay (SCD): -0.630ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.218 -0.630 SLICE_X84Y61 FDRE 0.000 -0.630 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C SLICE_X84Y61 FDRE (Prop_fdre_C_Q) 0.164 -0.466 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/Q net (fo=6, routed) 0.266 -0.201 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][14]__0_0[7] SLICE_X82Y61 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/I3 SLICE_X82Y61 LUT6 (Prop_lut6_I3_O) 0.045 -0.156 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/O net (fo=1, routed) 0.000 -0.156 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_sp_re[7] SLICE_X82Y61 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.544 -0.403 clock pessimism 0.037 -0.366 SLICE_X82Y61 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7] ------------------------------------------------------------------- required time 0.274 arrival time -0.156 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.475ns (logic 0.209ns (44.040%) route 0.266ns (55.960%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.403ns Source Clock Delay (SCD): -0.630ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.218 -0.630 SLICE_X84Y61 FDRE 0.000 -0.630 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C SLICE_X84Y61 FDRE (Prop_fdre_C_Q) 0.164 -0.466 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/Q net (fo=6, routed) 0.266 -0.201 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][14]__0_0[7] SLICE_X82Y61 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/I3 SLICE_X82Y61 LUT6 (Prop_lut6_I3_O) 0.045 -0.156 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/O net (fo=1, routed) 0.000 -0.156 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_sp_re[7] SLICE_X82Y61 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.544 -0.403 clock pessimism 0.037 -0.366 SLICE_X82Y61 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7] ------------------------------------------------------------------- required time 0.274 arrival time -0.156 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.119ns (arrival time - required time) Source: u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.418ns Source Clock Delay (SCD): -0.645ns Clock Pessimism Removal (CPR): 0.227ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.203 -0.645 SLICE_X39Y105 FDRE 0.000 -0.645 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C SLICE_X39Y105 FDRE (Prop_fdre_C_Q) 0.141 -0.504 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/Q net (fo=1, routed) 0.056 -0.448 u_matmul_axi_slave/mult_inst[3].u_mult/prod[59] SLICE_X39Y105 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.529 -0.418 clock pessimism -0.227 -0.645 SLICE_X39Y105 FDRE (Hold_fdre_C_D) 0.078 -0.567 u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59] ------------------------------------------------------------------- required time 0.567 arrival time -0.448 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.119ns (arrival time - required time) Source: u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.418ns Source Clock Delay (SCD): -0.645ns Clock Pessimism Removal (CPR): 0.227ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.203 -0.645 SLICE_X39Y105 FDRE 0.000 -0.645 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C SLICE_X39Y105 FDRE (Prop_fdre_C_Q) 0.141 -0.504 f u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/Q net (fo=1, routed) 0.056 -0.448 u_matmul_axi_slave/mult_inst[3].u_mult/prod[59] SLICE_X39Y105 FDRE f u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.529 -0.418 clock pessimism -0.227 -0.645 SLICE_X39Y105 FDRE (Hold_fdre_C_D) 0.078 -0.567 u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59] ------------------------------------------------------------------- required time 0.567 arrival time -0.448 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.476ns (logic 0.209ns (43.921%) route 0.267ns (56.079%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.420ns Source Clock Delay (SCD): -0.640ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.208 -0.640 SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q net (fo=127, routed) 0.267 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 SLICE_X151Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/I1 SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.164 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/O net (fo=1, routed) 0.000 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1_n_0 SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.527 -0.420 clock pessimism 0.045 -0.375 SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.091 -0.284 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6] ------------------------------------------------------------------- required time 0.284 arrival time -0.164 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.476ns (logic 0.209ns (43.921%) route 0.267ns (56.079%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.420ns Source Clock Delay (SCD): -0.640ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.208 -0.640 SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q net (fo=127, routed) 0.267 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 SLICE_X151Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/I1 SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/O net (fo=1, routed) 0.000 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1_n_0 SLICE_X151Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.527 -0.420 clock pessimism 0.045 -0.375 SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.091 -0.284 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6] ------------------------------------------------------------------- required time 0.284 arrival time -0.164 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.727ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.651ns (logic 0.227ns (34.873%) route 0.424ns (65.127%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.263ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.143 0.154 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X11Y39 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.684 -0.263 clock pessimism -0.218 -0.481 SLICE_X11Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.573 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.573 arrival time 0.154 ------------------------------------------------------------------- slack 0.727 Slack (MET) : 0.727ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.651ns (logic 0.227ns (34.873%) route 0.424ns (65.127%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.263ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.143 0.154 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X11Y39 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.684 -0.263 clock pessimism -0.218 -0.481 SLICE_X11Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.573 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.573 arrival time 0.154 ------------------------------------------------------------------- slack 0.727 Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.525 arrival time 0.236 ------------------------------------------------------------------- slack 0.761 Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.525 arrival time 0.236 ------------------------------------------------------------------- slack 0.761 Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.525 arrival time 0.236 ------------------------------------------------------------------- slack 0.761 Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 0.525 arrival time 0.236 ------------------------------------------------------------------- slack 0.761 Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.218 -0.480 SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.547 arrival time 0.218 ------------------------------------------------------------------- slack 0.765 Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.218 -0.480 SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.547 arrival time 0.218 ------------------------------------------------------------------- slack 0.765 Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.218 -0.480 SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.547 arrival time 0.218 ------------------------------------------------------------------- slack 0.765 Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.218 -0.480 SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.547 arrival time 0.218 ------------------------------------------------------------------- slack 0.765 Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.218 -0.480 SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.547 arrival time 0.218 ------------------------------------------------------------------- slack 0.765 Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.218 -0.480 SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.547 arrival time 0.218 ------------------------------------------------------------------- slack 0.765 Slack (MET) : 0.790ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.736ns (logic 0.227ns (30.836%) route 0.509ns (69.164%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.263ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.228 0.239 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y39 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.684 -0.263 clock pessimism -0.196 -0.459 SLICE_X13Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.551 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.551 arrival time 0.239 ------------------------------------------------------------------- slack 0.790 Slack (MET) : 0.790ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.218 -0.480 SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.572 arrival time 0.218 ------------------------------------------------------------------- slack 0.790 Slack (MET) : 0.790ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.218 -0.480 SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.572 arrival time 0.218 ------------------------------------------------------------------- slack 0.790 Slack (MET) : 0.790ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.218 -0.480 SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.572 arrival time 0.218 ------------------------------------------------------------------- slack 0.790 Slack (MET) : 0.790ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.218 -0.480 SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.572 arrival time 0.218 ------------------------------------------------------------------- slack 0.790 Slack (MET) : 0.790ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.218 -0.480 SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.572 arrival time 0.218 ------------------------------------------------------------------- slack 0.790 Slack (MET) : 0.808ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.221 -0.482 SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.574 arrival time 0.234 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.221 -0.482 SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.574 arrival time 0.234 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.221 -0.482 SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.574 arrival time 0.234 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.221 -0.482 SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.574 arrival time 0.234 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.221 -0.482 SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.574 arrival time 0.234 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.221 -0.482 SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.574 arrival time 0.234 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.381 -0.468 SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.196 -0.457 SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 0.524 arrival time 0.329 ------------------------------------------------------------------- slack 0.853 Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.381 -0.468 SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.196 -0.457 SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 0.524 arrival time 0.329 ------------------------------------------------------------------- slack 0.853 Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.381 -0.468 SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.196 -0.457 SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 0.524 arrival time 0.329 ------------------------------------------------------------------- slack 0.853 Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.381 -0.468 SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.196 -0.457 SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 0.524 arrival time 0.329 ------------------------------------------------------------------- slack 0.853 Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.381 -0.468 SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.196 -0.457 SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 0.524 arrival time 0.329 ------------------------------------------------------------------- slack 0.853 Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.550 arrival time 0.310 ------------------------------------------------------------------- slack 0.860 Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.550 arrival time 0.310 ------------------------------------------------------------------- slack 0.860 Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.550 arrival time 0.310 ------------------------------------------------------------------- slack 0.860 Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.550 arrival time 0.310 ------------------------------------------------------------------- slack 0.860 Slack (MET) : 0.871ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.972%) route 0.548ns (69.028%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.262 0.299 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X9Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.218 -0.480 SLICE_X9Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.572 arrival time 0.299 ------------------------------------------------------------------- slack 0.871 Slack (MET) : 0.871ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.972%) route 0.548ns (69.028%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.262 0.299 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X9Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.218 -0.480 SLICE_X9Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.572 arrival time 0.299 ------------------------------------------------------------------- slack 0.871 Slack (MET) : 0.872ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.218 -0.479 SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.571 arrival time 0.301 ------------------------------------------------------------------- slack 0.872 Slack (MET) : 0.872ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.218 -0.479 SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.571 arrival time 0.301 ------------------------------------------------------------------- slack 0.872 Slack (MET) : 0.872ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.218 -0.479 SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.571 arrival time 0.301 ------------------------------------------------------------------- slack 0.872 Slack (MET) : 0.890ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.864ns (logic 0.186ns (21.517%) route 0.678ns (78.483%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 0.372 0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in SLICE_X112Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism -0.192 -0.572 SLICE_X112Y66 FDCE (Remov_fdce_C_CLR) -0.067 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0] ------------------------------------------------------------------- required time 0.639 arrival time 0.251 ------------------------------------------------------------------- slack 0.890 Slack (MET) : 0.914ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.786ns (logic 0.249ns (31.687%) route 0.537ns (68.313%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.377ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.371 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X125Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.570 -0.377 clock pessimism -0.192 -0.569 SLICE_X125Y65 FDCE (Remov_fdce_C_CLR) -0.165 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253] ------------------------------------------------------------------- required time 0.734 arrival time 0.179 ------------------------------------------------------------------- slack 0.914 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.381 -0.468 SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.381 -0.468 SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.381 -0.468 SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.381 -0.468 SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.381 -0.468 SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.381 -0.468 SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.381 -0.468 SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.381 -0.468 SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.196 -0.457 SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.549 arrival time 0.368 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.196 -0.457 SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.549 arrival time 0.368 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.196 -0.457 SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.549 arrival time 0.368 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.196 -0.457 SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 0.549 arrival time 0.368 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.918ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 1.021ns (logic 0.246ns (24.092%) route 0.775ns (75.908%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.336ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.489 0.526 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X11Y53 FDCE f u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.611 -0.336 clock pessimism 0.037 -0.299 SLICE_X11Y53 FDCE (Remov_fdce_C_CLR) -0.092 -0.391 u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.391 arrival time 0.526 ------------------------------------------------------------------- slack 0.918 Slack (MET) : 0.928ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.218 -0.479 SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.571 arrival time 0.357 ------------------------------------------------------------------- slack 0.928 Slack (MET) : 0.928ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.218 -0.479 SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.571 arrival time 0.357 ------------------------------------------------------------------- slack 0.928 Slack (MET) : 0.928ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.218 -0.479 SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.571 arrival time 0.357 ------------------------------------------------------------------- slack 0.928 Slack (MET) : 0.928ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.218 -0.479 SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.571 arrival time 0.357 ------------------------------------------------------------------- slack 0.928 Slack (MET) : 0.932ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.817ns (logic 0.249ns (30.489%) route 0.568ns (69.511%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.025ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.402 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X112Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.558 -0.389 clock pessimism -0.192 -0.581 SLICE_X112Y75 FDCE (Remov_fdce_C_CLR) -0.140 -0.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10] ------------------------------------------------------------------- required time 0.721 arrival time 0.210 ------------------------------------------------------------------- slack 0.932 Slack (MET) : 0.935ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism -0.192 -0.571 SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0] ------------------------------------------------------------------- required time 0.638 arrival time 0.297 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism -0.192 -0.571 SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1] ------------------------------------------------------------------- required time 0.638 arrival time 0.297 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism -0.192 -0.571 SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2] ------------------------------------------------------------------- required time 0.638 arrival time 0.297 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism -0.192 -0.571 SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3] ------------------------------------------------------------------- required time 0.638 arrival time 0.297 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.944ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.815ns (logic 0.249ns (30.565%) route 0.566ns (69.435%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.400 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X127Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.569 -0.378 clock pessimism -0.192 -0.570 SLICE_X127Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217] ------------------------------------------------------------------- required time 0.735 arrival time 0.208 ------------------------------------------------------------------- slack 0.944 Slack (MET) : 0.944ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.815ns (logic 0.249ns (30.565%) route 0.566ns (69.435%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.400 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X127Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.569 -0.378 clock pessimism -0.192 -0.570 SLICE_X127Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223] ------------------------------------------------------------------- required time 0.735 arrival time 0.208 ------------------------------------------------------------------- slack 0.944 Slack (MET) : 0.947ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.819ns (logic 0.211ns (25.751%) route 0.608ns (74.249%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.377ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.164 -0.442 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q net (fo=8, routed) 0.237 -0.205 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.047 -0.158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.371 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X125Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.570 -0.377 clock pessimism -0.192 -0.569 SLICE_X125Y65 FDCE (Remov_fdce_C_CLR) -0.165 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253] ------------------------------------------------------------------- required time 0.734 arrival time 0.213 ------------------------------------------------------------------- slack 0.947 Slack (MET) : 0.948ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.569 -0.378 clock pessimism -0.192 -0.570 SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233] ------------------------------------------------------------------- required time 0.735 arrival time 0.213 ------------------------------------------------------------------- slack 0.948 Slack (MET) : 0.948ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.569 -0.378 clock pessimism -0.192 -0.570 SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234] ------------------------------------------------------------------- required time 0.735 arrival time 0.213 ------------------------------------------------------------------- slack 0.948 Slack (MET) : 0.948ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.569 -0.378 clock pessimism -0.192 -0.570 SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236] ------------------------------------------------------------------- required time 0.735 arrival time 0.213 ------------------------------------------------------------------- slack 0.948 Slack (MET) : 0.948ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.569 -0.378 clock pessimism -0.192 -0.570 SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237] ------------------------------------------------------------------- required time 0.735 arrival time 0.213 ------------------------------------------------------------------- slack 0.948 Slack (MET) : 0.948ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.569 -0.378 clock pessimism -0.192 -0.570 SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239] ------------------------------------------------------------------- required time 0.735 arrival time 0.213 ------------------------------------------------------------------- slack 0.948 Slack (MET) : 0.952ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.822ns (logic 0.249ns (30.308%) route 0.573ns (69.692%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.407 0.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X125Y67 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism -0.192 -0.571 SLICE_X125Y67 FDCE (Remov_fdce_C_CLR) -0.165 -0.736 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37] ------------------------------------------------------------------- required time 0.736 arrival time 0.215 ------------------------------------------------------------------- slack 0.952 Slack (MET) : 0.955ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.925ns (logic 0.246ns (26.589%) route 0.679ns (73.411%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.393 0.430 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X12Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.525 arrival time 0.430 ------------------------------------------------------------------- slack 0.955 Slack (MET) : 0.955ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.925ns (logic 0.246ns (26.589%) route 0.679ns (73.411%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.354 -0.495 SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.393 0.430 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.685 -0.262 clock pessimism -0.196 -0.458 SLICE_X12Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.525 arrival time 0.430 ------------------------------------------------------------------- slack 0.955 Slack (MET) : 0.957ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.817ns (logic 0.249ns (30.489%) route 0.568ns (69.511%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.025ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.402 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X113Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.558 -0.389 clock pessimism -0.192 -0.581 SLICE_X113Y75 FDCE (Remov_fdce_C_CLR) -0.165 -0.746 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5] ------------------------------------------------------------------- required time 0.746 arrival time 0.210 ------------------------------------------------------------------- slack 0.957 Slack (MET) : 0.957ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.830ns (logic 0.249ns (29.992%) route 0.581ns (70.008%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.376ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.415 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X131Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.571 -0.376 clock pessimism -0.192 -0.568 SLICE_X131Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90] ------------------------------------------------------------------- required time 0.733 arrival time 0.224 ------------------------------------------------------------------- slack 0.957 Slack (MET) : 0.957ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.830ns (logic 0.249ns (29.992%) route 0.581ns (70.008%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.376ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.415 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X131Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.571 -0.376 clock pessimism -0.192 -0.568 SLICE_X131Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93] ------------------------------------------------------------------- required time 0.733 arrival time 0.224 ------------------------------------------------------------------- slack 0.957 Slack (MET) : 0.960ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in SLICE_X113Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism -0.192 -0.571 SLICE_X113Y65 FDCE (Remov_fdce_C_CLR) -0.092 -0.663 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2] ------------------------------------------------------------------- required time 0.663 arrival time 0.297 ------------------------------------------------------------------- slack 0.960 Slack (MET) : 0.961ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.192 -0.575 SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1] ------------------------------------------------------------------- required time 0.740 arrival time 0.221 ------------------------------------------------------------------- slack 0.961 Slack (MET) : 0.961ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.192 -0.575 SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2] ------------------------------------------------------------------- required time 0.740 arrival time 0.221 ------------------------------------------------------------------- slack 0.961 Slack (MET) : 0.961ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.192 -0.575 SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3] ------------------------------------------------------------------- required time 0.740 arrival time 0.221 ------------------------------------------------------------------- slack 0.961 Slack (MET) : 0.961ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.192 -0.575 SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4] ------------------------------------------------------------------- required time 0.740 arrival time 0.221 ------------------------------------------------------------------- slack 0.961 Slack (MET) : 0.961ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.192 -0.575 SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5] ------------------------------------------------------------------- required time 0.740 arrival time 0.221 ------------------------------------------------------------------- slack 0.961 Slack (MET) : 0.961ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[7]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.192 -0.575 SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[7] ------------------------------------------------------------------- required time 0.740 arrival time 0.221 ------------------------------------------------------------------- slack 0.961 Slack (MET) : 0.961ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[8]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.192 -0.575 SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[8] ------------------------------------------------------------------- required time 0.740 arrival time 0.221 ------------------------------------------------------------------- slack 0.961 Slack (MET) : 0.961ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[9]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.192 -0.575 SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[9] ------------------------------------------------------------------- required time 0.740 arrival time 0.221 ------------------------------------------------------------------- slack 0.961 Slack (MET) : 0.962ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[251]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.835ns (logic 0.249ns (29.836%) route 0.586ns (70.164%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.376ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.420 0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X130Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[251]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.571 -0.376 clock pessimism -0.192 -0.568 SLICE_X130Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[251] ------------------------------------------------------------------- required time 0.733 arrival time 0.228 ------------------------------------------------------------------- slack 0.962 Slack (MET) : 0.962ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[254]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.835ns (logic 0.249ns (29.836%) route 0.586ns (70.164%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.376ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.420 0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X130Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[254]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.571 -0.376 clock pessimism -0.192 -0.568 SLICE_X130Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[254] ------------------------------------------------------------------- required time 0.733 arrival time 0.228 ------------------------------------------------------------------- slack 0.962 Slack (MET) : 0.965ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[104]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.376ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[104]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.571 -0.376 clock pessimism -0.192 -0.568 SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[104] ------------------------------------------------------------------- required time 0.708 arrival time 0.256 ------------------------------------------------------------------- slack 0.965 Slack (MET) : 0.965ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[105]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.376ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[105]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.571 -0.376 clock pessimism -0.192 -0.568 SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[105] ------------------------------------------------------------------- required time 0.708 arrival time 0.256 ------------------------------------------------------------------- slack 0.965 Slack (MET) : 0.965ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[106]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.376ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[106]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.571 -0.376 clock pessimism -0.192 -0.568 SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[106] ------------------------------------------------------------------- required time 0.708 arrival time 0.256 ------------------------------------------------------------------- slack 0.965 Slack (MET) : 0.965ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[107]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.376ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[107]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.571 -0.376 clock pessimism -0.192 -0.568 SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[107] ------------------------------------------------------------------- required time 0.708 arrival time 0.256 ------------------------------------------------------------------- slack 0.965 Slack (MET) : 0.965ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[108]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.376ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[108]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.571 -0.376 clock pessimism -0.192 -0.568 SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[108] ------------------------------------------------------------------- required time 0.708 arrival time 0.256 ------------------------------------------------------------------- slack 0.965 Slack (MET) : 0.965ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[109]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.376ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[109]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.571 -0.376 clock pessimism -0.192 -0.568 SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[109] ------------------------------------------------------------------- required time 0.708 arrival time 0.256 ------------------------------------------------------------------- slack 0.965 Slack (MET) : 0.965ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[110]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.376ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[110]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.571 -0.376 clock pessimism -0.192 -0.568 SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[110] ------------------------------------------------------------------- required time 0.708 arrival time 0.256 ------------------------------------------------------------------- slack 0.965 Slack (MET) : 0.965ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[111]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.376ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[111]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.571 -0.376 clock pessimism -0.192 -0.568 SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[111] ------------------------------------------------------------------- required time 0.708 arrival time 0.256 ------------------------------------------------------------------- slack 0.965 Slack (MET) : 0.965ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.850ns (logic 0.211ns (24.816%) route 0.639ns (75.184%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.025ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.242 -0.606 SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.164 -0.442 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q net (fo=8, routed) 0.237 -0.205 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.047 -0.158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.402 0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X112Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.558 -0.389 clock pessimism -0.192 -0.581 SLICE_X112Y75 FDCE (Remov_fdce_C_CLR) -0.140 -0.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10] ------------------------------------------------------------------- required time 0.721 arrival time 0.244 ------------------------------------------------------------------- slack 0.965 Slack (MET) : 0.970ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.196 -0.457 SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.549 arrival time 0.421 ------------------------------------------------------------------- slack 0.970 Slack (MET) : 0.970ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.196 -0.457 SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.549 arrival time 0.421 ------------------------------------------------------------------- slack 0.970 Slack (MET) : 0.970ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.196 -0.457 SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.549 arrival time 0.421 ------------------------------------------------------------------- slack 0.970 Slack (MET) : 0.970ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.352 -0.497 SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.686 -0.261 clock pessimism -0.196 -0.457 SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.549 arrival time 0.421 ------------------------------------------------------------------- slack 0.970 ======= 1.470 -0.477 clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.939ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[55]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.140ns (logic 0.226ns (19.816%) route 0.914ns (80.184%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.744 0.461 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/delay_reg[1] SLICE_X98Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[55]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism 0.040 -0.345 SLICE_X98Y91 FDCE (Remov_fdce_C_CLR) -0.134 -0.479 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[55] ------------------------------------------------------------------- required time 0.479 arrival time 0.461 ------------------------------------------------------------------- slack 0.939 Slack (MET) : 0.942ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[54]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.141ns (logic 0.226ns (19.800%) route 0.915ns (80.200%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.745 0.461 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X92Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[54]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.040 -0.347 SLICE_X92Y90 FDCE (Remov_fdce_C_CLR) -0.134 -0.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[54] ------------------------------------------------------------------- required time 0.481 arrival time 0.461 ------------------------------------------------------------------- slack 0.942 Slack (MET) : 0.948ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.122ns (logic 0.190ns (16.937%) route 0.932ns (83.063%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q net (fo=8, routed) 0.249 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[0] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I3 SLICE_X95Y102 LUT5 (Prop_lut5_I3_O) 0.049 -0.241 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.683 0.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.040 -0.347 SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15] ------------------------------------------------------------------- required time 0.506 arrival time 0.442 ------------------------------------------------------------------- slack 0.948 Slack (MET) : 0.948ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.122ns (logic 0.190ns (16.937%) route 0.932ns (83.063%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q net (fo=8, routed) 0.249 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[0] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I3 SLICE_X95Y102 LUT5 (Prop_lut5_I3_O) 0.049 -0.241 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.683 0.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.040 -0.347 SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53] ------------------------------------------------------------------- required time 0.506 arrival time 0.442 ------------------------------------------------------------------- slack 0.948 Slack (MET) : 0.952ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[25]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.148ns (logic 0.226ns (19.693%) route 0.922ns (80.307%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.751 0.468 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X90Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.557 -0.390 clock pessimism 0.040 -0.350 SLICE_X90Y91 FDCE (Remov_fdce_C_CLR) -0.134 -0.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[25] ------------------------------------------------------------------- required time 0.484 arrival time 0.468 ------------------------------------------------------------------- slack 0.952 Slack (MET) : 0.952ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[56]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.148ns (logic 0.226ns (19.693%) route 0.922ns (80.307%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.751 0.468 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X90Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[56]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.557 -0.390 clock pessimism 0.040 -0.350 SLICE_X90Y91 FDCE (Remov_fdce_C_CLR) -0.134 -0.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[56] ------------------------------------------------------------------- required time 0.484 arrival time 0.468 ------------------------------------------------------------------- slack 0.952 Slack (MET) : 0.952ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.157ns (logic 0.206ns (17.801%) route 0.951ns (82.199%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.735 0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.040 -0.341 SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16] ------------------------------------------------------------------- required time 0.475 arrival time 0.477 ------------------------------------------------------------------- slack 0.952 Slack (MET) : 0.952ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.157ns (logic 0.206ns (17.801%) route 0.951ns (82.199%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.735 0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.040 -0.341 SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17] ------------------------------------------------------------------- required time 0.475 arrival time 0.477 ------------------------------------------------------------------- slack 0.952 Slack (MET) : 0.952ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.157ns (logic 0.206ns (17.801%) route 0.951ns (82.199%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.735 0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.040 -0.341 SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18] ------------------------------------------------------------------- required time 0.475 arrival time 0.477 ------------------------------------------------------------------- slack 0.952 Slack (MET) : 0.952ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.157ns (logic 0.206ns (17.801%) route 0.951ns (82.199%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.735 0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.040 -0.341 SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19] ------------------------------------------------------------------- required time 0.475 arrival time 0.477 ------------------------------------------------------------------- slack 0.952 Slack (MET) : 0.956ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[12]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X103Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[12]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X103Y98 FDCE (Remov_fdce_C_CLR) -0.159 -0.498 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[12] ------------------------------------------------------------------- required time 0.498 arrival time 0.458 ------------------------------------------------------------------- slack 0.956 Slack (MET) : 0.956ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[13]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X103Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X103Y98 FDCE (Remov_fdce_C_CLR) -0.159 -0.498 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[13] ------------------------------------------------------------------- required time 0.498 arrival time 0.458 ------------------------------------------------------------------- slack 0.956 Slack (MET) : 0.956ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[19]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X103Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X103Y98 FDCE (Remov_fdce_C_CLR) -0.159 -0.498 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[19] ------------------------------------------------------------------- required time 0.498 arrival time 0.458 ------------------------------------------------------------------- slack 0.956 Slack (MET) : 0.956ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.163ns (logic 0.206ns (17.713%) route 0.957ns (82.287%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0] ------------------------------------------------------------------- required time 0.473 arrival time 0.483 ------------------------------------------------------------------- slack 0.956 Slack (MET) : 0.956ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.163ns (logic 0.206ns (17.713%) route 0.957ns (82.287%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16] ------------------------------------------------------------------- required time 0.473 arrival time 0.483 ------------------------------------------------------------------- slack 0.956 Slack (MET) : 0.956ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.163ns (logic 0.206ns (17.713%) route 0.957ns (82.287%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17] ------------------------------------------------------------------- required time 0.473 arrival time 0.483 ------------------------------------------------------------------- slack 0.956 Slack (MET) : 0.956ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.163ns (logic 0.206ns (17.713%) route 0.957ns (82.287%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.168 -0.680 SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.040 -0.339 SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18] ------------------------------------------------------------------- required time 0.473 arrival time 0.483 ------------------------------------------------------------------- slack 0.956 >>>>>>> Stashed changes