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  rtl [label="RTL 静态检查\nVerilator lint"];
  unit [label="模块级仿真\n协议、边界、反压"];
  soc [label="SoC 仿真\nCPU + AXI + 加速器"];
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  board [label="板级回归\n正确性 + 实测耗时"];
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