Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 | Date : Sat Jul 11 09:34:15 2026 | Host : fedora running 64-bit unknown | Command : report_timing_summary -delay_type max -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_summary_full.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 38 input ports with no input delay specified. (HIGH) UART_RX UART_TX dip_sw[0] dip_sw[10] dip_sw[11] dip_sw[12] dip_sw[13] dip_sw[14] dip_sw[15] dip_sw[16] dip_sw[17] dip_sw[18] dip_sw[19] dip_sw[1] dip_sw[20] dip_sw[21] dip_sw[22] dip_sw[23] dip_sw[24] dip_sw[25] dip_sw[26] dip_sw[27] dip_sw[28] dip_sw[29] dip_sw[2] dip_sw[30] dip_sw[31] dip_sw[3] dip_sw[4] dip_sw[5] dip_sw[6] dip_sw[7] dip_sw[8] dip_sw[9] touch_btn[0] touch_btn[1] touch_btn[2] touch_btn[3] There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 40 ports with no output delay specified. (HIGH) UART_RX UART_TX dpy0[0] dpy0[1] dpy0[2] dpy0[3] dpy0[4] dpy0[5] dpy0[6] dpy0[7] dpy1[0] dpy1[1] dpy1[2] dpy1[3] dpy1[4] dpy1[5] dpy1[6] dpy1[7] leds[0] leds[10] leds[11] leds[12] leds[13] leds[14] leds[15] leds[1] leds[2] leds[3] leds[4] leds[5] leds[6] leds[7] leds[8] leds[9] video_de video_hsync video_red[0] video_red[1] video_red[2] video_vsync There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.070 0.000 0 88843 5.250 0.000 0 33736 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk {0.000 10.000} 20.000 50.000 clkfbout_clk_pll {0.000 10.000} 20.000 50.000 cpu_clk {0.000 15.000} 30.000 33.333 mlkem_clk {0.000 6.500} 13.000 76.923 sys_clk {0.000 10.000} 20.000 50.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk 7.000 0.000 0 1 clkfbout_clk_pll 17.845 0.000 0 3 cpu_clk 0.737 0.000 0 17197 13.750 0.000 0 6486 mlkem_clk 0.070 0.000 0 31646 5.250 0.000 0 17274 sys_clk 0.125 0.000 0 22307 8.750 0.000 0 9972 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- **async_default** cpu_clk cpu_clk 26.018 0.000 0 67 **async_default** mlkem_clk mlkem_clk 3.826 0.000 0 16740 **async_default** sys_clk sys_clk 6.335 0.000 0 886 ------------------------------------------------------------------------------------------------ | User Ignored Path Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) sys_clk cpu_clk (none) sys_clk mlkem_clk (none) cpu_clk sys_clk (none) mlkem_clk sys_clk ------------------------------------------------------------------------------------------------ | Unconstrained Path Table | ------------------------ ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) clkfbout_clk_pll (none) sys_clk (none) sys_clk ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk To Clock: clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { clk } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_pll To Clock: clkfbout_clk_pll Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_pll Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y19 pll_clk.u_clk_pll/inst/clkf_buf/I Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT --------------------------------------------------------------------------------------------------- From Clock: cpu_clk To Clock: cpu_clk Setup : 0 Failing Endpoints, Worst Slack 0.737ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 13.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.737ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2 SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0 SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139] SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] ------------------------------------------------------------------- required time 27.175 arrival time -26.438 ------------------------------------------------------------------- slack 0.737 Slack (MET) : 0.754ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6 SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143] SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.720 u_cpu/exe_stage/cpu_clk SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/C clock pessimism -0.514 27.207 clock uncertainty -0.113 27.093 SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] ------------------------------------------------------------------- required time 27.124 arrival time -26.370 ------------------------------------------------------------------- slack 0.754 Slack (MET) : 0.793ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0 SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0 SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136] SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] ------------------------------------------------------------------- required time 27.177 arrival time -26.384 ------------------------------------------------------------------- slack 0.793 Slack (MET) : 0.803ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118] SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] ------------------------------------------------------------------- required time 27.125 arrival time -26.322 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.804ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2 SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 27.172 arrival time -26.369 ------------------------------------------------------------------- slack 0.804 Slack (MET) : 0.863ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0 SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0 SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135] SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] ------------------------------------------------------------------- required time 27.173 arrival time -26.311 ------------------------------------------------------------------- slack 0.863 Slack (MET) : 0.865ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%)) Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114] SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] ------------------------------------------------------------------- required time 27.126 arrival time -26.261 ------------------------------------------------------------------- slack 0.865 Slack (MET) : 0.867ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.720 u_cpu/exe_stage/cpu_clk SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/C clock pessimism -0.514 27.207 clock uncertainty -0.113 27.093 SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 27.122 arrival time -26.255 ------------------------------------------------------------------- slack 0.867 Slack (MET) : 0.894ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%)) Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171] SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121] SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] ------------------------------------------------------------------- required time 27.127 arrival time -26.233 ------------------------------------------------------------------- slack 0.894 Slack (MET) : 0.921ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%)) Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172] SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172] SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122] SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/C clock pessimism -0.514 27.208 clock uncertainty -0.113 27.094 SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] ------------------------------------------------------------------- required time 27.125 arrival time -26.204 ------------------------------------------------------------------- slack 0.921 Slack (MET) : 0.943ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.831ns (logic 8.005ns (27.765%) route 20.826ns (72.235%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=9 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.866 24.418 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 SLICE_X115Y152 LUT5 (Prop_lut5_I0_O) 0.326 24.744 r u_cpu/u_csr/ds_to_es_bus_r[192]_i_9/O net (fo=1, routed) 0.415 25.158 u_cpu/id_stage/ds_to_es_bus_r_reg[192] SLICE_X111Y152 LUT4 (Prop_lut4_I3_O) 0.124 25.282 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_3/O net (fo=1, routed) 0.775 26.057 u_cpu/id_stage/ds_to_es_bus_r[192]_i_3_n_0 SLICE_X110Y159 LUT6 (Prop_lut6_I2_O) 0.124 26.181 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_1/O net (fo=1, routed) 0.000 26.181 u_cpu/exe_stage/ds_to_es_bus[142] SLICE_X110Y159 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.720 u_cpu/exe_stage/cpu_clk SLICE_X110Y159 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/C clock pessimism -0.514 27.207 clock uncertainty -0.113 27.093 SLICE_X110Y159 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[192] ------------------------------------------------------------------- required time 27.124 arrival time -26.181 ------------------------------------------------------------------- slack 0.943 Slack (MET) : 0.964ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.862ns (logic 7.809ns (27.057%) route 21.053ns (72.943%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.275ns = ( 27.725 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O net (fo=32, routed) 1.058 24.188 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_4 SLICE_X103Y151 LUT4 (Prop_lut4_I2_O) 0.124 24.312 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_7/O net (fo=1, routed) 0.590 24.902 u_cpu/id_stage/ds_to_es_bus_r[163]_i_7_n_0 SLICE_X102Y150 LUT5 (Prop_lut5_I4_O) 0.124 25.026 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_3/O net (fo=1, routed) 1.061 26.087 u_cpu/id_stage/ds_to_es_bus_r[163]_i_3_n_0 SLICE_X112Y150 LUT6 (Prop_lut6_I2_O) 0.124 26.211 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_1/O net (fo=1, routed) 0.000 26.211 u_cpu/exe_stage/ds_to_es_bus[113] SLICE_X112Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.554 27.725 u_cpu/exe_stage/cpu_clk SLICE_X112Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/C clock pessimism -0.514 27.212 clock uncertainty -0.113 27.098 SLICE_X112Y150 FDRE (Setup_fdre_C_D) 0.077 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[163] ------------------------------------------------------------------- required time 27.175 arrival time -26.211 ------------------------------------------------------------------- slack 0.964 Slack (MET) : 0.965ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.812ns (logic 8.005ns (27.784%) route 20.807ns (72.216%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.702 24.253 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 SLICE_X114Y154 LUT4 (Prop_lut4_I0_O) 0.326 24.579 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_7/O net (fo=1, routed) 0.772 25.352 u_cpu/id_stage/ds_to_es_bus_r[175]_i_7_n_0 SLICE_X112Y154 LUT4 (Prop_lut4_I2_O) 0.124 25.476 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_3/O net (fo=1, routed) 0.561 26.037 u_cpu/id_stage/ds_to_es_bus_r[175]_i_3_n_0 SLICE_X111Y153 LUT6 (Prop_lut6_I2_O) 0.124 26.161 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O net (fo=1, routed) 0.000 26.161 u_cpu/exe_stage/ds_to_es_bus[125] SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X111Y153 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- required time 27.126 arrival time -26.161 ------------------------------------------------------------------- slack 0.965 Slack (MET) : 1.001ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.774ns (logic 7.809ns (27.139%) route 20.965ns (72.861%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O net (fo=15, routed) 0.935 25.244 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 SLICE_X117Y151 LUT6 (Prop_lut6_I0_O) 0.124 25.368 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_2/O net (fo=1, routed) 0.631 26.000 u_cpu/id_stage/ds_to_es_bus_r[178]_i_2_n_0 SLICE_X110Y156 LUT6 (Prop_lut6_I1_O) 0.124 26.124 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O net (fo=1, routed) 0.000 26.124 u_cpu/exe_stage/ds_to_es_bus[128] SLICE_X110Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk SLICE_X110Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X110Y156 FDRE (Setup_fdre_C_D) 0.029 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- required time 27.124 arrival time -26.124 ------------------------------------------------------------------- slack 1.001 Slack (MET) : 1.021ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.754ns (logic 7.809ns (27.158%) route 20.945ns (72.842%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 SLICE_X112Y150 LUT4 (Prop_lut4_I2_O) 0.124 25.241 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_2/O net (fo=1, routed) 0.738 25.979 u_cpu/id_stage/ds_to_es_bus_r[170]_i_2_n_0 SLICE_X111Y153 LUT6 (Prop_lut6_I1_O) 0.124 26.103 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O net (fo=1, routed) 0.000 26.103 u_cpu/exe_stage/ds_to_es_bus[120] SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X111Y153 FDRE (Setup_fdre_C_D) 0.029 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] ------------------------------------------------------------------- required time 27.124 arrival time -26.103 ------------------------------------------------------------------- slack 1.021 Slack (MET) : 1.037ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.784ns (logic 8.012ns (27.834%) route 20.772ns (72.165%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.761 24.317 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X112Y155 LUT5 (Prop_lut5_I0_O) 0.332 24.649 r u_cpu/u_csr/ds_to_es_bus_r[182]_i_8/O net (fo=1, routed) 0.667 25.316 u_cpu/id_stage/ds_to_es_bus_r_reg[182] SLICE_X112Y154 LUT6 (Prop_lut6_I1_O) 0.124 25.440 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_2/O net (fo=1, routed) 0.569 26.010 u_cpu/id_stage/ds_to_es_bus_r[182]_i_2_n_0 SLICE_X108Y157 LUT6 (Prop_lut6_I1_O) 0.124 26.134 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_1/O net (fo=1, routed) 0.000 26.134 u_cpu/exe_stage/ds_to_es_bus[132] SLICE_X108Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk SLICE_X108Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/C clock pessimism -0.514 27.208 clock uncertainty -0.113 27.094 SLICE_X108Y157 FDRE (Setup_fdre_C_D) 0.077 27.171 u_cpu/exe_stage/ds_to_es_bus_r_reg[182] ------------------------------------------------------------------- required time 27.171 arrival time -26.134 ------------------------------------------------------------------- slack 1.037 Slack (MET) : 1.065ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.709ns (logic 7.809ns (27.200%) route 20.900ns (72.800%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O net (fo=15, routed) 0.884 25.193 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 SLICE_X117Y153 LUT6 (Prop_lut6_I3_O) 0.124 25.317 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_3/O net (fo=1, routed) 0.617 25.935 u_cpu/id_stage/ds_to_es_bus_r[187]_i_3_n_0 SLICE_X111Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.059 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 26.059 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X111Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk SLICE_X111Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/C clock pessimism -0.514 27.208 clock uncertainty -0.113 27.094 SLICE_X111Y158 FDRE (Setup_fdre_C_D) 0.029 27.123 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 27.123 arrival time -26.059 ------------------------------------------------------------------- slack 1.065 Slack (MET) : 1.081ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.695ns (logic 8.005ns (27.897%) route 20.690ns (72.103%)) Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.124 23.557 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 0.657 24.214 u_cpu/u_csr/ds_to_es_bus_r[166]_i_4_0 SLICE_X112Y151 LUT2 (Prop_lut2_I1_O) 0.116 24.330 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_8/O net (fo=1, routed) 0.808 25.138 u_cpu/u_csr/ds_to_es_bus_r[165]_i_8_n_0 SLICE_X111Y151 LUT6 (Prop_lut6_I0_O) 0.328 25.466 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O net (fo=1, routed) 0.455 25.920 u_cpu/id_stage/ds_to_es_bus_r_reg[165] SLICE_X109Y151 LUT6 (Prop_lut6_I3_O) 0.124 26.044 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 26.044 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 27.125 arrival time -26.044 ------------------------------------------------------------------- slack 1.081 Slack (MET) : 1.086ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.690ns (logic 8.012ns (27.926%) route 20.678ns (72.074%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.950 24.506 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X115Y152 LUT5 (Prop_lut5_I1_O) 0.332 24.838 r u_cpu/u_csr/ds_to_es_bus_r[180]_i_8/O net (fo=1, routed) 0.451 25.289 u_cpu/id_stage/ds_to_es_bus_r_reg[180] SLICE_X113Y152 LUT6 (Prop_lut6_I1_O) 0.124 25.413 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_2/O net (fo=1, routed) 0.502 25.916 u_cpu/id_stage/ds_to_es_bus_r[180]_i_2_n_0 SLICE_X110Y158 LUT6 (Prop_lut6_I1_O) 0.124 26.040 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/O net (fo=1, routed) 0.000 26.040 u_cpu/exe_stage/ds_to_es_bus[130] SLICE_X110Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk SLICE_X110Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/C clock pessimism -0.514 27.208 clock uncertainty -0.113 27.094 SLICE_X110Y158 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[180] ------------------------------------------------------------------- required time 27.125 arrival time -26.040 ------------------------------------------------------------------- slack 1.086 Slack (MET) : 1.129ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.694ns (logic 8.012ns (27.922%) route 20.682ns (72.078%)) Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O net (fo=32, routed) 0.922 24.333 u_cpu/u_csr/ds_to_es_bus_r_reg[166]_0 SLICE_X111Y151 LUT2 (Prop_lut2_I1_O) 0.119 24.452 r u_cpu/u_csr/ds_to_es_bus_r[167]_i_9/O net (fo=1, routed) 0.505 24.957 u_cpu/id_stage/ds_to_es_bus_r_reg[167] SLICE_X110Y151 LUT6 (Prop_lut6_I5_O) 0.332 25.289 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_3/O net (fo=1, routed) 0.631 25.920 u_cpu/id_stage/ds_to_es_bus_r[167]_i_3_n_0 SLICE_X108Y152 LUT6 (Prop_lut6_I2_O) 0.124 26.044 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 26.044 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X108Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X108Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X108Y152 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 27.173 arrival time -26.044 ------------------------------------------------------------------- slack 1.129 Slack (MET) : 1.139ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.640ns (logic 7.809ns (27.266%) route 20.831ns (72.734%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.139ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.276ns = ( 27.724 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.369 23.528 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X100Y152 LUT6 (Prop_lut6_I1_O) 0.124 23.652 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O net (fo=29, routed) 1.525 25.177 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_2 SLICE_X115Y156 LUT5 (Prop_lut5_I3_O) 0.124 25.301 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O net (fo=1, routed) 0.564 25.865 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 SLICE_X113Y156 LUT6 (Prop_lut6_I3_O) 0.124 25.989 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O net (fo=1, routed) 0.000 25.989 u_cpu/exe_stage/ds_to_es_bus[127] SLICE_X113Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.553 27.724 u_cpu/exe_stage/cpu_clk SLICE_X113Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/C clock pessimism -0.514 27.211 clock uncertainty -0.113 27.097 SLICE_X113Y156 FDRE (Setup_fdre_C_D) 0.031 27.128 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] ------------------------------------------------------------------- required time 27.128 arrival time -25.989 ------------------------------------------------------------------- slack 1.139 Slack (MET) : 1.143ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.683ns (logic 7.809ns (27.225%) route 20.874ns (72.775%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 0.799 25.021 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 SLICE_X113Y151 LUT6 (Prop_lut6_I5_O) 0.124 25.145 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_3/O net (fo=1, routed) 0.763 25.908 u_cpu/id_stage/ds_to_es_bus_r[188]_i_3_n_0 SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.032 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_1/O net (fo=1, routed) 0.000 26.032 u_cpu/exe_stage/ds_to_es_bus[138] SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[188] ------------------------------------------------------------------- required time 27.175 arrival time -26.032 ------------------------------------------------------------------- slack 1.143 Slack (MET) : 1.148ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.629ns (logic 7.809ns (27.276%) route 20.820ns (72.723%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O net (fo=15, routed) 0.941 25.251 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 SLICE_X116Y155 LUT4 (Prop_lut4_I0_O) 0.124 25.375 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_3/O net (fo=1, routed) 0.480 25.854 u_cpu/id_stage/ds_to_es_bus_r[184]_i_3_n_0 SLICE_X110Y156 LUT6 (Prop_lut6_I2_O) 0.124 25.978 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O net (fo=1, routed) 0.000 25.978 u_cpu/exe_stage/ds_to_es_bus[134] SLICE_X110Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk SLICE_X110Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X110Y156 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- required time 27.126 arrival time -25.978 ------------------------------------------------------------------- slack 1.148 Slack (MET) : 1.171ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.653ns (logic 7.809ns (27.254%) route 20.844ns (72.746%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 1.015 25.238 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 SLICE_X115Y150 LUT6 (Prop_lut6_I3_O) 0.124 25.362 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_2/O net (fo=1, routed) 0.516 25.878 u_cpu/id_stage/ds_to_es_bus_r[179]_i_2_n_0 SLICE_X112Y157 LUT5 (Prop_lut5_I1_O) 0.124 26.002 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_1/O net (fo=1, routed) 0.000 26.002 u_cpu/exe_stage/ds_to_es_bus[129] SLICE_X112Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X112Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X112Y157 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[179] ------------------------------------------------------------------- required time 27.173 arrival time -26.002 ------------------------------------------------------------------- slack 1.171 Slack (MET) : 1.184ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.639ns (logic 7.809ns (27.267%) route 20.830ns (72.733%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 0.606 24.829 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 SLICE_X112Y150 LUT4 (Prop_lut4_I0_O) 0.124 24.953 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_2/O net (fo=1, routed) 0.911 25.864 u_cpu/id_stage/ds_to_es_bus_r[174]_i_2_n_0 SLICE_X108Y154 LUT6 (Prop_lut6_I1_O) 0.124 25.988 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O net (fo=1, routed) 0.000 25.988 u_cpu/exe_stage/ds_to_es_bus[124] SLICE_X108Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk SLICE_X108Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X108Y154 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- required time 27.172 arrival time -25.988 ------------------------------------------------------------------- slack 1.184 Slack (MET) : 1.184ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[6][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.591ns (logic 7.135ns (24.956%) route 21.456ns (75.044%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.796 24.197 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X119Y184 LUT6 (Prop_lut6_I0_O) 0.124 24.321 r u_cpu/id_stage/btb_counter[6][1]_i_4/O net (fo=2, routed) 0.623 24.944 u_cpu/btb/btb_counter_reg[6][1]_0 SLICE_X120Y184 LUT3 (Prop_lut3_I1_O) 0.149 25.093 r u_cpu/btb/btb_counter[6][0]_i_2/O net (fo=1, routed) 0.492 25.585 u_cpu/btb/btb_counter[6][0]_i_2_n_0 SLICE_X121Y184 LUT6 (Prop_lut6_I0_O) 0.355 25.940 r u_cpu/btb/btb_counter[6][0]_i_1/O net (fo=1, routed) 0.000 25.940 u_cpu/btb/btb_counter[6][0]_i_1_n_0 SLICE_X121Y184 FDRE r u_cpu/btb/btb_counter_reg[6][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.720 u_cpu/btb/cpu_clk SLICE_X121Y184 FDRE r u_cpu/btb/btb_counter_reg[6][0]/C clock pessimism -0.514 27.207 clock uncertainty -0.113 27.093 SLICE_X121Y184 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/btb/btb_counter_reg[6][0] ------------------------------------------------------------------- required time 27.124 arrival time -25.940 ------------------------------------------------------------------- slack 1.184 Slack (MET) : 1.189ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.586ns (logic 7.809ns (27.317%) route 20.777ns (72.683%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O net (fo=32, routed) 0.901 24.031 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_4 SLICE_X100Y150 LUT6 (Prop_lut6_I0_O) 0.124 24.155 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_8/O net (fo=1, routed) 1.039 25.194 u_cpu/id_stage/ds_to_es_bus_r[162]_i_8_n_0 SLICE_X104Y150 LUT6 (Prop_lut6_I1_O) 0.124 25.318 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_4/O net (fo=1, routed) 0.493 25.812 u_cpu/id_stage/ds_to_es_bus_r[162]_i_4_n_0 SLICE_X105Y150 LUT6 (Prop_lut6_I2_O) 0.124 25.936 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_1/O net (fo=1, routed) 0.000 25.936 u_cpu/exe_stage/ds_to_es_bus[112] SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.029 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[162] ------------------------------------------------------------------- required time 27.124 arrival time -25.936 ------------------------------------------------------------------- slack 1.189 Slack (MET) : 1.194ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.581ns (logic 7.809ns (27.322%) route 20.772ns (72.678%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O net (fo=15, routed) 0.729 25.039 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 SLICE_X115Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.163 r u_cpu/id_stage/ds_to_es_bus_r[191]_i_2/O net (fo=1, routed) 0.644 25.807 u_cpu/id_stage/ds_to_es_bus_r[191]_i_2_n_0 SLICE_X109Y160 LUT6 (Prop_lut6_I1_O) 0.124 25.931 r u_cpu/id_stage/ds_to_es_bus_r[191]_i_1/O net (fo=1, routed) 0.000 25.931 u_cpu/exe_stage/ds_to_es_bus[141] SLICE_X109Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.720 u_cpu/exe_stage/cpu_clk SLICE_X109Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/C clock pessimism -0.514 27.207 clock uncertainty -0.113 27.093 SLICE_X109Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[191] ------------------------------------------------------------------- required time 27.124 arrival time -25.931 ------------------------------------------------------------------- slack 1.194 Slack (MET) : 1.202ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.624ns (logic 7.809ns (27.281%) route 20.815ns (72.719%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 0.886 25.109 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 SLICE_X112Y152 LUT6 (Prop_lut6_I5_O) 0.124 25.233 r u_cpu/id_stage/ds_to_es_bus_r[183]_i_2/O net (fo=1, routed) 0.617 25.849 u_cpu/id_stage/ds_to_es_bus_r[183]_i_2_n_0 SLICE_X108Y157 LUT6 (Prop_lut6_I1_O) 0.124 25.973 r u_cpu/id_stage/ds_to_es_bus_r[183]_i_1/O net (fo=1, routed) 0.000 25.973 u_cpu/exe_stage/ds_to_es_bus[133] SLICE_X108Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk SLICE_X108Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/C clock pessimism -0.514 27.208 clock uncertainty -0.113 27.094 SLICE_X108Y157 FDRE (Setup_fdre_C_D) 0.081 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[183] ------------------------------------------------------------------- required time 27.175 arrival time -25.973 ------------------------------------------------------------------- slack 1.202 Slack (MET) : 1.264ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[31][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.507ns (logic 7.107ns (24.931%) route 21.400ns (75.069%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.285ns = ( 27.715 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.681 24.083 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X122Y181 LUT6 (Prop_lut6_I5_O) 0.124 24.207 r u_cpu/id_stage/btb_counter[31][1]_i_7/O net (fo=2, routed) 0.737 24.944 u_cpu/btb/btb_counter_reg[31][1]_0 SLICE_X122Y180 LUT3 (Prop_lut3_I1_O) 0.150 25.094 r u_cpu/btb/btb_counter[31][0]_i_2/O net (fo=1, routed) 0.436 25.530 u_cpu/btb/btb_counter[31][0]_i_2_n_0 SLICE_X122Y180 LUT6 (Prop_lut6_I0_O) 0.326 25.856 r u_cpu/btb/btb_counter[31][0]_i_1/O net (fo=1, routed) 0.000 25.856 u_cpu/btb/btb_counter[31][0]_i_1_n_0 SLICE_X122Y180 FDRE r u_cpu/btb/btb_counter_reg[31][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.544 27.715 u_cpu/btb/cpu_clk SLICE_X122Y180 FDRE r u_cpu/btb/btb_counter_reg[31][0]/C clock pessimism -0.514 27.202 clock uncertainty -0.113 27.088 SLICE_X122Y180 FDRE (Setup_fdre_C_D) 0.032 27.120 u_cpu/btb/btb_counter_reg[31][0] ------------------------------------------------------------------- required time 27.120 arrival time -25.856 ------------------------------------------------------------------- slack 1.264 Slack (MET) : 1.268ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.505ns (logic 7.809ns (27.395%) route 20.696ns (72.605%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.493 23.007 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X102Y155 LUT6 (Prop_lut6_I0_O) 0.124 23.131 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 1.314 24.445 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X117Y155 LUT5 (Prop_lut5_I0_O) 0.124 24.569 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_7/O net (fo=1, routed) 0.584 25.153 u_cpu/id_stage/ds_to_es_bus_r[169]_i_7_n_0 SLICE_X110Y155 LUT5 (Prop_lut5_I2_O) 0.124 25.277 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_3/O net (fo=1, routed) 0.454 25.731 u_cpu/id_stage/ds_to_es_bus_r[169]_i_3_n_0 SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.124 25.855 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_1/O net (fo=1, routed) 0.000 25.855 u_cpu/exe_stage/ds_to_es_bus[119] SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/C clock pessimism -0.514 27.208 clock uncertainty -0.113 27.094 SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.029 27.123 u_cpu/exe_stage/ds_to_es_bus_r_reg[169] ------------------------------------------------------------------- required time 27.123 arrival time -25.855 ------------------------------------------------------------------- slack 1.268 Slack (MET) : 1.281ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.496ns (logic 7.809ns (27.404%) route 20.687ns (72.596%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.139ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.276ns = ( 27.724 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.632 23.146 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 LUT6 (Prop_lut6_I3_O) 0.124 23.270 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O net (fo=32, routed) 0.937 24.207 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 SLICE_X109Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.331 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_12/O net (fo=1, routed) 0.363 24.694 u_cpu/id_stage/ds_to_es_bus_r[176]_i_12_n_0 SLICE_X109Y155 LUT5 (Prop_lut5_I4_O) 0.124 24.818 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_5/O net (fo=1, routed) 0.903 25.721 u_cpu/id_stage/ds_to_es_bus_r[176]_i_5_n_0 SLICE_X113Y156 LUT6 (Prop_lut6_I4_O) 0.124 25.845 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O net (fo=1, routed) 0.000 25.845 u_cpu/exe_stage/ds_to_es_bus[126] SLICE_X113Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.553 27.724 u_cpu/exe_stage/cpu_clk SLICE_X113Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/C clock pessimism -0.514 27.211 clock uncertainty -0.113 27.097 SLICE_X113Y156 FDRE (Setup_fdre_C_D) 0.029 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- required time 27.126 arrival time -25.845 ------------------------------------------------------------------- slack 1.281 Slack (MET) : 1.307ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.470ns (logic 8.005ns (28.117%) route 20.465ns (71.883%)) Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.662 23.176 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.300 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_16/O net (fo=32, routed) 1.089 24.389 u_cpu/u_csr/ds_to_es_bus_r_reg[169] SLICE_X111Y152 LUT2 (Prop_lut2_I1_O) 0.118 24.507 r u_cpu/u_csr/ds_to_es_bus_r[166]_i_11/O net (fo=1, routed) 0.578 25.085 u_cpu/u_csr/ds_to_es_bus_r[166]_i_11_n_0 SLICE_X111Y151 LUT6 (Prop_lut6_I5_O) 0.326 25.411 r u_cpu/u_csr/ds_to_es_bus_r[166]_i_4/O net (fo=1, routed) 0.285 25.696 u_cpu/id_stage/ds_to_es_bus_r_reg[166] SLICE_X109Y151 LUT6 (Prop_lut6_I3_O) 0.124 25.820 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_1/O net (fo=1, routed) 0.000 25.820 u_cpu/exe_stage/ds_to_es_bus[116] SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[166] ------------------------------------------------------------------- required time 27.127 arrival time -25.820 ------------------------------------------------------------------- slack 1.307 Slack (MET) : 1.392ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[5][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.383ns (logic 7.115ns (25.068%) route 21.268ns (74.932%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.786 24.187 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X123Y184 LUT6 (Prop_lut6_I0_O) 0.124 24.311 r u_cpu/id_stage/btb_counter[5][1]_i_4/O net (fo=2, routed) 0.649 24.960 u_cpu/btb/btb_counter_reg[5][1]_0 SLICE_X122Y184 LUT3 (Prop_lut3_I1_O) 0.152 25.112 r u_cpu/btb/btb_counter[5][0]_i_2/O net (fo=1, routed) 0.288 25.400 u_cpu/btb/btb_counter[5][0]_i_2_n_0 SLICE_X122Y184 LUT6 (Prop_lut6_I0_O) 0.332 25.732 r u_cpu/btb/btb_counter[5][0]_i_1/O net (fo=1, routed) 0.000 25.732 u_cpu/btb/btb_counter[5][0]_i_1_n_0 SLICE_X122Y184 FDRE r u_cpu/btb/btb_counter_reg[5][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.720 u_cpu/btb/cpu_clk SLICE_X122Y184 FDRE r u_cpu/btb/btb_counter_reg[5][0]/C clock pessimism -0.514 27.207 clock uncertainty -0.113 27.093 SLICE_X122Y184 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/btb/btb_counter_reg[5][0] ------------------------------------------------------------------- required time 27.124 arrival time -25.732 ------------------------------------------------------------------- slack 1.392 Slack (MET) : 1.450ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.327ns (logic 7.809ns (27.568%) route 20.518ns (72.432%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.662 23.176 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.300 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_16/O net (fo=32, routed) 1.223 24.523 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_3 SLICE_X108Y153 LUT4 (Prop_lut4_I0_O) 0.124 24.647 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_12/O net (fo=1, routed) 0.498 25.145 u_cpu/id_stage/ds_to_es_bus_r[173]_i_12_n_0 SLICE_X109Y153 LUT6 (Prop_lut6_I1_O) 0.124 25.269 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_4/O net (fo=1, routed) 0.283 25.552 u_cpu/id_stage/ds_to_es_bus_r[173]_i_4_n_0 SLICE_X111Y153 LUT6 (Prop_lut6_I4_O) 0.124 25.676 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_1/O net (fo=1, routed) 0.000 25.676 u_cpu/exe_stage/ds_to_es_bus[123] SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X111Y153 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[173] ------------------------------------------------------------------- required time 27.126 arrival time -25.676 ------------------------------------------------------------------- slack 1.450 Slack (MET) : 1.497ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[28][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.272ns (logic 7.111ns (25.152%) route 21.161ns (74.848%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.285ns = ( 27.715 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.669 24.070 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X121Y181 LUT6 (Prop_lut6_I0_O) 0.124 24.194 r u_cpu/id_stage/btb_counter[28][1]_i_8/O net (fo=2, routed) 0.661 24.855 u_cpu/btb/btb_counter_reg[28][1]_0 SLICE_X122Y180 LUT3 (Prop_lut3_I1_O) 0.153 25.008 r u_cpu/btb/btb_counter[28][1]_i_2/O net (fo=1, routed) 0.287 25.295 u_cpu/btb/btb_counter[28][1]_i_2_n_0 SLICE_X121Y180 LUT6 (Prop_lut6_I0_O) 0.327 25.622 r u_cpu/btb/btb_counter[28][1]_i_1/O net (fo=1, routed) 0.000 25.622 u_cpu/btb/btb_counter[28][1]_i_1_n_0 SLICE_X121Y180 FDRE r u_cpu/btb/btb_counter_reg[28][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.544 27.715 u_cpu/btb/cpu_clk SLICE_X121Y180 FDRE r u_cpu/btb/btb_counter_reg[28][1]/C clock pessimism -0.514 27.202 clock uncertainty -0.113 27.088 SLICE_X121Y180 FDRE (Setup_fdre_C_D) 0.031 27.119 u_cpu/btb/btb_counter_reg[28][1] ------------------------------------------------------------------- required time 27.119 arrival time -25.622 ------------------------------------------------------------------- slack 1.497 Slack (MET) : 1.516ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[4][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.306ns (logic 7.129ns (25.185%) route 21.177ns (74.815%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.744 24.146 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X120Y182 LUT6 (Prop_lut6_I0_O) 0.124 24.270 r u_cpu/id_stage/btb_counter[4][1]_i_4/O net (fo=2, routed) 0.602 24.872 u_cpu/btb/btb_counter_reg[4][1]_0 SLICE_X120Y183 LUT3 (Prop_lut3_I1_O) 0.150 25.022 r u_cpu/btb/btb_counter[4][1]_i_2/O net (fo=1, routed) 0.286 25.308 u_cpu/btb/btb_counter[4][1]_i_2_n_0 SLICE_X120Y183 LUT6 (Prop_lut6_I0_O) 0.348 25.656 r u_cpu/btb/btb_counter[4][1]_i_1/O net (fo=1, routed) 0.000 25.656 u_cpu/btb/btb_counter[4][1]_i_1_n_0 SLICE_X120Y183 FDRE r u_cpu/btb/btb_counter_reg[4][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.548 27.719 u_cpu/btb/cpu_clk SLICE_X120Y183 FDRE r u_cpu/btb/btb_counter_reg[4][1]/C clock pessimism -0.514 27.206 clock uncertainty -0.113 27.092 SLICE_X120Y183 FDRE (Setup_fdre_C_D) 0.079 27.171 u_cpu/btb/btb_counter_reg[4][1] ------------------------------------------------------------------- required time 27.171 arrival time -25.656 ------------------------------------------------------------------- slack 1.516 Slack (MET) : 1.521ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[6][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.255ns (logic 7.082ns (25.065%) route 21.173ns (74.935%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.796 24.197 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X119Y184 LUT6 (Prop_lut6_I0_O) 0.124 24.321 r u_cpu/id_stage/btb_counter[6][1]_i_4/O net (fo=2, routed) 0.567 24.888 u_cpu/btb/btb_counter_reg[6][1]_0 SLICE_X121Y184 LUT3 (Prop_lut3_I1_O) 0.119 25.007 r u_cpu/btb/btb_counter[6][1]_i_2/O net (fo=1, routed) 0.266 25.272 u_cpu/btb/btb_counter[6][1]_i_2_n_0 SLICE_X121Y184 LUT6 (Prop_lut6_I0_O) 0.332 25.604 r u_cpu/btb/btb_counter[6][1]_i_1/O net (fo=1, routed) 0.000 25.604 u_cpu/btb/btb_counter[6][1]_i_1_n_0 SLICE_X121Y184 FDRE r u_cpu/btb/btb_counter_reg[6][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.720 u_cpu/btb/cpu_clk SLICE_X121Y184 FDRE r u_cpu/btb/btb_counter_reg[6][1]/C clock pessimism -0.514 27.207 clock uncertainty -0.113 27.093 SLICE_X121Y184 FDRE (Setup_fdre_C_D) 0.032 27.125 u_cpu/btb/btb_counter_reg[6][1] ------------------------------------------------------------------- required time 27.125 arrival time -25.604 ------------------------------------------------------------------- slack 1.521 Slack (MET) : 1.534ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[24][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.286ns (logic 6.879ns (24.320%) route 21.407ns (75.680%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.800 24.201 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X120Y183 LUT6 (Prop_lut6_I0_O) 0.124 24.325 r u_cpu/id_stage/btb_counter[24][1]_i_4/O net (fo=2, routed) 0.610 24.935 u_cpu/btb/btb_counter_reg[24][1]_0 SLICE_X120Y183 LUT3 (Prop_lut3_I1_O) 0.124 25.059 r u_cpu/btb/btb_counter[24][1]_i_2/O net (fo=1, routed) 0.452 25.511 u_cpu/btb/btb_counter[24][1]_i_2_n_0 SLICE_X120Y183 LUT6 (Prop_lut6_I0_O) 0.124 25.635 r u_cpu/btb/btb_counter[24][1]_i_1/O net (fo=1, routed) 0.000 25.635 u_cpu/btb/btb_counter[24][1]_i_1_n_0 SLICE_X120Y183 FDRE r u_cpu/btb/btb_counter_reg[24][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.548 27.719 u_cpu/btb/cpu_clk SLICE_X120Y183 FDRE r u_cpu/btb/btb_counter_reg[24][1]/C clock pessimism -0.514 27.206 clock uncertainty -0.113 27.092 SLICE_X120Y183 FDRE (Setup_fdre_C_D) 0.077 27.169 u_cpu/btb/btb_counter_reg[24][1] ------------------------------------------------------------------- required time 27.169 arrival time -25.635 ------------------------------------------------------------------- slack 1.534 Slack (MET) : 1.554ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[19][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.273ns (logic 6.879ns (24.331%) route 21.394ns (75.669%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.781 24.182 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X123Y184 LUT6 (Prop_lut6_I0_O) 0.124 24.306 r u_cpu/id_stage/btb_counter[19][1]_i_4/O net (fo=2, routed) 0.482 24.788 u_cpu/btb/btb_counter_reg[19][1]_0 SLICE_X123Y184 LUT3 (Prop_lut3_I1_O) 0.124 24.912 r u_cpu/btb/btb_counter[19][1]_i_2/O net (fo=1, routed) 0.586 25.498 u_cpu/btb/btb_counter[19][1]_i_2_n_0 SLICE_X124Y186 LUT6 (Prop_lut6_I0_O) 0.124 25.622 r u_cpu/btb/btb_counter[19][1]_i_1/O net (fo=1, routed) 0.000 25.622 u_cpu/btb/btb_counter[19][1]_i_1_n_0 SLICE_X124Y186 FDRE r u_cpu/btb/btb_counter_reg[19][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/btb/cpu_clk SLICE_X124Y186 FDRE r u_cpu/btb/btb_counter_reg[19][1]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X124Y186 FDRE (Setup_fdre_C_D) 0.081 27.176 u_cpu/btb/btb_counter_reg[19][1] ------------------------------------------------------------------- required time 27.176 arrival time -25.622 ------------------------------------------------------------------- slack 1.554 Slack (MET) : 1.569ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[30][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.200ns (logic 6.879ns (24.393%) route 21.321ns (75.607%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.147ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns = ( 27.716 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.723 24.124 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X122Y181 LUT6 (Prop_lut6_I0_O) 0.124 24.248 r u_cpu/id_stage/btb_counter[30][1]_i_6/O net (fo=2, routed) 0.621 24.869 u_cpu/btb/btb_counter_reg[30][1]_0 SLICE_X123Y181 LUT3 (Prop_lut3_I1_O) 0.124 24.993 r u_cpu/btb/btb_counter[30][1]_i_2/O net (fo=1, routed) 0.433 25.426 u_cpu/btb/btb_counter[30][1]_i_2_n_0 SLICE_X123Y181 LUT6 (Prop_lut6_I0_O) 0.124 25.550 r u_cpu/btb/btb_counter[30][1]_i_1/O net (fo=1, routed) 0.000 25.550 u_cpu/btb/btb_counter[30][1]_i_1_n_0 SLICE_X123Y181 FDRE r u_cpu/btb/btb_counter_reg[30][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.545 27.716 u_cpu/btb/cpu_clk SLICE_X123Y181 FDRE r u_cpu/btb/btb_counter_reg[30][1]/C clock pessimism -0.514 27.203 clock uncertainty -0.113 27.089 SLICE_X123Y181 FDRE (Setup_fdre_C_D) 0.029 27.118 u_cpu/btb/btb_counter_reg[30][1] ------------------------------------------------------------------- required time 27.118 arrival time -25.550 ------------------------------------------------------------------- slack 1.569 Slack (MET) : 1.573ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[31][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.194ns (logic 7.082ns (25.118%) route 21.112ns (74.882%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.285ns = ( 27.715 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.681 24.083 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X122Y181 LUT6 (Prop_lut6_I5_O) 0.124 24.207 r u_cpu/id_stage/btb_counter[31][1]_i_7/O net (fo=2, routed) 0.417 24.624 u_cpu/btb/btb_counter_reg[31][1]_0 SLICE_X123Y181 LUT3 (Prop_lut3_I1_O) 0.119 24.743 r u_cpu/btb/btb_counter[31][1]_i_2/O net (fo=1, routed) 0.469 25.212 u_cpu/btb/btb_counter[31][1]_i_2_n_0 SLICE_X123Y180 LUT6 (Prop_lut6_I0_O) 0.332 25.544 r u_cpu/btb/btb_counter[31][1]_i_1/O net (fo=1, routed) 0.000 25.544 u_cpu/btb/btb_counter[31][1]_i_1_n_0 SLICE_X123Y180 FDRE r u_cpu/btb/btb_counter_reg[31][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.544 27.715 u_cpu/btb/cpu_clk SLICE_X123Y180 FDRE r u_cpu/btb/btb_counter_reg[31][1]/C clock pessimism -0.514 27.202 clock uncertainty -0.113 27.088 SLICE_X123Y180 FDRE (Setup_fdre_C_D) 0.029 27.117 u_cpu/btb/btb_counter_reg[31][1] ------------------------------------------------------------------- required time 27.117 arrival time -25.544 ------------------------------------------------------------------- slack 1.573 Slack (MET) : 1.574ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[1][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.197ns (logic 6.879ns (24.396%) route 21.318ns (75.604%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.147ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns = ( 27.716 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.723 24.125 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X122Y182 LUT6 (Prop_lut6_I0_O) 0.124 24.249 r u_cpu/id_stage/btb_counter[1][1]_i_4/O net (fo=2, routed) 0.767 25.016 u_cpu/btb/btb_counter_reg[1][1]_0 SLICE_X122Y181 LUT3 (Prop_lut3_I1_O) 0.124 25.140 r u_cpu/btb/btb_counter[1][0]_i_2/O net (fo=1, routed) 0.282 25.423 u_cpu/btb/btb_counter[1][0]_i_2_n_0 SLICE_X121Y181 LUT6 (Prop_lut6_I0_O) 0.124 25.547 r u_cpu/btb/btb_counter[1][0]_i_1/O net (fo=1, routed) 0.000 25.547 u_cpu/btb/btb_counter[1][0]_i_1_n_0 SLICE_X121Y181 FDRE r u_cpu/btb/btb_counter_reg[1][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.545 27.716 u_cpu/btb/cpu_clk SLICE_X121Y181 FDRE r u_cpu/btb/btb_counter_reg[1][0]/C clock pessimism -0.514 27.203 clock uncertainty -0.113 27.089 SLICE_X121Y181 FDRE (Setup_fdre_C_D) 0.031 27.120 u_cpu/btb/btb_counter_reg[1][0] ------------------------------------------------------------------- required time 27.120 arrival time -25.547 ------------------------------------------------------------------- slack 1.574 Slack (MET) : 1.574ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[19][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.249ns (logic 6.879ns (24.351%) route 21.370ns (75.649%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.781 24.182 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X123Y184 LUT6 (Prop_lut6_I0_O) 0.124 24.306 r u_cpu/id_stage/btb_counter[19][1]_i_4/O net (fo=2, routed) 0.574 24.880 u_cpu/btb/btb_counter_reg[19][1]_0 SLICE_X123Y186 LUT3 (Prop_lut3_I1_O) 0.124 25.004 r u_cpu/btb/btb_counter[19][0]_i_2/O net (fo=1, routed) 0.471 25.474 u_cpu/btb/btb_counter[19][0]_i_2_n_0 SLICE_X124Y186 LUT6 (Prop_lut6_I0_O) 0.124 25.598 r u_cpu/btb/btb_counter[19][0]_i_1/O net (fo=1, routed) 0.000 25.598 u_cpu/btb/btb_counter[19][0]_i_1_n_0 SLICE_X124Y186 FDRE r u_cpu/btb/btb_counter_reg[19][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/btb/cpu_clk SLICE_X124Y186 FDRE r u_cpu/btb/btb_counter_reg[19][0]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X124Y186 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/btb/btb_counter_reg[19][0] ------------------------------------------------------------------- required time 27.172 arrival time -25.598 ------------------------------------------------------------------- slack 1.574 Slack (MET) : 1.574ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[26][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.199ns (logic 6.879ns (24.395%) route 21.320ns (75.605%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.727 24.128 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X122Y182 LUT6 (Prop_lut6_I0_O) 0.124 24.252 r u_cpu/id_stage/btb_counter[26][1]_i_4/O net (fo=2, routed) 0.604 24.856 u_cpu/btb/btb_counter_reg[26][1]_0 SLICE_X122Y184 LUT3 (Prop_lut3_I1_O) 0.124 24.980 r u_cpu/btb/btb_counter[26][0]_i_2/O net (fo=1, routed) 0.444 25.424 u_cpu/btb/btb_counter[26][0]_i_2_n_0 SLICE_X122Y184 LUT6 (Prop_lut6_I0_O) 0.124 25.548 r u_cpu/btb/btb_counter[26][0]_i_1/O net (fo=1, routed) 0.000 25.548 u_cpu/btb/btb_counter[26][0]_i_1_n_0 SLICE_X122Y184 FDRE r u_cpu/btb/btb_counter_reg[26][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.720 u_cpu/btb/cpu_clk SLICE_X122Y184 FDRE r u_cpu/btb/btb_counter_reg[26][0]/C clock pessimism -0.514 27.207 clock uncertainty -0.113 27.093 SLICE_X122Y184 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/btb/btb_counter_reg[26][0] ------------------------------------------------------------------- required time 27.122 arrival time -25.548 ------------------------------------------------------------------- slack 1.574 Slack (MET) : 1.584ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[14][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.190ns (logic 6.879ns (24.402%) route 21.311ns (75.598%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.661 24.063 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X124Y185 LUT6 (Prop_lut6_I5_O) 0.124 24.187 r u_cpu/id_stage/btb_counter[14][1]_i_4/O net (fo=2, routed) 0.672 24.859 u_cpu/btb/btb_counter_reg[14][1]_0 SLICE_X123Y185 LUT3 (Prop_lut3_I1_O) 0.124 24.983 r u_cpu/btb/btb_counter[14][1]_i_2/O net (fo=1, routed) 0.433 25.416 u_cpu/btb/btb_counter[14][1]_i_2_n_0 SLICE_X123Y185 LUT6 (Prop_lut6_I0_O) 0.124 25.540 r u_cpu/btb/btb_counter[14][1]_i_1/O net (fo=1, routed) 0.000 25.540 u_cpu/btb/btb_counter[14][1]_i_1_n_0 SLICE_X123Y185 FDRE r u_cpu/btb/btb_counter_reg[14][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.550 27.721 u_cpu/btb/cpu_clk SLICE_X123Y185 FDRE r u_cpu/btb/btb_counter_reg[14][1]/C clock pessimism -0.514 27.208 clock uncertainty -0.113 27.094 SLICE_X123Y185 FDRE (Setup_fdre_C_D) 0.029 27.123 u_cpu/btb/btb_counter_reg[14][1] ------------------------------------------------------------------- required time 27.123 arrival time -25.540 ------------------------------------------------------------------- slack 1.584 Slack (MET) : 1.587ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[26][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.186ns (logic 7.107ns (25.215%) route 21.079ns (74.785%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.282ns = ( 27.718 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.727 24.128 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X122Y182 LUT6 (Prop_lut6_I0_O) 0.124 24.252 r u_cpu/id_stage/btb_counter[26][1]_i_4/O net (fo=2, routed) 0.645 24.897 u_cpu/btb/btb_counter_reg[26][1]_0 SLICE_X122Y182 LUT3 (Prop_lut3_I1_O) 0.150 25.047 r u_cpu/btb/btb_counter[26][1]_i_2/O net (fo=1, routed) 0.162 25.209 u_cpu/btb/btb_counter[26][1]_i_2_n_0 SLICE_X122Y182 LUT6 (Prop_lut6_I0_O) 0.326 25.535 r u_cpu/btb/btb_counter[26][1]_i_1/O net (fo=1, routed) 0.000 25.535 u_cpu/btb/btb_counter[26][1]_i_1_n_0 SLICE_X122Y182 FDRE r u_cpu/btb/btb_counter_reg[26][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.718 u_cpu/btb/cpu_clk SLICE_X122Y182 FDRE r u_cpu/btb/btb_counter_reg[26][1]/C clock pessimism -0.514 27.205 clock uncertainty -0.113 27.091 SLICE_X122Y182 FDRE (Setup_fdre_C_D) 0.031 27.122 u_cpu/btb/btb_counter_reg[26][1] ------------------------------------------------------------------- required time 27.122 arrival time -25.535 ------------------------------------------------------------------- slack 1.587 Slack (MET) : 1.599ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[5][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.176ns (logic 7.107ns (25.223%) route 21.069ns (74.777%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.786 24.187 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X123Y184 LUT6 (Prop_lut6_I0_O) 0.124 24.311 r u_cpu/id_stage/btb_counter[5][1]_i_4/O net (fo=2, routed) 0.584 24.895 u_cpu/btb/btb_counter_reg[5][1]_0 SLICE_X123Y184 LUT3 (Prop_lut3_I1_O) 0.150 25.045 r u_cpu/btb/btb_counter[5][1]_i_2/O net (fo=1, routed) 0.154 25.200 u_cpu/btb/btb_counter[5][1]_i_2_n_0 SLICE_X123Y184 LUT6 (Prop_lut6_I0_O) 0.326 25.526 r u_cpu/btb/btb_counter[5][1]_i_1/O net (fo=1, routed) 0.000 25.526 u_cpu/btb/btb_counter[5][1]_i_1_n_0 SLICE_X123Y184 FDRE r u_cpu/btb/btb_counter_reg[5][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.720 u_cpu/btb/cpu_clk SLICE_X123Y184 FDRE r u_cpu/btb/btb_counter_reg[5][1]/C clock pessimism -0.514 27.207 clock uncertainty -0.113 27.093 SLICE_X123Y184 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/btb/btb_counter_reg[5][1] ------------------------------------------------------------------- required time 27.124 arrival time -25.526 ------------------------------------------------------------------- slack 1.599 Slack (MET) : 1.603ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[28][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.167ns (logic 6.879ns (24.422%) route 21.288ns (75.578%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.285ns = ( 27.715 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.669 24.070 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X121Y181 LUT6 (Prop_lut6_I0_O) 0.124 24.194 r u_cpu/id_stage/btb_counter[28][1]_i_8/O net (fo=2, routed) 0.632 24.827 u_cpu/btb/btb_counter_reg[28][1]_0 SLICE_X121Y182 LUT3 (Prop_lut3_I1_O) 0.124 24.951 r u_cpu/btb/btb_counter[28][0]_i_2/O net (fo=1, routed) 0.442 25.393 u_cpu/btb/btb_counter[28][0]_i_2_n_0 SLICE_X121Y180 LUT6 (Prop_lut6_I0_O) 0.124 25.517 r u_cpu/btb/btb_counter[28][0]_i_1/O net (fo=1, routed) 0.000 25.517 u_cpu/btb/btb_counter[28][0]_i_1_n_0 SLICE_X121Y180 FDRE r u_cpu/btb/btb_counter_reg[28][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.544 27.715 u_cpu/btb/cpu_clk SLICE_X121Y180 FDRE r u_cpu/btb/btb_counter_reg[28][0]/C clock pessimism -0.514 27.202 clock uncertainty -0.113 27.088 SLICE_X121Y180 FDRE (Setup_fdre_C_D) 0.031 27.119 u_cpu/btb/btb_counter_reg[28][0] ------------------------------------------------------------------- required time 27.119 arrival time -25.517 ------------------------------------------------------------------- slack 1.603 Slack (MET) : 1.636ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/btb_counter_reg[17][1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.137ns (logic 6.879ns (24.449%) route 21.258ns (75.551%)) Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O net (fo=49, routed) 0.636 24.037 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 SLICE_X123Y183 LUT6 (Prop_lut6_I0_O) 0.124 24.161 r u_cpu/id_stage/btb_counter[17][1]_i_4/O net (fo=2, routed) 0.644 24.805 u_cpu/btb/btb_counter_reg[17][1]_0 SLICE_X121Y184 LUT3 (Prop_lut3_I1_O) 0.124 24.929 r u_cpu/btb/btb_counter[17][1]_i_2/O net (fo=1, routed) 0.433 25.362 u_cpu/btb/btb_counter[17][1]_i_2_n_0 SLICE_X121Y184 LUT6 (Prop_lut6_I0_O) 0.124 25.486 r u_cpu/btb/btb_counter[17][1]_i_1/O net (fo=1, routed) 0.000 25.486 u_cpu/btb/btb_counter[17][1]_i_1_n_0 SLICE_X121Y184 FDRE r u_cpu/btb/btb_counter_reg[17][1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.720 u_cpu/btb/cpu_clk SLICE_X121Y184 FDRE r u_cpu/btb/btb_counter_reg[17][1]/C clock pessimism -0.514 27.207 clock uncertainty -0.113 27.093 SLICE_X121Y184 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/btb/btb_counter_reg[17][1] ------------------------------------------------------------------- required time 27.122 arrival time -25.486 ------------------------------------------------------------------- slack 1.636 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: cpu_clk Waveform(ns): { 0.000 15.000 } Period(ns): 30.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y47 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y47 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y46 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y46 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y48 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y48 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y49 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y49 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y50 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y50 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y51 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y51 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y48 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y48 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y49 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y49 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y52 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y52 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y51 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y51 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y52 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y52 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y51 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y51 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X7Y50 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X7Y50 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X7Y51 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X7Y51 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X6Y48 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X6Y48 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X6Y49 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X6Y49 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 30.000 27.845 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkout1_buf/I Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.000 28.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X140Y147 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[10][9]/C Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X143Y140 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][0]/C Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X143Y140 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][10]/C Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X142Y141 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][11]/C Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X142Y141 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][12]/C Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X145Y142 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][13]/C Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X143Y143 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][14]/C Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X142Y141 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][15]/C Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.000 130.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X124Y169 u_cpu/btb/btb_target_reg_0_31_22_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X124Y169 u_cpu/btb/btb_target_reg_0_31_22_23/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- From Clock: mlkem_clk To Clock: mlkem_clk Setup : 0 Failing Endpoints, Worst Slack 0.070ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.250ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.070ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732] SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.982 11.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/C clock pessimism -0.498 10.655 clock uncertainty -0.093 10.562 SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732] ------------------------------------------------------------------- required time 10.626 arrival time -10.555 ------------------------------------------------------------------- slack 0.070 Slack (MET) : 0.088ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -10.080 ------------------------------------------------------------------- slack 0.088 Slack (MET) : 0.091ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -10.077 ------------------------------------------------------------------- slack 0.091 Slack (MET) : 0.128ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948] SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/C clock pessimism -0.498 10.730 clock uncertainty -0.093 10.637 SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948] ------------------------------------------------------------------- required time 10.701 arrival time -10.573 ------------------------------------------------------------------- slack 0.128 Slack (MET) : 0.129ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -10.038 ------------------------------------------------------------------- slack 0.129 Slack (MET) : 0.135ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731] SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.982 11.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/C clock pessimism -0.498 10.655 clock uncertainty -0.093 10.562 SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731] ------------------------------------------------------------------- required time 10.626 arrival time -10.491 ------------------------------------------------------------------- slack 0.135 Slack (MET) : 0.151ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) Clock Path Skew: 0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) Source Clock Delay (SCD): -2.481ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK clock pessimism -0.426 10.586 clock uncertainty -0.093 10.493 RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- required time 10.252 arrival time -10.101 ------------------------------------------------------------------- slack 0.151 Slack (MET) : 0.155ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -10.013 ------------------------------------------------------------------- slack 0.155 Slack (MET) : 0.157ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -10.011 ------------------------------------------------------------------- slack 0.157 Slack (MET) : 0.159ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943] SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/C clock pessimism -0.498 10.730 clock uncertainty -0.093 10.637 SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943] ------------------------------------------------------------------- required time 10.750 arrival time -10.591 ------------------------------------------------------------------- slack 0.159 Slack (MET) : 0.175ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: 0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0 SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975] SLICE_X155Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.987 11.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X155Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/C clock pessimism -0.498 10.660 clock uncertainty -0.093 10.567 SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975] ------------------------------------------------------------------- required time 10.631 arrival time -10.455 ------------------------------------------------------------------- slack 0.175 Slack (MET) : 0.181ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: 0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0 SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888] SLICE_X162Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.061 11.232 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X162Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/C clock pessimism -0.498 10.734 clock uncertainty -0.093 10.641 SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888] ------------------------------------------------------------------- required time 10.754 arrival time -10.573 ------------------------------------------------------------------- slack 0.181 Slack (MET) : 0.181ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) Clock Path Skew: 0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) Source Clock Delay (SCD): -2.481ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK clock pessimism -0.426 10.586 clock uncertainty -0.093 10.493 RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- required time 10.252 arrival time -10.071 ------------------------------------------------------------------- slack 0.181 Slack (MET) : 0.185ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.209ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812] SLICE_X160Y33 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.056 11.227 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X160Y33 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/C clock pessimism -0.498 10.729 clock uncertainty -0.093 10.636 SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812] ------------------------------------------------------------------- required time 10.700 arrival time -10.515 ------------------------------------------------------------------- slack 0.185 Slack (MET) : 0.188ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.992ns (logic 0.732ns (5.634%) route 12.260ns (94.366%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.260 10.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.513 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/O net (fo=1, routed) 0.000 10.513 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[946] SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/C clock pessimism -0.498 10.730 clock uncertainty -0.093 10.637 SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946] ------------------------------------------------------------------- required time 10.701 arrival time -10.513 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.208ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.969ns (logic 0.732ns (5.644%) route 12.237ns (94.356%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.207ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.775ns = ( 11.225 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.237 10.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X159Y32 MUXF7 (Prop_muxf7_S_O) 0.276 10.490 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[921]_i_1/O net (fo=1, routed) 0.000 10.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[921] SLICE_X159Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.054 11.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X159Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921]/C clock pessimism -0.498 10.727 clock uncertainty -0.093 10.634 SLICE_X159Y32 FDCE (Setup_fdce_C_D) 0.064 10.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921] ------------------------------------------------------------------- required time 10.698 arrival time -10.490 ------------------------------------------------------------------- slack 0.208 Slack (MET) : 0.216ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[6] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.516ns (logic 4.831ns (38.597%) route 7.685ns (61.403%)) Logic Levels: 16 (CARRY4=5 LUT2=2 LUT5=2 LUT6=3 MUXF7=2 MUXF8=2) Clock Path Skew: 0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) Source Clock Delay (SCD): -2.481ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O net (fo=29, routed) 0.651 6.519 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 SLICE_X139Y85 LUT2 (Prop_lut2_I0_O) 0.150 6.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_182/O net (fo=1, routed) 0.617 7.286 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub1[0] SLICE_X139Y86 CARRY4 (Prop_carry4_CYINIT_CO[3]) 0.788 8.074 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100/CO[3] net (fo=1, routed) 0.000 8.074 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100_n_0 SLICE_X139Y87 CARRY4 (Prop_carry4_CI_O[1]) 0.334 8.408 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_87/O[1] net (fo=1, routed) 1.013 9.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[5] SLICE_X140Y88 LUT6 (Prop_lut6_I0_O) 0.303 9.723 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_27/O net (fo=1, routed) 0.313 10.036 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[6] RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[6] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK clock pessimism -0.426 10.586 clock uncertainty -0.093 10.493 RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[6]) -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- required time 10.252 arrival time -10.036 ------------------------------------------------------------------- slack 0.216 Slack (MET) : 0.221ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 13.008ns (logic 0.748ns (5.750%) route 12.260ns (94.250%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.260 10.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.292 10.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[936]_i_1/O net (fo=1, routed) 0.000 10.529 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[936] SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936]/C clock pessimism -0.498 10.730 clock uncertainty -0.093 10.637 SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936] ------------------------------------------------------------------- required time 10.750 arrival time -10.529 ------------------------------------------------------------------- slack 0.221 Slack (MET) : 0.223ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.960ns (logic 0.752ns (5.803%) route 12.208ns (94.197%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.212ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.770ns = ( 11.230 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.208 10.184 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X160Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[817]_i_1/O net (fo=1, routed) 0.000 10.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[817] SLICE_X160Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.059 11.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X160Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817]/C clock pessimism -0.498 10.732 clock uncertainty -0.093 10.639 SLICE_X160Y37 FDCE (Setup_fdce_C_D) 0.064 10.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817] ------------------------------------------------------------------- required time 10.703 arrival time -10.480 ------------------------------------------------------------------- slack 0.223 Slack (MET) : 0.230ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.947ns (logic 0.732ns (5.654%) route 12.215ns (94.346%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.207ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.775ns = ( 11.225 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.215 10.192 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X156Y32 MUXF7 (Prop_muxf7_S_O) 0.276 10.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[874]_i_1/O net (fo=1, routed) 0.000 10.468 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[874] SLICE_X156Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.054 11.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X156Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874]/C clock pessimism -0.498 10.727 clock uncertainty -0.093 10.634 SLICE_X156Y32 FDCE (Setup_fdce_C_D) 0.064 10.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874] ------------------------------------------------------------------- required time 10.698 arrival time -10.468 ------------------------------------------------------------------- slack 0.230 Slack (MET) : 0.236ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.497ns (logic 4.945ns (39.570%) route 7.552ns (60.430%)) Logic Levels: 17 (CARRY4=6 LUT2=2 LUT5=2 LUT6=3 MUXF7=2 MUXF8=2) Clock Path Skew: 0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) Source Clock Delay (SCD): -2.481ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O net (fo=29, routed) 0.651 6.519 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 SLICE_X139Y85 LUT2 (Prop_lut2_I0_O) 0.150 6.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_182/O net (fo=1, routed) 0.617 7.286 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub1[0] SLICE_X139Y86 CARRY4 (Prop_carry4_CYINIT_CO[3]) 0.788 8.074 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100/CO[3] net (fo=1, routed) 0.000 8.074 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100_n_0 SLICE_X139Y87 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 8.188 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_87/CO[3] net (fo=1, routed) 0.000 8.188 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_87_n_0 SLICE_X139Y88 CARRY4 (Prop_carry4_CI_O[1]) 0.334 8.522 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_75/O[1] net (fo=1, routed) 0.896 9.417 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[9] SLICE_X141Y88 LUT6 (Prop_lut6_I0_O) 0.303 9.720 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_23/O net (fo=1, routed) 0.296 10.016 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[10] RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK clock pessimism -0.426 10.586 clock uncertainty -0.093 10.493 RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[10]) -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- required time 10.252 arrival time -10.016 ------------------------------------------------------------------- slack 0.236 Slack (MET) : 0.240ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[4] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.447ns (logic 3.218ns (25.853%) route 9.229ns (74.147%)) Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[0]) 0.235 6.988 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[0] net (fo=2, routed) 0.975 7.962 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[4] SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.299 8.261 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_141__0/O net (fo=1, routed) 0.445 8.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_6 SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.831 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_90__0/O net (fo=1, routed) 0.437 9.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_90__0_n_0 SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.391 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_31__0/O net (fo=1, routed) 0.536 9.928 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[4] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[4] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[4]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -9.928 ------------------------------------------------------------------- slack 0.240 Slack (MET) : 0.241ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1002]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.985ns (logic 0.748ns (5.760%) route 12.237ns (94.240%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.207ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.775ns = ( 11.225 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.237 10.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X158Y32 MUXF7 (Prop_muxf7_S_O) 0.292 10.506 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1002]_i_1/O net (fo=1, routed) 0.000 10.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[1002] SLICE_X158Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1002]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.054 11.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X158Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1002]/C clock pessimism -0.498 10.727 clock uncertainty -0.093 10.634 SLICE_X158Y32 FDCE (Setup_fdce_C_D) 0.113 10.747 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1002] ------------------------------------------------------------------- required time 10.747 arrival time -10.506 ------------------------------------------------------------------- slack 0.241 Slack (MET) : 0.246ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[729]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.908ns (logic 0.748ns (5.795%) route 12.160ns (94.205%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.160 10.137 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X148Y37 MUXF7 (Prop_muxf7_S_O) 0.292 10.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[729]_i_1/O net (fo=1, routed) 0.000 10.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[729] SLICE_X148Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[729]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.982 11.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X148Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[729]/C clock pessimism -0.498 10.655 clock uncertainty -0.093 10.562 SLICE_X148Y37 FDCE (Setup_fdce_C_D) 0.113 10.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[729] ------------------------------------------------------------------- required time 10.675 arrival time -10.429 ------------------------------------------------------------------- slack 0.246 Slack (MET) : 0.247ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[743]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.908ns (logic 0.748ns (5.795%) route 12.160ns (94.205%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.846ns = ( 11.154 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.160 10.137 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X148Y38 MUXF7 (Prop_muxf7_S_O) 0.292 10.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[743]_i_2/O net (fo=1, routed) 0.000 10.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[743] SLICE_X148Y38 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[743]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.983 11.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X148Y38 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[743]/C clock pessimism -0.498 10.656 clock uncertainty -0.093 10.563 SLICE_X148Y38 FDCE (Setup_fdce_C_D) 0.113 10.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[743] ------------------------------------------------------------------- required time 10.676 arrival time -10.429 ------------------------------------------------------------------- slack 0.247 Slack (MET) : 0.252ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[8] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.435ns (logic 3.332ns (26.795%) route 9.103ns (73.205%)) Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[0]) 0.235 7.111 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[0] net (fo=2, routed) 0.804 7.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[8] SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.299 8.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_130/O net (fo=1, routed) 0.473 8.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_10 SLICE_X135Y74 LUT6 (Prop_lut6_I5_O) 0.124 8.811 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_84__0/O net (fo=1, routed) 0.298 9.109 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_84__0_n_0 SLICE_X137Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_27__0/O net (fo=1, routed) 0.682 9.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[8] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[8]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -9.915 ------------------------------------------------------------------- slack 0.252 Slack (MET) : 0.261ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[819]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.970ns (logic 0.770ns (5.937%) route 12.200ns (94.063%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.211ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.771ns = ( 11.229 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.200 10.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X162Y36 MUXF7 (Prop_muxf7_S_O) 0.314 10.490 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[819]_i_1/O net (fo=1, routed) 0.000 10.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[819] SLICE_X162Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[819]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.058 11.229 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X162Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[819]/C clock pessimism -0.498 10.731 clock uncertainty -0.093 10.638 SLICE_X162Y36 FDCE (Setup_fdce_C_D) 0.113 10.751 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[819] ------------------------------------------------------------------- required time 10.751 arrival time -10.490 ------------------------------------------------------------------- slack 0.261 Slack (MET) : 0.271ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.462ns (logic 4.562ns (36.608%) route 7.900ns (63.392%)) Logic Levels: 15 (CARRY4=4 LUT2=2 LUT5=2 LUT6=3 MUXF7=2 MUXF8=2) Clock Path Skew: 0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) Source Clock Delay (SCD): -2.481ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O net (fo=29, routed) 0.651 6.519 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 SLICE_X139Y85 LUT2 (Prop_lut2_I0_O) 0.150 6.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_182/O net (fo=1, routed) 0.617 7.286 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub1[0] SLICE_X139Y86 CARRY4 (Prop_carry4_CYINIT_O[3]) 0.850 8.136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100/O[3] net (fo=1, routed) 1.041 9.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[3] SLICE_X140Y88 LUT6 (Prop_lut6_I0_O) 0.306 9.482 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29/O net (fo=1, routed) 0.499 9.981 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[4] RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK clock pessimism -0.426 10.586 clock uncertainty -0.093 10.493 RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[4]) -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- required time 10.252 arrival time -9.981 ------------------------------------------------------------------- slack 0.271 Slack (MET) : 0.271ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[951]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.961ns (logic 0.789ns (6.087%) route 12.172ns (93.913%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: 0.213ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.769ns = ( 11.231 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 12.172 10.148 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X158Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.272 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[951]_i_3/O net (fo=1, routed) 0.000 10.272 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[951]_i_3_n_0 SLICE_X158Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[951]_i_2/O net (fo=1, routed) 0.000 10.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[951] SLICE_X158Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[951]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.060 11.231 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X158Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[951]/C clock pessimism -0.498 10.733 clock uncertainty -0.093 10.640 SLICE_X158Y40 FDCE (Setup_fdce_C_D) 0.113 10.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[951] ------------------------------------------------------------------- required time 10.753 arrival time -10.481 ------------------------------------------------------------------- slack 0.271 Slack (MET) : 0.282ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[825]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.903ns (logic 0.792ns (6.138%) route 12.111ns (93.862%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: 0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.767ns = ( 11.233 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 12.111 10.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X163Y41 LUT4 (Prop_lut4_I2_O) 0.124 10.211 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[825]_i_2/O net (fo=1, routed) 0.000 10.211 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[825]_i_2_n_0 SLICE_X163Y41 MUXF7 (Prop_muxf7_I0_O) 0.212 10.423 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[825]_i_1/O net (fo=1, routed) 0.000 10.423 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[825] SLICE_X163Y41 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[825]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.062 11.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X163Y41 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[825]/C clock pessimism -0.498 10.735 clock uncertainty -0.093 10.642 SLICE_X163Y41 FDCE (Setup_fdce_C_D) 0.064 10.706 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[825] ------------------------------------------------------------------- required time 10.706 arrival time -10.423 ------------------------------------------------------------------- slack 0.282 Slack (MET) : 0.284ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.448ns (logic 3.752ns (30.141%) route 8.696ns (69.859%)) Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) Clock Path Skew: 0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) Source Clock Delay (SCD): -2.481ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O net (fo=12, routed) 0.714 9.320 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 SLICE_X141Y86 LUT6 (Prop_lut6_I2_O) 0.124 9.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__0/O net (fo=1, routed) 0.523 9.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[0] RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK clock pessimism -0.426 10.586 clock uncertainty -0.093 10.493 RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[0]) -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- required time 10.252 arrival time -9.968 ------------------------------------------------------------------- slack 0.284 Slack (MET) : 0.288ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[848]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.897ns (logic 0.792ns (6.141%) route 12.105ns (93.859%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: 0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.767ns = ( 11.233 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 12.105 10.082 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X157Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[848]_i_2/O net (fo=1, routed) 0.000 10.206 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[848]_i_2_n_0 SLICE_X157Y43 MUXF7 (Prop_muxf7_I0_O) 0.212 10.418 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[848]_i_1/O net (fo=1, routed) 0.000 10.418 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[848] SLICE_X157Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[848]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.062 11.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X157Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[848]/C clock pessimism -0.498 10.735 clock uncertainty -0.093 10.642 SLICE_X157Y43 FDCE (Setup_fdce_C_D) 0.064 10.706 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[848] ------------------------------------------------------------------- required time 10.706 arrival time -10.418 ------------------------------------------------------------------- slack 0.288 Slack (MET) : 0.299ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[7] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.388ns (logic 3.319ns (26.792%) route 9.069ns (73.208%)) Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[3]) 0.329 7.082 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[3] net (fo=2, routed) 0.954 8.036 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[7] SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.306 8.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_134/O net (fo=1, routed) 0.451 8.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_9 SLICE_X137Y74 LUT6 (Prop_lut6_I5_O) 0.124 8.917 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_86__1/O net (fo=1, routed) 0.294 9.211 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_86__1_n_0 SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.335 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_28__0/O net (fo=1, routed) 0.533 9.869 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[7] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[7] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[7]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -9.869 ------------------------------------------------------------------- slack 0.299 Slack (MET) : 0.305ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.427ns (logic 3.951ns (31.793%) route 8.476ns (68.207%)) Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) Clock Path Skew: 0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) Source Clock Delay (SCD): -2.481ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O net (fo=12, routed) 0.937 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 SLICE_X140Y87 LUT6 (Prop_lut6_I3_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22/O net (fo=1, routed) 0.313 9.947 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[11] RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK clock pessimism -0.426 10.586 clock uncertainty -0.093 10.493 RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[11]) -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- required time 10.252 arrival time -9.947 ------------------------------------------------------------------- slack 0.305 Slack (MET) : 0.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[1] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.377ns (logic 2.879ns (23.261%) route 9.498ns (76.739%)) Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[1]) 0.424 6.645 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[1] net (fo=2, routed) 0.964 7.608 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[1] SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 7.911 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_152/O net (fo=1, routed) 0.454 8.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_3 SLICE_X136Y74 LUT6 (Prop_lut6_I5_O) 0.124 8.489 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_95__0/O net (fo=1, routed) 0.481 8.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_95__0_n_0 SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_34/O net (fo=1, routed) 0.763 9.858 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[1] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[1] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[1]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -9.858 ------------------------------------------------------------------- slack 0.310 Slack (MET) : 0.325ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[944]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.855ns (logic 0.732ns (5.694%) route 12.123ns (94.306%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.123 10.100 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X160Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.376 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[944]_i_1/O net (fo=1, routed) 0.000 10.376 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[944] SLICE_X160Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[944]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X160Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[944]/C clock pessimism -0.498 10.730 clock uncertainty -0.093 10.637 SLICE_X160Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[944] ------------------------------------------------------------------- required time 10.701 arrival time -10.376 ------------------------------------------------------------------- slack 0.325 Slack (MET) : 0.328ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[2] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.404ns (logic 4.515ns (36.399%) route 7.889ns (63.601%)) Logic Levels: 15 (CARRY4=4 LUT2=2 LUT5=2 LUT6=3 MUXF7=2 MUXF8=2) Clock Path Skew: 0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) Source Clock Delay (SCD): -2.481ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O net (fo=29, routed) 0.651 6.519 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 SLICE_X139Y85 LUT2 (Prop_lut2_I0_O) 0.150 6.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_182/O net (fo=1, routed) 0.617 7.286 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub1[0] SLICE_X139Y86 CARRY4 (Prop_carry4_CYINIT_O[1]) 0.806 8.092 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100/O[1] net (fo=1, routed) 1.043 9.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[1] SLICE_X141Y87 LUT6 (Prop_lut6_I0_O) 0.303 9.438 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_31/O net (fo=1, routed) 0.486 9.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[2] RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[2] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK clock pessimism -0.426 10.586 clock uncertainty -0.093 10.493 RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[2]) -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- required time 10.252 arrival time -9.924 ------------------------------------------------------------------- slack 0.328 Slack (MET) : 0.330ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.402ns (logic 3.951ns (31.858%) route 8.451ns (68.142%)) Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) Clock Path Skew: 0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) Source Clock Delay (SCD): -2.481ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O net (fo=12, routed) 0.914 9.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 SLICE_X140Y87 LUT6 (Prop_lut6_I3_O) 0.124 9.611 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25/O net (fo=1, routed) 0.310 9.921 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[8] RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK clock pessimism -0.426 10.586 clock uncertainty -0.093 10.493 RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[8]) -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- required time 10.252 arrival time -9.921 ------------------------------------------------------------------- slack 0.330 Slack (MET) : 0.331ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[947]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.849ns (logic 0.732ns (5.697%) route 12.117ns (94.303%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.117 10.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X161Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.370 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[947]_i_1/O net (fo=1, routed) 0.000 10.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[947] SLICE_X161Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[947]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X161Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[947]/C clock pessimism -0.498 10.730 clock uncertainty -0.093 10.637 SLICE_X161Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[947] ------------------------------------------------------------------- required time 10.701 arrival time -10.370 ------------------------------------------------------------------- slack 0.331 Slack (MET) : 0.331ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[828]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.903ns (logic 0.789ns (6.115%) route 12.114ns (93.885%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: 0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.767ns = ( 11.233 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 12.114 10.090 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X162Y41 LUT4 (Prop_lut4_I2_O) 0.124 10.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[828]_i_2/O net (fo=1, routed) 0.000 10.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[828]_i_2_n_0 SLICE_X162Y41 MUXF7 (Prop_muxf7_I0_O) 0.209 10.423 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[828]_i_1/O net (fo=1, routed) 0.000 10.423 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[828] SLICE_X162Y41 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[828]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.062 11.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X162Y41 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[828]/C clock pessimism -0.498 10.735 clock uncertainty -0.093 10.642 SLICE_X162Y41 FDCE (Setup_fdce_C_D) 0.113 10.755 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[828] ------------------------------------------------------------------- required time 10.755 arrival time -10.423 ------------------------------------------------------------------- slack 0.331 Slack (MET) : 0.333ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.354ns (logic 3.036ns (24.575%) route 9.318ns (75.425%)) Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 SLICE_X106Y75 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 6.990 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CO[3] net (fo=2, routed) 1.126 8.115 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[11] SLICE_X130Y75 LUT6 (Prop_lut6_I1_O) 0.124 8.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_121__0/O net (fo=1, routed) 0.612 8.852 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_13 SLICE_X136Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.976 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_77__0/O net (fo=1, routed) 0.293 9.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_77__0_n_0 SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.393 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_24__0/O net (fo=1, routed) 0.442 9.835 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[11] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[11]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -9.835 ------------------------------------------------------------------- slack 0.333 Slack (MET) : 0.333ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[805]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.737ns (logic 0.580ns (4.554%) route 12.157ns (95.446%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.157 10.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X153Y36 LUT5 (Prop_lut5_I2_O) 0.124 10.258 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[805]_i_1/O net (fo=1, routed) 0.000 10.258 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[805] SLICE_X153Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[805]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.982 11.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X153Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[805]/C clock pessimism -0.498 10.655 clock uncertainty -0.093 10.562 SLICE_X153Y36 FDCE (Setup_fdce_C_D) 0.029 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[805] ------------------------------------------------------------------- required time 10.591 arrival time -10.258 ------------------------------------------------------------------- slack 0.333 Slack (MET) : 0.333ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[806]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.739ns (logic 0.580ns (4.553%) route 12.159ns (95.447%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.159 10.136 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X153Y36 LUT5 (Prop_lut5_I2_O) 0.124 10.260 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[806]_i_1/O net (fo=1, routed) 0.000 10.260 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[806] SLICE_X153Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[806]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.982 11.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X153Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[806]/C clock pessimism -0.498 10.655 clock uncertainty -0.093 10.562 SLICE_X153Y36 FDCE (Setup_fdce_C_D) 0.031 10.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[806] ------------------------------------------------------------------- required time 10.593 arrival time -10.260 ------------------------------------------------------------------- slack 0.333 Slack (MET) : 0.339ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1014]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.809ns (logic 0.580ns (4.528%) route 12.229ns (95.472%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.229 10.205 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X156Y36 LUT5 (Prop_lut5_I2_O) 0.124 10.329 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1014]_i_1/O net (fo=1, routed) 0.000 10.329 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[1014] SLICE_X156Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1014]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X156Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1014]/C clock pessimism -0.498 10.730 clock uncertainty -0.093 10.637 SLICE_X156Y36 FDCE (Setup_fdce_C_D) 0.032 10.669 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1014] ------------------------------------------------------------------- required time 10.669 arrival time -10.329 ------------------------------------------------------------------- slack 0.339 Slack (MET) : 0.340ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1013]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.808ns (logic 0.580ns (4.529%) route 12.228ns (95.471%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.228 10.204 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X156Y36 LUT5 (Prop_lut5_I2_O) 0.124 10.328 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1013]_i_1/O net (fo=1, routed) 0.000 10.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[1013] SLICE_X156Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1013]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X156Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1013]/C clock pessimism -0.498 10.730 clock uncertainty -0.093 10.637 SLICE_X156Y36 FDCE (Setup_fdce_C_D) 0.031 10.668 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1013] ------------------------------------------------------------------- required time 10.668 arrival time -10.328 ------------------------------------------------------------------- slack 0.340 Slack (MET) : 0.349ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[945]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.831ns (logic 0.752ns (5.861%) route 12.079ns (94.139%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.079 10.056 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X160Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.352 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[945]_i_1/O net (fo=1, routed) 0.000 10.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[945] SLICE_X160Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[945]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X160Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[945]/C clock pessimism -0.498 10.730 clock uncertainty -0.093 10.637 SLICE_X160Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[945] ------------------------------------------------------------------- required time 10.701 arrival time -10.352 ------------------------------------------------------------------- slack 0.349 Slack (MET) : 0.362ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[809]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.817ns (logic 0.732ns (5.711%) route 12.085ns (94.289%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.209ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.085 10.062 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X159Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.338 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[809]_i_1/O net (fo=1, routed) 0.000 10.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[809] SLICE_X159Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[809]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.056 11.227 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X159Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[809]/C clock pessimism -0.498 10.729 clock uncertainty -0.093 10.636 SLICE_X159Y34 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[809] ------------------------------------------------------------------- required time 10.700 arrival time -10.338 ------------------------------------------------------------------- slack 0.362 Slack (MET) : 0.371ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[924]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.860ns (logic 0.748ns (5.817%) route 12.112ns (94.183%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.211ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.771ns = ( 11.229 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.112 10.088 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X162Y35 MUXF7 (Prop_muxf7_S_O) 0.292 10.380 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[924]_i_1/O net (fo=1, routed) 0.000 10.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[924] SLICE_X162Y35 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[924]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.058 11.229 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X162Y35 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[924]/C clock pessimism -0.498 10.731 clock uncertainty -0.093 10.638 SLICE_X162Y35 FDCE (Setup_fdce_C_D) 0.113 10.751 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[924] ------------------------------------------------------------------- required time 10.751 arrival time -10.380 ------------------------------------------------------------------- slack 0.371 Slack (MET) : 0.375ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[985]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.804ns (logic 0.732ns (5.717%) route 12.072ns (94.283%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.209ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.072 10.049 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X156Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.325 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[985]_i_1/O net (fo=1, routed) 0.000 10.325 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[985] SLICE_X156Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[985]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.056 11.227 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X156Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[985]/C clock pessimism -0.498 10.729 clock uncertainty -0.093 10.636 SLICE_X156Y34 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[985] ------------------------------------------------------------------- required time 10.700 arrival time -10.325 ------------------------------------------------------------------- slack 0.375 Slack (MET) : 0.379ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[988]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.801ns (logic 0.752ns (5.875%) route 12.049ns (94.125%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.209ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.049 10.025 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X157Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.321 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[988]_i_1/O net (fo=1, routed) 0.000 10.321 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[988] SLICE_X157Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[988]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.056 11.227 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X157Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[988]/C clock pessimism -0.498 10.729 clock uncertainty -0.093 10.636 SLICE_X157Y34 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[988] ------------------------------------------------------------------- required time 10.700 arrival time -10.321 ------------------------------------------------------------------- slack 0.379 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: mlkem_clk Waveform(ns): { 0.000 6.500 } Period(ns): 13.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y39 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y38 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y40 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y41 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB36_X7Y14 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y37 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X8Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X6Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y44 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y43 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y42 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y45 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y39 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y38 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y40 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y41 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB36_X7Y14 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y37 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X8Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X6Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y44 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y43 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y42 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y45 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 13.000 10.845 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout3_buf/I Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 13.000 11.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X160Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[0]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[1]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[2]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[3]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[4]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X160Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[5]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[6]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[7]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X102Y84 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[94]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X105Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[95]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X102Y84 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[96]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X107Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[97]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X109Y78 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[98]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X111Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[99]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X127Y86 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[9]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X155Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/snt_ack_reg/C Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 13.000 147.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- From Clock: sys_clk To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 0.125ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.125ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) 0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 13.197 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -13.197 ------------------------------------------------------------------- slack 0.125 Slack (MET) : 0.253ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T AC16 OBUFT (TriStatE_obuft_T_O) 3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O net (fo=1, unset) 0.000 13.069 ext_ram_data[21] AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -13.069 ------------------------------------------------------------------- slack 0.253 Slack (MET) : 0.342ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T Y15 OBUFT (TriStatE_obuft_T_O) 3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O net (fo=1, unset) 0.000 12.980 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.980 ------------------------------------------------------------------- slack 0.342 Slack (MET) : 0.395ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1 SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) 0.152 2.452 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20] SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0 SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20] SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 r ext_ram_data_IOBUF[20]_inst/OBUFT/O net (fo=1, unset) 0.000 12.927 ext_ram_data[20] AD18 r ext_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.927 ------------------------------------------------------------------- slack 0.395 Slack (MET) : 0.403ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T AB16 OBUFT (TriStatE_obuft_T_O) 3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.919 ext_ram_data[16] AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.919 ------------------------------------------------------------------- slack 0.403 Slack (MET) : 0.416ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[6] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%)) Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1 SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O) 0.152 2.820 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38] SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 r u_matmul_axi_slave/ram_reg_i_46/O net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6] SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 r ext_ram_data_IOBUF[6]_inst/OBUFT/O net (fo=1, unset) 0.000 12.906 ext_ram_data[6] AE20 r ext_ram_data[6] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.906 ------------------------------------------------------------------- slack 0.416 Slack (MET) : 0.422ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.900 ext_ram_data[31] AC23 r ext_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.900 ------------------------------------------------------------------- slack 0.422 Slack (MET) : 0.475ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T L25 OBUFT (TriStatE_obuft_T_O) 3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O net (fo=1, unset) 0.000 12.847 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.847 ------------------------------------------------------------------- slack 0.475 Slack (MET) : 0.483ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.839 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.839 ------------------------------------------------------------------- slack 0.483 Slack (MET) : 0.489ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[19] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T AC18 OBUFT (TriStatE_obuft_T_O) 3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O net (fo=1, unset) 0.000 12.833 ext_ram_data[19] AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.833 ------------------------------------------------------------------- slack 0.489 Slack (MET) : 0.508ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[23] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.143ns (logic 6.882ns (45.449%) route 8.261ns (54.551%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.595 9.272 ext_ram_data_IOBUF[23]_inst/T AA15 OBUFT (TriStatE_obuft_T_O) 3.542 12.815 r ext_ram_data_IOBUF[23]_inst/OBUFT/O net (fo=1, unset) 0.000 12.815 ext_ram_data[23] AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.815 ------------------------------------------------------------------- slack 0.508 Slack (MET) : 0.518ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.133ns (logic 6.891ns (45.538%) route 8.241ns (54.462%)) Logic Levels: 13 (CARRY4=6 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.371 7.266 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X0Y129 LUT6 (Prop_lut6_I5_O) 0.124 7.390 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O net (fo=1, routed) 1.863 9.253 base_ram_be_n_OBUF[3] K25 OBUF (Prop_obuf_I_O) 3.551 12.804 r base_ram_be_n_OBUF[3]_inst/O net (fo=0) 0.000 12.804 base_ram_be_n[3] K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.804 ------------------------------------------------------------------- slack 0.518 Slack (MET) : 0.535ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.116ns (logic 6.893ns (45.603%) route 8.223ns (54.397%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.557 9.234 ext_ram_data_IOBUF[25]_inst/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.788 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.788 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.788 ------------------------------------------------------------------- slack 0.535 Slack (MET) : 0.557ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.173ns (logic 5.026ns (33.126%) route 10.147ns (66.874%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 0.971 1.949 u_snix_axil_cdma_mux_8ch/ep_rd_elem[1] SLICE_X21Y79 LUT6 (Prop_lut6_I3_O) 0.124 2.073 r u_snix_axil_cdma_mux_8ch/ram_reg_i_77/O net (fo=32, routed) 1.329 3.402 u_matmul_axi_slave/ram_reg_i_51_1 SLICE_X24Y84 LUT4 (Prop_lut4_I3_O) 0.124 3.526 r u_matmul_axi_slave/ram_reg_i_67/O net (fo=1, routed) 0.500 4.026 u_matmul_axi_slave/ram_reg_i_67_n_0 SLICE_X25Y84 LUT5 (Prop_lut5_I4_O) 0.124 4.150 r u_matmul_axi_slave/ram_reg_i_49/O net (fo=1, routed) 0.645 4.795 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[3] SLICE_X29Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.919 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_33/O net (fo=3, routed) 0.413 5.332 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[3] SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.456 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[3]_inst_i_1/O net (fo=2, routed) 3.731 9.187 ext_ram_data_IOBUF[3]_inst/I AE22 OBUFT (Prop_obuft_I_O) 3.578 12.765 r ext_ram_data_IOBUF[3]_inst/OBUFT/O net (fo=1, unset) 0.000 12.765 ext_ram_data[3] AE22 r ext_ram_data[3] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.765 ------------------------------------------------------------------- slack 0.557 Slack (MET) : 0.561ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.169ns (logic 5.223ns (34.430%) route 9.946ns (65.570%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT6=4 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=136, routed) 1.303 2.393 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA0 SLICE_X22Y84 RAMD32 (Prop_ramd32_RADR0_O) 0.150 2.543 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.961 3.504 u_matmul_axi_slave/ep_rd_c0[0] SLICE_X24Y82 LUT4 (Prop_lut4_I2_O) 0.328 3.832 r u_matmul_axi_slave/ram_reg_i_73/O net (fo=1, routed) 0.667 4.499 u_matmul_axi_slave/ram_reg_i_73_n_0 SLICE_X24Y82 LUT6 (Prop_lut6_I0_O) 0.124 4.623 r u_matmul_axi_slave/ram_reg_i_52/O net (fo=1, routed) 0.414 5.036 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[0] SLICE_X26Y82 LUT6 (Prop_lut6_I5_O) 0.124 5.160 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_36/O net (fo=3, routed) 0.309 5.470 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X27Y83 LUT3 (Prop_lut3_I0_O) 0.124 5.594 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.623 9.217 base_ram_data_IOBUF[0]_inst/I L24 OBUFT (Prop_obuft_I_O) 3.545 12.761 r base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.761 base_ram_data[0] L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.761 ------------------------------------------------------------------- slack 0.561 Slack (MET) : 0.585ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.145ns (logic 5.222ns (34.482%) route 9.923ns (65.518%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=136, routed) 1.356 2.446 u_matmul_axi_slave/b0_c_reg_r2_0_15_30_35/ADDRA0 SLICE_X22Y85 RAMD32 (Prop_ramd32_RADR0_O) 0.150 2.596 r u_matmul_axi_slave/b0_c_reg_r2_0_15_30_35/RAMA/O net (fo=1, routed) 0.805 3.401 u_matmul_axi_slave/ep_rd_c0[30] SLICE_X24Y83 LUT4 (Prop_lut4_I2_O) 0.328 3.729 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_13__0/O net (fo=1, routed) 0.428 4.157 u_matmul_axi_slave/ram_reg_0_7_30_35_i_13__0_n_0 SLICE_X26Y82 LUT5 (Prop_lut5_I4_O) 0.124 4.281 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=1, routed) 0.462 4.742 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[30] SLICE_X28Y82 LUT6 (Prop_lut6_I5_O) 0.124 4.866 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_8__1/O net (fo=3, routed) 0.482 5.348 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[30] SLICE_X28Y82 LUT3 (Prop_lut3_I0_O) 0.124 5.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.721 9.193 base_ram_data_IOBUF[30]_inst/I M24 OBUFT (Prop_obuft_I_O) 3.544 12.737 r base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.737 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.737 ------------------------------------------------------------------- slack 0.585 Slack (MET) : 0.587ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.143ns (logic 5.221ns (34.475%) route 9.923ns (65.525%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=136, routed) 1.328 2.418 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/ADDRA0 SLICE_X22Y82 RAMD32 (Prop_ramd32_RADR0_O) 0.150 2.568 r u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA/O net (fo=1, routed) 0.801 3.369 u_matmul_axi_slave/ep_rd_c0[24] SLICE_X19Y77 LUT4 (Prop_lut4_I2_O) 0.328 3.697 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_20__0/O net (fo=1, routed) 0.151 3.848 u_matmul_axi_slave/ram_reg_0_7_24_29_i_20__0_n_0 SLICE_X19Y77 LUT5 (Prop_lut5_I4_O) 0.124 3.972 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_14__0/O net (fo=1, routed) 0.433 4.405 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[24] SLICE_X19Y77 LUT6 (Prop_lut6_I5_O) 0.124 4.529 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_8__1/O net (fo=3, routed) 0.840 5.368 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[24] SLICE_X11Y71 LUT3 (Prop_lut3_I0_O) 0.124 5.492 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[24]_inst_i_1/O net (fo=2, routed) 3.701 9.193 ext_ram_data_IOBUF[24]_inst/I AD17 OBUFT (Prop_obuft_I_O) 3.543 12.736 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 12.736 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.736 ------------------------------------------------------------------- slack 0.587 Slack (MET) : 0.616ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.035ns (logic 6.884ns (45.785%) route 8.151ns (54.215%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.367 9.162 base_ram_data_IOBUF[21]_inst/T M20 OBUFT (TriStatE_obuft_T_O) 3.544 12.706 r base_ram_data_IOBUF[21]_inst/OBUFT/O net (fo=1, unset) 0.000 12.706 base_ram_data[21] M20 r base_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.706 ------------------------------------------------------------------- slack 0.616 Slack (MET) : 0.622ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.029ns (logic 6.910ns (45.974%) route 8.120ns (54.026%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.335 9.131 base_ram_data_IOBUF[3]_inst/T M25 OBUFT (TriStatE_obuft_T_O) 3.570 12.701 r base_ram_data_IOBUF[3]_inst/OBUFT/O net (fo=1, unset) 0.000 12.701 base_ram_data[3] M25 r base_ram_data[3] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.701 ------------------------------------------------------------------- slack 0.622 Slack (MET) : 0.628ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.102ns (logic 5.207ns (34.482%) route 9.895ns (65.518%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) 0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O net (fo=2, routed) 3.505 9.161 base_ram_data_IOBUF[18]_inst/I P23 OBUFT (Prop_obuft_I_O) 3.533 12.694 r base_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.694 base_ram_data[18] P23 r base_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.694 ------------------------------------------------------------------- slack 0.628 Slack (MET) : 0.632ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[17] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.019ns (logic 6.895ns (45.909%) route 8.124ns (54.091%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.458 9.135 ext_ram_data_IOBUF[17]_inst/T AC19 OBUFT (TriStatE_obuft_T_O) 3.555 12.691 r ext_ram_data_IOBUF[17]_inst/OBUFT/O net (fo=1, unset) 0.000 12.691 ext_ram_data[17] AC19 r ext_ram_data[17] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.691 ------------------------------------------------------------------- slack 0.632 Slack (MET) : 0.636ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.094ns (logic 5.207ns (34.496%) route 9.887ns (65.504%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=136, routed) 1.356 2.446 u_matmul_axi_slave/b0_c_reg_r2_0_15_30_35/ADDRA0 SLICE_X22Y85 RAMD32 (Prop_ramd32_RADR0_O) 0.150 2.596 r u_matmul_axi_slave/b0_c_reg_r2_0_15_30_35/RAMA/O net (fo=1, routed) 0.805 3.401 u_matmul_axi_slave/ep_rd_c0[30] SLICE_X24Y83 LUT4 (Prop_lut4_I2_O) 0.328 3.729 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_13__0/O net (fo=1, routed) 0.428 4.157 u_matmul_axi_slave/ram_reg_0_7_30_35_i_13__0_n_0 SLICE_X26Y82 LUT5 (Prop_lut5_I4_O) 0.124 4.281 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=1, routed) 0.462 4.742 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[30] SLICE_X28Y82 LUT6 (Prop_lut6_I5_O) 0.124 4.866 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_8__1/O net (fo=3, routed) 0.482 5.348 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[30] SLICE_X28Y82 LUT3 (Prop_lut3_I0_O) 0.124 5.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.685 9.158 ext_ram_data_IOBUF[30]_inst/I AA19 OBUFT (Prop_obuft_I_O) 3.529 12.687 r ext_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.687 ext_ram_data[30] AA19 r ext_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.687 ------------------------------------------------------------------- slack 0.636 Slack (MET) : 0.692ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[17] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.958ns (logic 6.886ns (46.033%) route 8.073ns (53.967%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.288 9.084 base_ram_data_IOBUF[17]_inst/T M21 OBUFT (TriStatE_obuft_T_O) 3.546 12.630 r base_ram_data_IOBUF[17]_inst/OBUFT/O net (fo=1, unset) 0.000 12.630 base_ram_data[17] M21 r base_ram_data[17] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.630 ------------------------------------------------------------------- slack 0.692 Slack (MET) : 0.732ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.997ns (logic 5.202ns (34.686%) route 9.795ns (65.314%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1 SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) 0.152 2.452 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20] SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0 SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20] SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O net (fo=2, routed) 3.539 9.088 base_ram_data_IOBUF[20]_inst/I N19 OBUFT (Prop_obuft_I_O) 3.502 12.590 r base_ram_data_IOBUF[20]_inst/OBUFT/O net (fo=1, unset) 0.000 12.590 base_ram_data[20] N19 r base_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.590 ------------------------------------------------------------------- slack 0.732 Slack (MET) : 0.760ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[27] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.890ns (logic 6.863ns (46.087%) route 8.028ns (53.913%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.244 9.039 base_ram_data_IOBUF[27]_inst/T P20 OBUFT (TriStatE_obuft_T_O) 3.523 12.562 r base_ram_data_IOBUF[27]_inst/OBUFT/O net (fo=1, unset) 0.000 12.562 base_ram_data[27] P20 r base_ram_data[27] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.562 ------------------------------------------------------------------- slack 0.760 Slack (MET) : 0.761ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[26] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.969ns (logic 5.252ns (35.086%) route 9.717ns (64.914%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=136, routed) 1.318 2.408 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/ADDRB0 SLICE_X22Y82 RAMD32 (Prop_ramd32_RADR0_O) 0.152 2.560 r u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB/O net (fo=1, routed) 0.643 3.203 u_matmul_axi_slave/ep_rd_c0[26] SLICE_X23Y81 LUT4 (Prop_lut4_I2_O) 0.348 3.551 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_22__0/O net (fo=1, routed) 0.434 3.985 u_matmul_axi_slave/ram_reg_0_7_24_29_i_22__0_n_0 SLICE_X23Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.109 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_16__0/O net (fo=1, routed) 0.676 4.785 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[26] SLICE_X26Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.909 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_10__1/O net (fo=3, routed) 0.455 5.364 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[26] SLICE_X27Y84 LUT3 (Prop_lut3_I0_O) 0.124 5.488 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[26]_inst_i_1/O net (fo=2, routed) 3.522 9.010 ext_ram_data_IOBUF[26]_inst/I AD20 OBUFT (Prop_obuft_I_O) 3.552 12.562 r ext_ram_data_IOBUF[26]_inst/OBUFT/O net (fo=1, unset) 0.000 12.562 ext_ram_data[26] AD20 r ext_ram_data[26] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.562 ------------------------------------------------------------------- slack 0.761 Slack (MET) : 0.781ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[27] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.870ns (logic 6.901ns (46.406%) route 7.969ns (53.594%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.304 8.981 ext_ram_data_IOBUF[27]_inst/T AB21 OBUFT (TriStatE_obuft_T_O) 3.561 12.541 r ext_ram_data_IOBUF[27]_inst/OBUFT/O net (fo=1, unset) 0.000 12.541 ext_ram_data[27] AB21 r ext_ram_data[27] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.541 ------------------------------------------------------------------- slack 0.781 Slack (MET) : 0.788ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[4] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.942ns (logic 5.261ns (35.206%) route 9.682ns (64.794%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.421 2.399 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRC1 SLICE_X22Y84 RAMD32 (Prop_ramd32_RADR1_O) 0.153 2.552 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC/O net (fo=1, routed) 0.575 3.127 u_matmul_axi_slave/ep_rd_c0[4] SLICE_X23Y84 LUT4 (Prop_lut4_I2_O) 0.331 3.458 r u_matmul_axi_slave/ram_reg_i_66/O net (fo=1, routed) 0.672 4.130 u_matmul_axi_slave/ram_reg_i_66_n_0 SLICE_X26Y82 LUT5 (Prop_lut5_I4_O) 0.124 4.254 r u_matmul_axi_slave/ram_reg_i_48/O net (fo=1, routed) 0.485 4.738 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[4] SLICE_X27Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.862 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_32/O net (fo=3, routed) 0.276 5.138 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[4] SLICE_X27Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.262 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[4]_inst_i_1/O net (fo=2, routed) 3.696 8.958 ext_ram_data_IOBUF[4]_inst/I AF22 OBUFT (Prop_obuft_I_O) 3.577 12.535 r ext_ram_data_IOBUF[4]_inst/OBUFT/O net (fo=1, unset) 0.000 12.535 ext_ram_data[4] AF22 r ext_ram_data[4] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.535 ------------------------------------------------------------------- slack 0.788 Slack (MET) : 0.790ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[5] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.940ns (logic 5.012ns (33.550%) route 9.928ns (66.450%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.421 2.399 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRC1 SLICE_X22Y84 RAMD32 (Prop_ramd32_RADR1_O) 0.124 2.523 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/O net (fo=1, routed) 0.664 3.188 u_matmul_axi_slave/ep_rd_c0[5] SLICE_X24Y84 LUT4 (Prop_lut4_I2_O) 0.124 3.312 r u_matmul_axi_slave/ram_reg_i_65/O net (fo=1, routed) 0.582 3.893 u_matmul_axi_slave/ram_reg_i_65_n_0 SLICE_X26Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.017 r u_matmul_axi_slave/ram_reg_i_47/O net (fo=1, routed) 0.489 4.506 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[5] SLICE_X26Y81 LUT6 (Prop_lut6_I5_O) 0.124 4.630 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_31/O net (fo=4, routed) 0.747 5.377 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_0 SLICE_X20Y75 LUT3 (Prop_lut3_I0_O) 0.124 5.501 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[5]_inst_i_1/O net (fo=2, routed) 3.467 8.968 ext_ram_data_IOBUF[5]_inst/I AE21 OBUFT (Prop_obuft_I_O) 3.564 12.533 r ext_ram_data_IOBUF[5]_inst/OBUFT/O net (fo=1, unset) 0.000 12.533 ext_ram_data[5] AE21 r ext_ram_data[5] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.533 ------------------------------------------------------------------- slack 0.790 Slack (MET) : 0.795ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[2] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.935ns (logic 5.281ns (35.363%) route 9.654ns (64.637%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=136, routed) 1.300 2.389 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/ADDRB0 SLICE_X20Y84 RAMD32 (Prop_ramd32_RADR0_O) 0.152 2.541 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMB/O net (fo=1, routed) 0.661 3.203 u_matmul_axi_slave/ep_rd_c1[2] SLICE_X23Y83 LUT4 (Prop_lut4_I0_O) 0.348 3.551 r u_matmul_axi_slave/ram_reg_i_68/O net (fo=1, routed) 0.507 4.057 u_matmul_axi_slave/ram_reg_i_68_n_0 SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.181 r u_matmul_axi_slave/ram_reg_i_50/O net (fo=1, routed) 0.598 4.780 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[2] SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.904 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_34/O net (fo=3, routed) 0.464 5.368 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[2] SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.492 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[2]_inst_i_1/O net (fo=2, routed) 3.454 8.946 ext_ram_data_IOBUF[2]_inst/I AF23 OBUFT (Prop_obuft_I_O) 3.581 12.528 r ext_ram_data_IOBUF[2]_inst/OBUFT/O net (fo=1, unset) 0.000 12.528 ext_ram_data[2] AF23 r ext_ram_data[2] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.528 ------------------------------------------------------------------- slack 0.795 Slack (MET) : 0.796ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.934ns (logic 5.264ns (35.250%) route 9.670ns (64.750%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT6=4 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=136, routed) 1.303 2.393 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA0 SLICE_X22Y84 RAMD32 (Prop_ramd32_RADR0_O) 0.150 2.543 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.961 3.504 u_matmul_axi_slave/ep_rd_c0[0] SLICE_X24Y82 LUT4 (Prop_lut4_I2_O) 0.328 3.832 r u_matmul_axi_slave/ram_reg_i_73/O net (fo=1, routed) 0.667 4.499 u_matmul_axi_slave/ram_reg_i_73_n_0 SLICE_X24Y82 LUT6 (Prop_lut6_I0_O) 0.124 4.623 r u_matmul_axi_slave/ram_reg_i_52/O net (fo=1, routed) 0.414 5.036 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[0] SLICE_X26Y82 LUT6 (Prop_lut6_I5_O) 0.124 5.160 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_36/O net (fo=3, routed) 0.309 5.470 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X27Y83 LUT3 (Prop_lut3_I0_O) 0.124 5.594 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.346 8.940 ext_ram_data_IOBUF[0]_inst/I AF24 OBUFT (Prop_obuft_I_O) 3.586 12.526 r ext_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.526 ext_ram_data[0] AF24 r ext_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.526 ------------------------------------------------------------------- slack 0.796 Slack (MET) : 0.801ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ch_mode_reg[2][1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_addr[15] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.932ns (logic 4.764ns (31.902%) route 10.168ns (68.098%)) Logic Levels: 7 (LUT3=2 LUT5=1 LUT6=3 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.865ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.411ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.931 -2.411 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X37Y90 FDRE r u_snix_axil_cdma_mux_8ch/ch_mode_reg[2][1]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y90 FDRE (Prop_fdre_C_Q) 0.456 -1.955 r u_snix_axil_cdma_mux_8ch/ch_mode_reg[2][1]/Q net (fo=3, routed) 1.018 -0.936 u_snix_axil_cdma_mux_8ch/u_core_engine/ep_axi_addr_reg[0]_2[1] SLICE_X37Y90 LUT6 (Prop_lut6_I5_O) 0.124 -0.812 r u_snix_axil_cdma_mux_8ch/u_core_engine/FSM_onehot_ep_state[6]_i_10/O net (fo=62, routed) 0.448 -0.364 u_snix_axil_cdma_mux_8ch/u_core_engine_n_398 SLICE_X36Y89 LUT3 (Prop_lut3_I1_O) 0.124 -0.240 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_30_35_i_9__1/O net (fo=103, routed) 1.352 1.112 u_snix_axil_cdma_mux_8ch/u_core_engine/_zz_ram_port1_reg[31]_3 SLICE_X49Y96 LUT5 (Prop_lut5_I1_O) 0.124 1.236 r u_snix_axil_cdma_mux_8ch/u_core_engine/ram_reg_0_3_12_17_i_9/O net (fo=2, routed) 1.285 2.521 u_Axi_CDC/arFifo/dma_m_araddr[17] SLICE_X41Y81 LUT3 (Prop_lut3_I2_O) 0.124 2.645 r u_Axi_CDC/arFifo/ax_req_q_addr[17]_i_2/O net (fo=3, routed) 1.789 4.434 u_Axi_CDC/arFifo/ram_araddr[15] SLICE_X8Y70 LUT6 (Prop_lut6_I0_O) 0.124 4.558 r u_Axi_CDC/arFifo/base_ram_addr_OBUF[15]_inst_i_3/O net (fo=1, routed) 0.884 5.442 u_axi_ram/u_axi_sram_sp/ext_ram_addr[15] SLICE_X2Y64 LUT6 (Prop_lut6_I2_O) 0.124 5.566 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[15]_inst_i_1/O net (fo=2, routed) 3.391 8.958 ext_ram_addr_OBUF[15] AF17 OBUF (Prop_obuf_I_O) 3.564 12.521 r ext_ram_addr_OBUF[15]_inst/O net (fo=0) 0.000 12.521 ext_ram_addr[15] AF17 r ext_ram_addr[15] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.521 ------------------------------------------------------------------- slack 0.801 Slack (MET) : 0.801ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[29] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.850ns (logic 6.891ns (46.403%) route 7.959ns (53.597%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.175 8.970 base_ram_data_IOBUF[29]_inst/T N23 OBUFT (TriStatE_obuft_T_O) 3.551 12.521 r base_ram_data_IOBUF[29]_inst/OBUFT/O net (fo=1, unset) 0.000 12.521 base_ram_data[29] N23 r base_ram_data[29] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.521 ------------------------------------------------------------------- slack 0.801 Slack (MET) : 0.821ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_we_n (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.830ns (logic 6.884ns (46.415%) route 7.947ns (53.585%)) Logic Levels: 13 (CARRY4=6 LUT2=1 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.411 7.306 u_axi_ram/u_axi_sram_sp/ax_req_q_burst_reg[0]_0 SLICE_X1Y21 LUT2 (Prop_lut2_I0_O) 0.124 7.430 r u_axi_ram/u_axi_sram_sp/ext_ram_we_n_OBUF_inst_i_1/O net (fo=1, routed) 1.529 8.958 ext_ram_we_n_OBUF AD19 OBUF (Prop_obuf_I_O) 3.544 12.502 r ext_ram_we_n_OBUF_inst/O net (fo=0) 0.000 12.502 ext_ram_we_n AD19 r ext_ram_we_n (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.502 ------------------------------------------------------------------- slack 0.821 Slack (MET) : 0.822ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.828ns (logic 6.867ns (46.312%) route 7.961ns (53.688%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.177 8.973 base_ram_data_IOBUF[16]_inst/T P21 OBUFT (TriStatE_obuft_T_O) 3.527 12.500 r base_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.500 base_ram_data[16] P21 r base_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.500 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.823ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.828ns (logic 6.871ns (46.339%) route 7.957ns (53.661%)) Logic Levels: 13 (CARRY4=6 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.454 5.348 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] SLICE_X0Y74 LUT6 (Prop_lut6_I5_O) 0.124 5.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O net (fo=1, routed) 3.496 8.968 base_ram_be_n_OBUF[0] L20 OBUF (Prop_obuf_I_O) 3.531 12.499 r base_ram_be_n_OBUF[0]_inst/O net (fo=0) 0.000 12.499 base_ram_be_n[0] L20 r base_ram_be_n[0] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.499 ------------------------------------------------------------------- slack 0.823 Slack (MET) : 0.828ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[2] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.822ns (logic 6.875ns (46.384%) route 7.947ns (53.616%)) Logic Levels: 13 (CARRY4=6 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.593 5.487 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X0Y74 LUT6 (Prop_lut6_I5_O) 0.124 5.611 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[2]_inst_i_1/O net (fo=1, routed) 3.348 8.959 base_ram_be_n_OBUF[2] L23 OBUF (Prop_obuf_I_O) 3.535 12.494 r base_ram_be_n_OBUF[2]_inst/O net (fo=0) 0.000 12.494 base_ram_be_n[2] L23 r base_ram_be_n[2] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.494 ------------------------------------------------------------------- slack 0.828 Slack (MET) : 0.837ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[26] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.814ns (logic 6.873ns (46.396%) route 7.941ns (53.604%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.157 8.952 base_ram_data_IOBUF[26]_inst/T R21 OBUFT (TriStatE_obuft_T_O) 3.533 12.485 r base_ram_data_IOBUF[26]_inst/OBUFT/O net (fo=1, unset) 0.000 12.485 base_ram_data[26] R21 r base_ram_data[26] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.485 ------------------------------------------------------------------- slack 0.837 Slack (MET) : 0.840ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_addr[8] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.811ns (logic 6.738ns (45.495%) route 8.072ns (54.505%)) Logic Levels: 12 (CARRY4=6 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.832 4.091 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y68 LUT6 (Prop_lut6_I5_O) 0.313 4.404 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[8]_inst_i_2/O net (fo=2, routed) 0.840 5.244 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[8]_inst_i_2_n_0 SLICE_X3Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.368 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[8]_inst_i_1/O net (fo=2, routed) 3.591 8.960 ext_ram_addr_OBUF[8] AA17 OBUF (Prop_obuf_I_O) 3.522 12.482 r ext_ram_addr_OBUF[8]_inst/O net (fo=0) 0.000 12.482 ext_ram_addr[8] AA17 r ext_ram_addr[8] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.482 ------------------------------------------------------------------- slack 0.840 Slack (MET) : 0.849ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_oe_n (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.802ns (logic 6.872ns (46.430%) route 7.929ns (53.570%)) Logic Levels: 13 (CARRY4=6 LUT2=1 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 1.354 6.248 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y53 LUT2 (Prop_lut2_I1_O) 0.124 6.372 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_oe_n_OBUF_inst_i_1/O net (fo=1, routed) 2.568 8.941 ext_ram_oe_n_OBUF AB19 OBUF (Prop_obuf_I_O) 3.532 12.473 r ext_ram_oe_n_OBUF_inst/O net (fo=0) 0.000 12.473 ext_ram_oe_n AB19 r ext_ram_oe_n (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.473 ------------------------------------------------------------------- slack 0.849 Slack (MET) : 0.871ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[5] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.859ns (logic 4.987ns (33.560%) route 9.872ns (66.440%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.421 2.399 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRC1 SLICE_X22Y84 RAMD32 (Prop_ramd32_RADR1_O) 0.124 2.523 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/O net (fo=1, routed) 0.664 3.188 u_matmul_axi_slave/ep_rd_c0[5] SLICE_X24Y84 LUT4 (Prop_lut4_I2_O) 0.124 3.312 r u_matmul_axi_slave/ram_reg_i_65/O net (fo=1, routed) 0.582 3.893 u_matmul_axi_slave/ram_reg_i_65_n_0 SLICE_X26Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.017 r u_matmul_axi_slave/ram_reg_i_47/O net (fo=1, routed) 0.489 4.506 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[5] SLICE_X26Y81 LUT6 (Prop_lut6_I5_O) 0.124 4.630 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_31/O net (fo=4, routed) 0.747 5.377 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_0 SLICE_X20Y75 LUT3 (Prop_lut3_I0_O) 0.124 5.501 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[5]_inst_i_1/O net (fo=2, routed) 3.411 8.912 base_ram_data_IOBUF[5]_inst/I P24 OBUFT (Prop_obuft_I_O) 3.539 12.451 r base_ram_data_IOBUF[5]_inst/OBUFT/O net (fo=1, unset) 0.000 12.451 base_ram_data[5] P24 r base_ram_data[5] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.451 ------------------------------------------------------------------- slack 0.871 Slack (MET) : 0.872ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[29] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.858ns (logic 4.995ns (33.620%) route 9.863ns (66.380%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.324 2.301 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/ADDRC1 SLICE_X22Y82 RAMD32 (Prop_ramd32_RADR1_O) 0.124 2.425 r u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMC_D1/O net (fo=1, routed) 0.709 3.134 u_matmul_axi_slave/ep_rd_c0[29] SLICE_X24Y82 LUT4 (Prop_lut4_I2_O) 0.124 3.258 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_23__0/O net (fo=1, routed) 0.481 3.738 u_matmul_axi_slave/ram_reg_0_7_24_29_i_23__0_n_0 SLICE_X25Y82 LUT5 (Prop_lut5_I4_O) 0.124 3.862 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_17__0/O net (fo=1, routed) 0.578 4.441 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[29] SLICE_X30Y81 LUT6 (Prop_lut6_I5_O) 0.124 4.565 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_11__1/O net (fo=3, routed) 0.456 5.021 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[29] SLICE_X31Y82 LUT3 (Prop_lut3_I0_O) 0.124 5.145 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[29]_inst_i_1/O net (fo=2, routed) 3.758 8.903 ext_ram_data_IOBUF[29]_inst/I AC21 OBUFT (Prop_obuft_I_O) 3.547 12.451 r ext_ram_data_IOBUF[29]_inst/OBUFT/O net (fo=1, unset) 0.000 12.451 ext_ram_data[29] AC21 r ext_ram_data[29] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.451 ------------------------------------------------------------------- slack 0.872 Slack (MET) : 0.875ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[23] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.776ns (logic 6.875ns (46.530%) route 7.901ns (53.470%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.116 8.912 base_ram_data_IOBUF[23]_inst/T N21 OBUFT (TriStatE_obuft_T_O) 3.535 12.447 r base_ram_data_IOBUF[23]_inst/OBUFT/O net (fo=1, unset) 0.000 12.447 base_ram_data[23] N21 r base_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.447 ------------------------------------------------------------------- slack 0.875 Slack (MET) : 0.889ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.762ns (logic 6.871ns (46.543%) route 7.891ns (53.457%)) Logic Levels: 13 (CARRY4=6 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.457 5.351 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X0Y74 LUT6 (Prop_lut6_I5_O) 0.124 5.475 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O net (fo=1, routed) 3.427 8.903 base_ram_be_n_OBUF[1] L22 OBUF (Prop_obuf_I_O) 3.531 12.433 r base_ram_be_n_OBUF[1]_inst/O net (fo=0) 0.000 12.433 base_ram_be_n[1] L22 r base_ram_be_n[1] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.433 ------------------------------------------------------------------- slack 0.889 Slack (MET) : 0.896ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[7] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.834ns (logic 4.899ns (33.025%) route 9.935ns (66.975%)) Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1 SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O) 0.124 2.792 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB_D1/O net (fo=1, routed) 1.211 4.003 u_matmul_axi_slave/ep_rd_c1[39] SLICE_X21Y80 LUT5 (Prop_lut5_I3_O) 0.124 4.127 r u_matmul_axi_slave/ram_reg_i_45/O net (fo=1, routed) 0.499 4.626 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[7] SLICE_X17Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.750 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_29/O net (fo=4, routed) 0.556 5.306 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_2 SLICE_X15Y79 LUT3 (Prop_lut3_I0_O) 0.124 5.430 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[7]_inst_i_1/O net (fo=2, routed) 3.422 8.852 ext_ram_data_IOBUF[7]_inst/I AF20 OBUFT (Prop_obuft_I_O) 3.575 12.426 r ext_ram_data_IOBUF[7]_inst/OBUFT/O net (fo=1, unset) 0.000 12.426 ext_ram_data[7] AF20 r ext_ram_data[7] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.426 ------------------------------------------------------------------- slack 0.896 Slack (MET) : 0.897ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[28] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.754ns (logic 6.876ns (46.603%) route 7.878ns (53.397%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.094 8.890 base_ram_data_IOBUF[28]_inst/T N22 OBUFT (TriStatE_obuft_T_O) 3.536 12.425 r base_ram_data_IOBUF[28]_inst/OBUFT/O net (fo=1, unset) 0.000 12.425 base_ram_data[28] N22 r base_ram_data[28] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.425 ------------------------------------------------------------------- slack 0.897 Slack (MET) : 0.940ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.711ns (logic 6.892ns (46.850%) route 7.819ns (53.150%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.035 8.830 base_ram_data_IOBUF[22]_inst/T N24 OBUFT (TriStatE_obuft_T_O) 3.552 12.383 r base_ram_data_IOBUF[22]_inst/OBUFT/O net (fo=1, unset) 0.000 12.383 base_ram_data[22] N24 r base_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.383 ------------------------------------------------------------------- slack 0.940 Slack (MET) : 0.944ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[28] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.707ns (logic 6.908ns (46.969%) route 7.799ns (53.031%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.134 8.811 ext_ram_data_IOBUF[28]_inst/T AD21 OBUFT (TriStatE_obuft_T_O) 3.568 12.378 r ext_ram_data_IOBUF[28]_inst/OBUFT/O net (fo=1, unset) 0.000 12.378 ext_ram_data[28] AD21 r ext_ram_data[28] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.378 ------------------------------------------------------------------- slack 0.944 Slack (MET) : 0.945ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[4] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.706ns (logic 6.913ns (47.012%) route 7.792ns (52.988%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.008 8.804 base_ram_data_IOBUF[4]_inst/T N26 OBUFT (TriStatE_obuft_T_O) 3.573 12.377 r base_ram_data_IOBUF[4]_inst/OBUFT/O net (fo=1, unset) 0.000 12.377 base_ram_data[4] N26 r base_ram_data[4] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.377 ------------------------------------------------------------------- slack 0.945 Slack (MET) : 0.953ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[7] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.698ns (logic 6.900ns (46.942%) route 7.799ns (53.058%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.014 8.810 base_ram_data_IOBUF[7]_inst/T P25 OBUFT (TriStatE_obuft_T_O) 3.560 12.370 r base_ram_data_IOBUF[7]_inst/OBUFT/O net (fo=1, unset) 0.000 12.370 base_ram_data[7] P25 r base_ram_data[7] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.370 ------------------------------------------------------------------- slack 0.953 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sys_clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X2Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X2Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y9 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X2Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X2Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y6 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y121 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[34]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y121 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[35]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[36]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[37]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[38]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[39]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X11Y112 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[3]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[40]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[41]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[42]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[43]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X69Y104 cdma_axil_b_bridge_reg/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X46Y92 u_matmul_axi_slave/b0_b_reg[0][0]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X72Y108 cdma_axil_r_bridge_reg/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X67Y105 cdma_axil_wr_active_reg/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X69Y105 cdma_axil_wr_bridge_hold_reg/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X12Y105 u_matmul_axi_slave/b0_b_reg[0][10]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X19Y92 u_matmul_axi_slave/b0_b_reg[0][11]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y79 u_matmul_axi_slave/b0_b_reg[0][12]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X4Y86 u_matmul_axi_slave/b0_b_reg[0][13]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X22Y103 u_matmul_axi_slave/b0_b_reg[0][14]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X2Y94 u_matmul_axi_slave/b0_b_reg[0][15]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X4Y86 u_matmul_axi_slave/b0_b_reg[0][16]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X37Y77 u_matmul_axi_slave/b0_b_reg[0][17]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X34Y76 u_matmul_axi_slave/b0_b_reg[0][18]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X47Y74 u_matmul_axi_slave/b0_b_reg[0][19]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X19Y92 u_matmul_axi_slave/b0_b_reg[0][1]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X46Y78 u_matmul_axi_slave/b0_b_reg[0][20]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y69 u_matmul_axi_slave/b0_b_reg[0][21]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X2Y94 u_matmul_axi_slave/b0_b_reg[0][22]/C Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: cpu_clk To Clock: cpu_clk Setup : 0 Failing Endpoints, Worst Slack 26.018ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 26.018ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 26.696 arrival time -0.678 ------------------------------------------------------------------- slack 26.018 Slack (MET) : 26.018ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 26.696 arrival time -0.678 ------------------------------------------------------------------- slack 26.018 Slack (MET) : 26.018ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 26.696 arrival time -0.678 ------------------------------------------------------------------- slack 26.018 Slack (MET) : 26.018ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 26.696 arrival time -0.678 ------------------------------------------------------------------- slack 26.018 Slack (MET) : 26.062ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.361 26.740 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 26.740 arrival time -0.678 ------------------------------------------------------------------- slack 26.062 Slack (MET) : 26.062ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.361 26.740 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 26.740 arrival time -0.678 ------------------------------------------------------------------- slack 26.062 Slack (MET) : 26.104ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.782 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 26.782 arrival time -0.678 ------------------------------------------------------------------- slack 26.104 Slack (MET) : 26.104ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.782 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 26.782 arrival time -0.678 ------------------------------------------------------------------- slack 26.104 Slack (MET) : 26.156ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.270ns (logic 0.642ns (19.635%) route 2.628ns (80.365%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.299ns = ( 27.701 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.986 0.592 u_Axi_CDC/wFifo/p_0_in SLICE_X89Y127 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.529 27.701 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y127 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.435 27.266 clock uncertainty -0.113 27.153 SLICE_X89Y127 FDCE (Recov_fdce_C_CLR) -0.405 26.748 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 26.748 arrival time -0.592 ------------------------------------------------------------------- slack 26.156 Slack (MET) : 26.156ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.270ns (logic 0.642ns (19.635%) route 2.628ns (80.365%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.299ns = ( 27.701 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.986 0.592 u_Axi_CDC/wFifo/p_0_in SLICE_X89Y127 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.529 27.701 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y127 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C clock pessimism -0.435 27.266 clock uncertainty -0.113 27.153 SLICE_X89Y127 FDCE (Recov_fdce_C_CLR) -0.405 26.748 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2] ------------------------------------------------------------------- required time 26.748 arrival time -0.592 ------------------------------------------------------------------- slack 26.156 Slack (MET) : 26.290ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.507 27.212 clock uncertainty -0.113 27.099 SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.361 26.738 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 26.738 arrival time -0.448 ------------------------------------------------------------------- slack 26.290 Slack (MET) : 26.332ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.507 27.212 clock uncertainty -0.113 27.099 SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.319 26.780 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 26.780 arrival time -0.448 ------------------------------------------------------------------- slack 26.332 Slack (MET) : 26.332ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.507 27.212 clock uncertainty -0.113 27.099 SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.319 26.780 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 26.780 arrival time -0.448 ------------------------------------------------------------------- slack 26.332 Slack (MET) : 26.332ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C clock pessimism -0.507 27.212 clock uncertainty -0.113 27.099 SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.319 26.780 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 26.780 arrival time -0.448 ------------------------------------------------------------------- slack 26.332 Slack (MET) : 26.351ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C clock pessimism -0.507 27.213 clock uncertainty -0.113 27.100 SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.361 26.739 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 26.739 arrival time -0.388 ------------------------------------------------------------------- slack 26.351 Slack (MET) : 26.393ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C clock pessimism -0.507 27.213 clock uncertainty -0.113 27.100 SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.781 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 26.781 arrival time -0.388 ------------------------------------------------------------------- slack 26.393 Slack (MET) : 26.393ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C clock pessimism -0.507 27.213 clock uncertainty -0.113 27.100 SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.781 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 26.781 arrival time -0.388 ------------------------------------------------------------------- slack 26.393 Slack (MET) : 26.393ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/C clock pessimism -0.507 27.213 clock uncertainty -0.113 27.100 SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.781 u_Axi_CDC/rFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- required time 26.781 arrival time -0.388 ------------------------------------------------------------------- slack 26.393 Slack (MET) : 26.825ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.435 27.267 clock uncertainty -0.113 27.154 SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 26.749 arrival time 0.077 ------------------------------------------------------------------- slack 26.825 Slack (MET) : 26.825ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.435 27.267 clock uncertainty -0.113 27.154 SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 26.749 arrival time 0.077 ------------------------------------------------------------------- slack 26.825 Slack (MET) : 26.825ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.435 27.267 clock uncertainty -0.113 27.154 SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 26.749 arrival time 0.077 ------------------------------------------------------------------- slack 26.825 Slack (MET) : 26.825ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.435 27.267 clock uncertainty -0.113 27.154 SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 26.749 arrival time 0.077 ------------------------------------------------------------------- slack 26.825 Slack (MET) : 26.825ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.435 27.267 clock uncertainty -0.113 27.154 SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 26.749 arrival time 0.077 ------------------------------------------------------------------- slack 26.825 Slack (MET) : 26.825ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.435 27.267 clock uncertainty -0.113 27.154 SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 26.749 arrival time 0.077 ------------------------------------------------------------------- slack 26.825 Slack (MET) : 26.890ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.532ns (logic 0.642ns (25.351%) route 1.890ns (74.649%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.302ns = ( 27.698 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.249 -0.145 u_Axi_CDC/wFifo/p_0_in SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.526 27.698 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.435 27.263 clock uncertainty -0.113 27.150 SLICE_X89Y125 FDCE (Recov_fdce_C_CLR) -0.405 26.745 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 26.745 arrival time 0.145 ------------------------------------------------------------------- slack 26.890 Slack (MET) : 26.890ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.532ns (logic 0.642ns (25.351%) route 1.890ns (74.649%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.302ns = ( 27.698 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.249 -0.145 u_Axi_CDC/wFifo/p_0_in SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.526 27.698 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.435 27.263 clock uncertainty -0.113 27.150 SLICE_X89Y125 FDCE (Recov_fdce_C_CLR) -0.405 26.745 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 26.745 arrival time 0.145 ------------------------------------------------------------------- slack 26.890 Slack (MET) : 26.890ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.532ns (logic 0.642ns (25.351%) route 1.890ns (74.649%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.302ns = ( 27.698 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.249 -0.145 u_Axi_CDC/wFifo/p_0_in SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.526 27.698 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C clock pessimism -0.435 27.263 clock uncertainty -0.113 27.150 SLICE_X89Y125 FDCE (Recov_fdce_C_CLR) -0.405 26.745 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3] ------------------------------------------------------------------- required time 26.745 arrival time 0.145 ------------------------------------------------------------------- slack 26.890 Slack (MET) : 26.890ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.532ns (logic 0.642ns (25.351%) route 1.890ns (74.649%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.302ns = ( 27.698 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.249 -0.145 u_Axi_CDC/wFifo/p_0_in SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.526 27.698 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.435 27.263 clock uncertainty -0.113 27.150 SLICE_X89Y125 FDCE (Recov_fdce_C_CLR) -0.405 26.745 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 26.745 arrival time 0.145 ------------------------------------------------------------------- slack 26.890 Slack (MET) : 26.890ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.532ns (logic 0.642ns (25.351%) route 1.890ns (74.649%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.302ns = ( 27.698 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.249 -0.145 u_Axi_CDC/wFifo/p_0_in SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.526 27.698 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.435 27.263 clock uncertainty -0.113 27.150 SLICE_X89Y125 FDCE (Recov_fdce_C_CLR) -0.405 26.745 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 26.745 arrival time 0.145 ------------------------------------------------------------------- slack 26.890 Slack (MET) : 26.954ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X91Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.435 27.269 clock uncertainty -0.113 27.156 SLICE_X91Y126 FDCE (Recov_fdce_C_CLR) -0.405 26.751 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 26.751 arrival time 0.203 ------------------------------------------------------------------- slack 26.954 Slack (MET) : 26.954ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X91Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.435 27.269 clock uncertainty -0.113 27.156 SLICE_X91Y126 FDCE (Recov_fdce_C_CLR) -0.405 26.751 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 26.751 arrival time 0.203 ------------------------------------------------------------------- slack 26.954 Slack (MET) : 26.973ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.454ns (logic 0.642ns (26.165%) route 1.812ns (73.835%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.170 -0.224 u_Axi_CDC/arFifo/p_0_in SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.435 27.267 clock uncertainty -0.113 27.154 SLICE_X86Y105 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 26.749 arrival time 0.224 ------------------------------------------------------------------- slack 26.973 Slack (MET) : 26.973ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.454ns (logic 0.642ns (26.165%) route 1.812ns (73.835%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.170 -0.224 u_Axi_CDC/arFifo/p_0_in SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.435 27.267 clock uncertainty -0.113 27.154 SLICE_X86Y105 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 26.749 arrival time 0.224 ------------------------------------------------------------------- slack 26.973 Slack (MET) : 26.973ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.454ns (logic 0.642ns (26.165%) route 1.812ns (73.835%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.170 -0.224 u_Axi_CDC/arFifo/p_0_in SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.435 27.267 clock uncertainty -0.113 27.154 SLICE_X86Y105 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 26.749 arrival time 0.224 ------------------------------------------------------------------- slack 26.973 Slack (MET) : 26.973ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.454ns (logic 0.642ns (26.165%) route 1.812ns (73.835%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.170 -0.224 u_Axi_CDC/arFifo/p_0_in SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.435 27.267 clock uncertainty -0.113 27.154 SLICE_X86Y105 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 26.749 arrival time 0.224 ------------------------------------------------------------------- slack 26.973 Slack (MET) : 26.973ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.454ns (logic 0.642ns (26.165%) route 1.812ns (73.835%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.170 -0.224 u_Axi_CDC/arFifo/p_0_in SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.435 27.267 clock uncertainty -0.113 27.154 SLICE_X86Y105 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 26.749 arrival time 0.224 ------------------------------------------------------------------- slack 26.973 Slack (MET) : 26.998ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.435 27.269 clock uncertainty -0.113 27.156 SLICE_X90Y126 FDCE (Recov_fdce_C_CLR) -0.361 26.795 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 26.795 arrival time 0.203 ------------------------------------------------------------------- slack 26.998 Slack (MET) : 26.998ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.435 27.269 clock uncertainty -0.113 27.156 SLICE_X90Y126 FDCE (Recov_fdce_C_CLR) -0.361 26.795 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 26.795 arrival time 0.203 ------------------------------------------------------------------- slack 26.998 Slack (MET) : 26.998ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.435 27.269 clock uncertainty -0.113 27.156 SLICE_X90Y126 FDCE (Recov_fdce_C_CLR) -0.361 26.795 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 26.795 arrival time 0.203 ------------------------------------------------------------------- slack 26.998 Slack (MET) : 27.040ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.435 27.269 clock uncertainty -0.113 27.156 SLICE_X90Y126 FDCE (Recov_fdce_C_CLR) -0.319 26.837 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 26.837 arrival time 0.203 ------------------------------------------------------------------- slack 27.040 Slack (MET) : 27.040ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.435 27.269 clock uncertainty -0.113 27.156 SLICE_X90Y126 FDCE (Recov_fdce_C_CLR) -0.319 26.837 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 26.837 arrival time 0.203 ------------------------------------------------------------------- slack 27.040 Slack (MET) : 27.040ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.435 27.269 clock uncertainty -0.113 27.156 SLICE_X90Y126 FDCE (Recov_fdce_C_CLR) -0.319 26.837 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 26.837 arrival time 0.203 ------------------------------------------------------------------- slack 27.040 Slack (MET) : 27.372ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.132ns (logic 0.642ns (30.109%) route 1.490ns (69.891%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.849 -0.545 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.418 27.301 clock uncertainty -0.113 27.188 SLICE_X92Y111 FDCE (Recov_fdce_C_CLR) -0.361 26.827 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 26.827 arrival time 0.545 ------------------------------------------------------------------- slack 27.372 Slack (MET) : 27.372ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.132ns (logic 0.642ns (30.109%) route 1.490ns (69.891%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.849 -0.545 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.418 27.301 clock uncertainty -0.113 27.188 SLICE_X92Y111 FDCE (Recov_fdce_C_CLR) -0.361 26.827 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 26.827 arrival time 0.545 ------------------------------------------------------------------- slack 27.372 Slack (MET) : 27.372ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.132ns (logic 0.642ns (30.109%) route 1.490ns (69.891%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.849 -0.545 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.418 27.301 clock uncertainty -0.113 27.188 SLICE_X92Y111 FDCE (Recov_fdce_C_CLR) -0.361 26.827 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 26.827 arrival time 0.545 ------------------------------------------------------------------- slack 27.372 Slack (MET) : 27.414ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.132ns (logic 0.642ns (30.109%) route 1.490ns (69.891%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.849 -0.545 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.418 27.301 clock uncertainty -0.113 27.188 SLICE_X92Y111 FDCE (Recov_fdce_C_CLR) -0.319 26.869 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 26.869 arrival time 0.545 ------------------------------------------------------------------- slack 27.414 Slack (MET) : 27.414ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.132ns (logic 0.642ns (30.109%) route 1.490ns (69.891%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.849 -0.545 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.418 27.301 clock uncertainty -0.113 27.188 SLICE_X92Y111 FDCE (Recov_fdce_C_CLR) -0.319 26.869 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 26.869 arrival time 0.545 ------------------------------------------------------------------- slack 27.414 Slack (MET) : 27.414ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.132ns (logic 0.642ns (30.109%) route 1.490ns (69.891%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.849 -0.545 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.418 27.301 clock uncertainty -0.113 27.188 SLICE_X92Y111 FDCE (Recov_fdce_C_CLR) -0.319 26.869 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 26.869 arrival time 0.545 ------------------------------------------------------------------- slack 27.414 Slack (MET) : 27.482ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.976ns (logic 0.642ns (32.486%) route 1.334ns (67.514%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.023ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.283ns = ( 27.717 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.693 -0.701 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.545 27.717 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.418 27.299 clock uncertainty -0.113 27.186 SLICE_X93Y113 FDCE (Recov_fdce_C_CLR) -0.405 26.781 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 26.781 arrival time 0.701 ------------------------------------------------------------------- slack 27.482 Slack (MET) : 27.482ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.976ns (logic 0.642ns (32.486%) route 1.334ns (67.514%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.023ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.283ns = ( 27.717 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.693 -0.701 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.545 27.717 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.418 27.299 clock uncertainty -0.113 27.186 SLICE_X93Y113 FDCE (Recov_fdce_C_CLR) -0.405 26.781 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 26.781 arrival time 0.701 ------------------------------------------------------------------- slack 27.482 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: mlkem_clk To Clock: mlkem_clk Setup : 0 Failing Endpoints, Worst Slack 3.826ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.826ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.817ns (logic 0.642ns (7.282%) route 8.175ns (92.718%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 10.892 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.745 6.147 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X96Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.720 10.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X96Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/C clock pessimism -0.507 10.385 clock uncertainty -0.093 10.292 SLICE_X96Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.973 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22] ------------------------------------------------------------------- required time 9.973 arrival time -6.147 ------------------------------------------------------------------- slack 3.826 Slack (MET) : 3.860ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.747ns (logic 0.642ns (7.340%) route 8.105ns (92.660%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.102ns = ( 10.898 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.675 6.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X104Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.726 10.898 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X104Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/C clock pessimism -0.507 10.391 clock uncertainty -0.093 10.298 SLICE_X104Y85 FDCE (Recov_fdce_C_CLR) -0.361 9.937 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5] ------------------------------------------------------------------- required time 9.937 arrival time -6.077 ------------------------------------------------------------------- slack 3.860 Slack (MET) : 3.902ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.747ns (logic 0.642ns (7.340%) route 8.105ns (92.660%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.102ns = ( 10.898 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.675 6.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X104Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.726 10.898 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X104Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/C clock pessimism -0.507 10.391 clock uncertainty -0.093 10.298 SLICE_X104Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26] ------------------------------------------------------------------- required time 9.979 arrival time -6.077 ------------------------------------------------------------------- slack 3.902 Slack (MET) : 4.068ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/C clock pessimism -0.507 10.381 clock uncertainty -0.093 10.288 SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22] ------------------------------------------------------------------- required time 9.883 arrival time -5.815 ------------------------------------------------------------------- slack 4.068 Slack (MET) : 4.068ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/C clock pessimism -0.507 10.381 clock uncertainty -0.093 10.288 SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8] ------------------------------------------------------------------- required time 9.883 arrival time -5.815 ------------------------------------------------------------------- slack 4.068 Slack (MET) : 4.068ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/C clock pessimism -0.507 10.381 clock uncertainty -0.093 10.288 SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9] ------------------------------------------------------------------- required time 9.883 arrival time -5.815 ------------------------------------------------------------------- slack 4.068 Slack (MET) : 4.115ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12] ------------------------------------------------------------------- required time 9.884 arrival time -5.769 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.115ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31] ------------------------------------------------------------------- required time 9.884 arrival time -5.769 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.115ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3] ------------------------------------------------------------------- required time 9.884 arrival time -5.769 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.115ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4] ------------------------------------------------------------------- required time 9.884 arrival time -5.769 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.115ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5] ------------------------------------------------------------------- required time 9.884 arrival time -5.769 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.115ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6] ------------------------------------------------------------------- required time 9.884 arrival time -5.769 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.154ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X94Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X94Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/C clock pessimism -0.507 10.381 clock uncertainty -0.093 10.288 SLICE_X94Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6] ------------------------------------------------------------------- required time 9.969 arrival time -5.815 ------------------------------------------------------------------- slack 4.154 Slack (MET) : 4.154ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X94Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X94Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/C clock pessimism -0.507 10.381 clock uncertainty -0.093 10.288 SLICE_X94Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8] ------------------------------------------------------------------- required time 9.969 arrival time -5.815 ------------------------------------------------------------------- slack 4.154 Slack (MET) : 4.159ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X100Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X100Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X100Y86 FDCE (Recov_fdce_C_CLR) -0.361 9.928 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26] ------------------------------------------------------------------- required time 9.928 arrival time -5.769 ------------------------------------------------------------------- slack 4.159 Slack (MET) : 4.201ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X100Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X100Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X100Y86 FDCE (Recov_fdce_C_CLR) -0.319 9.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25] ------------------------------------------------------------------- required time 9.970 arrival time -5.769 ------------------------------------------------------------------- slack 4.201 Slack (MET) : 4.223ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/C clock pessimism -0.507 10.384 clock uncertainty -0.093 10.291 SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24] ------------------------------------------------------------------- required time 9.886 arrival time -5.662 ------------------------------------------------------------------- slack 4.223 Slack (MET) : 4.223ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/C clock pessimism -0.507 10.384 clock uncertainty -0.093 10.291 SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27] ------------------------------------------------------------------- required time 9.886 arrival time -5.662 ------------------------------------------------------------------- slack 4.223 Slack (MET) : 4.223ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/C clock pessimism -0.507 10.384 clock uncertainty -0.093 10.291 SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4] ------------------------------------------------------------------- required time 9.886 arrival time -5.662 ------------------------------------------------------------------- slack 4.223 Slack (MET) : 4.223ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/C clock pessimism -0.507 10.384 clock uncertainty -0.093 10.291 SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7] ------------------------------------------------------------------- required time 9.886 arrival time -5.662 ------------------------------------------------------------------- slack 4.223 Slack (MET) : 4.224ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][22]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X95Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][22]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][22]/C clock pessimism -0.507 10.381 clock uncertainty -0.093 10.288 SLICE_X95Y98 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][22] ------------------------------------------------------------------- required time 9.883 arrival time -5.659 ------------------------------------------------------------------- slack 4.224 Slack (MET) : 4.224ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][6]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X95Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][6]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][6]/C clock pessimism -0.507 10.381 clock uncertainty -0.093 10.288 SLICE_X95Y98 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][6] ------------------------------------------------------------------- required time 9.883 arrival time -5.659 ------------------------------------------------------------------- slack 4.224 Slack (MET) : 4.224ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][8]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X95Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][8]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][8]/C clock pessimism -0.507 10.381 clock uncertainty -0.093 10.288 SLICE_X95Y98 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][8] ------------------------------------------------------------------- required time 9.883 arrival time -5.659 ------------------------------------------------------------------- slack 4.224 Slack (MET) : 4.275ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][13]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X99Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][13]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.715 10.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X99Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][13]/C clock pessimism -0.507 10.380 clock uncertainty -0.093 10.287 SLICE_X99Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][13] ------------------------------------------------------------------- required time 9.882 arrival time -5.607 ------------------------------------------------------------------- slack 4.275 Slack (MET) : 4.275ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][2]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X99Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.715 10.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X99Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][2]/C clock pessimism -0.507 10.380 clock uncertainty -0.093 10.287 SLICE_X99Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][2] ------------------------------------------------------------------- required time 9.882 arrival time -5.607 ------------------------------------------------------------------- slack 4.275 Slack (MET) : 4.275ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][3]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X99Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][3]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.715 10.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X99Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][3]/C clock pessimism -0.507 10.380 clock uncertainty -0.093 10.287 SLICE_X99Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][3] ------------------------------------------------------------------- required time 9.882 arrival time -5.607 ------------------------------------------------------------------- slack 4.275 Slack (MET) : 4.305ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.172ns (logic 0.642ns (7.856%) route 7.530ns (92.144%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 10.723 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.101 5.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X95Y101 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.551 10.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/C clock pessimism -0.418 10.305 clock uncertainty -0.093 10.212 SLICE_X95Y101 FDCE (Recov_fdce_C_CLR) -0.405 9.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2] ------------------------------------------------------------------- required time 9.807 arrival time -5.503 ------------------------------------------------------------------- slack 4.305 Slack (MET) : 4.309ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][24]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][24]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X102Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][24]/C clock pessimism -0.507 10.384 clock uncertainty -0.093 10.291 SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][24] ------------------------------------------------------------------- required time 9.972 arrival time -5.662 ------------------------------------------------------------------- slack 4.309 Slack (MET) : 4.309ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][26]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][26]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X102Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][26]/C clock pessimism -0.507 10.384 clock uncertainty -0.093 10.291 SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][26] ------------------------------------------------------------------- required time 9.972 arrival time -5.662 ------------------------------------------------------------------- slack 4.309 Slack (MET) : 4.309ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][5]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][5]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X102Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][5]/C clock pessimism -0.507 10.384 clock uncertainty -0.093 10.291 SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][5] ------------------------------------------------------------------- required time 9.972 arrival time -5.662 ------------------------------------------------------------------- slack 4.309 Slack (MET) : 4.309ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][7]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][7]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X102Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][7]/C clock pessimism -0.507 10.384 clock uncertainty -0.093 10.291 SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][7] ------------------------------------------------------------------- required time 9.972 arrival time -5.662 ------------------------------------------------------------------- slack 4.309 Slack (MET) : 4.310ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][6]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X94Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][6]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X94Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][6]/C clock pessimism -0.507 10.381 clock uncertainty -0.093 10.288 SLICE_X94Y98 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][6] ------------------------------------------------------------------- required time 9.969 arrival time -5.659 ------------------------------------------------------------------- slack 4.310 Slack (MET) : 4.319ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][19]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][19]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.715 10.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X98Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][19]/C clock pessimism -0.507 10.380 clock uncertainty -0.093 10.287 SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.361 9.926 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][19] ------------------------------------------------------------------- required time 9.926 arrival time -5.607 ------------------------------------------------------------------- slack 4.319 Slack (MET) : 4.319ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][2]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.715 10.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X98Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][2]/C clock pessimism -0.507 10.380 clock uncertainty -0.093 10.287 SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.361 9.926 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][2] ------------------------------------------------------------------- required time 9.926 arrival time -5.607 ------------------------------------------------------------------- slack 4.319 Slack (MET) : 4.361ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][12]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][12]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.715 10.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X98Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][12]/C clock pessimism -0.507 10.380 clock uncertainty -0.093 10.287 SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.319 9.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][12] ------------------------------------------------------------------- required time 9.968 arrival time -5.607 ------------------------------------------------------------------- slack 4.361 Slack (MET) : 4.361ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][29]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][29]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.715 10.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X98Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][29]/C clock pessimism -0.507 10.380 clock uncertainty -0.093 10.287 SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.319 9.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][29] ------------------------------------------------------------------- required time 9.968 arrival time -5.607 ------------------------------------------------------------------- slack 4.361 Slack (MET) : 4.382ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][25]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.173ns (logic 0.642ns (7.855%) route 7.531ns (92.145%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.101 5.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X103Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][25]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.718 10.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X103Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][25]/C clock pessimism -0.507 10.383 clock uncertainty -0.093 10.290 SLICE_X103Y84 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][25] ------------------------------------------------------------------- required time 9.885 arrival time -5.503 ------------------------------------------------------------------- slack 4.382 Slack (MET) : 4.382ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][6]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.173ns (logic 0.642ns (7.855%) route 7.531ns (92.145%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.101 5.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X103Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][6]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.718 10.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X103Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][6]/C clock pessimism -0.507 10.383 clock uncertainty -0.093 10.290 SLICE_X103Y84 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][6] ------------------------------------------------------------------- required time 9.885 arrival time -5.503 ------------------------------------------------------------------- slack 4.382 Slack (MET) : 4.406ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][25]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][25]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X99Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][25]/C clock pessimism -0.507 10.379 clock uncertainty -0.093 10.286 SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][25] ------------------------------------------------------------------- required time 9.881 arrival time -5.475 ------------------------------------------------------------------- slack 4.406 Slack (MET) : 4.406ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X99Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28]/C clock pessimism -0.507 10.379 clock uncertainty -0.093 10.286 SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28] ------------------------------------------------------------------- required time 9.881 arrival time -5.475 ------------------------------------------------------------------- slack 4.406 Slack (MET) : 4.406ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][2]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X99Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][2]/C clock pessimism -0.507 10.379 clock uncertainty -0.093 10.286 SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][2] ------------------------------------------------------------------- required time 9.881 arrival time -5.475 ------------------------------------------------------------------- slack 4.406 Slack (MET) : 4.406ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][3]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][3]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X99Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][3]/C clock pessimism -0.507 10.379 clock uncertainty -0.093 10.286 SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][3] ------------------------------------------------------------------- required time 9.881 arrival time -5.475 ------------------------------------------------------------------- slack 4.406 Slack (MET) : 4.420ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][12]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][12]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.718 10.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][12]/C clock pessimism -0.507 10.383 clock uncertainty -0.093 10.290 SLICE_X101Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][12] ------------------------------------------------------------------- required time 9.885 arrival time -5.465 ------------------------------------------------------------------- slack 4.420 Slack (MET) : 4.420ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][20]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][20]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.718 10.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][20]/C clock pessimism -0.507 10.383 clock uncertainty -0.093 10.290 SLICE_X101Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][20] ------------------------------------------------------------------- required time 9.885 arrival time -5.465 ------------------------------------------------------------------- slack 4.420 Slack (MET) : 4.420ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][3]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][3]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.718 10.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][3]/C clock pessimism -0.507 10.383 clock uncertainty -0.093 10.290 SLICE_X101Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][3] ------------------------------------------------------------------- required time 9.885 arrival time -5.465 ------------------------------------------------------------------- slack 4.420 Slack (MET) : 4.430ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][2]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X97Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][2]/C clock pessimism -0.507 10.379 clock uncertainty -0.093 10.286 SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][2] ------------------------------------------------------------------- required time 9.881 arrival time -5.450 ------------------------------------------------------------------- slack 4.430 Slack (MET) : 4.430ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X97Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]/C clock pessimism -0.507 10.379 clock uncertainty -0.093 10.286 SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31] ------------------------------------------------------------------- required time 9.881 arrival time -5.450 ------------------------------------------------------------------- slack 4.430 Slack (MET) : 4.430ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][7]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][7]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X97Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][7]/C clock pessimism -0.507 10.379 clock uncertainty -0.093 10.286 SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][7] ------------------------------------------------------------------- required time 9.881 arrival time -5.450 ------------------------------------------------------------------- slack 4.430 Slack (MET) : 4.430ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][8]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][8]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X97Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][8]/C clock pessimism -0.507 10.379 clock uncertainty -0.093 10.286 SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][8] ------------------------------------------------------------------- required time 9.881 arrival time -5.450 ------------------------------------------------------------------- slack 4.430 Slack (MET) : 4.450ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][3]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X98Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][3]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X98Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][3]/C clock pessimism -0.507 10.379 clock uncertainty -0.093 10.286 SLICE_X98Y86 FDCE (Recov_fdce_C_CLR) -0.361 9.925 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][3] ------------------------------------------------------------------- required time 9.925 arrival time -5.475 ------------------------------------------------------------------- slack 4.450 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 6.335ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 6.335ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C clock pessimism -0.514 17.184 clock uncertainty -0.102 17.081 SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[1] ------------------------------------------------------------------- required time 16.558 arrival time -10.223 ------------------------------------------------------------------- slack 6.335 Slack (MET) : 6.335ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C clock pessimism -0.514 17.184 clock uncertainty -0.102 17.081 SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[2] ------------------------------------------------------------------- required time 16.558 arrival time -10.223 ------------------------------------------------------------------- slack 6.335 Slack (MET) : 6.335ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C clock pessimism -0.514 17.184 clock uncertainty -0.102 17.081 SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[5] ------------------------------------------------------------------- required time 16.558 arrival time -10.223 ------------------------------------------------------------------- slack 6.335 Slack (MET) : 6.335ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C clock pessimism -0.514 17.184 clock uncertainty -0.102 17.081 SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[6] ------------------------------------------------------------------- required time 16.558 arrival time -10.223 ------------------------------------------------------------------- slack 6.335 Slack (MET) : 6.478ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.242ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C clock pessimism -0.514 17.185 clock uncertainty -0.102 17.082 SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[0] ------------------------------------------------------------------- required time 16.559 arrival time -10.081 ------------------------------------------------------------------- slack 6.478 Slack (MET) : 6.478ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.242ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C clock pessimism -0.514 17.185 clock uncertainty -0.102 17.082 SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[3] ------------------------------------------------------------------- required time 16.559 arrival time -10.081 ------------------------------------------------------------------- slack 6.478 Slack (MET) : 6.478ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.242ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C clock pessimism -0.514 17.185 clock uncertainty -0.102 17.082 SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[4] ------------------------------------------------------------------- required time 16.559 arrival time -10.081 ------------------------------------------------------------------- slack 6.478 Slack (MET) : 6.478ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.242ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C clock pessimism -0.514 17.185 clock uncertainty -0.102 17.082 SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[7] ------------------------------------------------------------------- required time 16.559 arrival time -10.081 ------------------------------------------------------------------- slack 6.478 Slack (MET) : 6.900ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.246ns (logic 0.668ns (5.455%) route 11.578ns (94.545%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 17.719 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 8.466 9.673 u_confreg/u_digitaltube_controller/p_0_in SLICE_X63Y141 FDCE f u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.547 17.719 u_confreg/u_digitaltube_controller/sys_clk SLICE_X63Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C clock pessimism -0.435 17.284 clock uncertainty -0.102 17.182 SLICE_X63Y141 FDCE (Recov_fdce_C_CLR) -0.609 16.573 u_confreg/u_digitaltube_controller/dpy0_reg_reg[0] ------------------------------------------------------------------- required time 16.573 arrival time -9.673 ------------------------------------------------------------------- slack 6.900 Slack (MET) : 6.930ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.290ns (logic 0.668ns (5.435%) route 11.622ns (94.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.155ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 8.509 9.716 u_confreg/u_int_ctrl/p_0_in SLICE_X70Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.534 17.706 u_confreg/u_int_ctrl/sys_clk SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C clock pessimism -0.435 17.271 clock uncertainty -0.102 17.169 SLICE_X70Y133 FDCE (Recov_fdce_C_CLR) -0.523 16.646 u_confreg/u_int_ctrl/int_in_sync_d1_reg[1] ------------------------------------------------------------------- required time 16.646 arrival time -9.716 ------------------------------------------------------------------- slack 6.930 Slack (MET) : 6.930ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d2_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.290ns (logic 0.668ns (5.435%) route 11.622ns (94.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.155ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 8.509 9.716 u_confreg/u_int_ctrl/p_0_in SLICE_X70Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d2_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.534 17.706 u_confreg/u_int_ctrl/sys_clk SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[1]/C clock pessimism -0.435 17.271 clock uncertainty -0.102 17.169 SLICE_X70Y133 FDCE (Recov_fdce_C_CLR) -0.523 16.646 u_confreg/u_int_ctrl/int_in_sync_d2_reg[1] ------------------------------------------------------------------- required time 16.646 arrival time -9.716 ------------------------------------------------------------------- slack 6.930 Slack (MET) : 7.490ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.649ns (logic 0.668ns (5.734%) route 10.981ns (94.266%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.288ns = ( 17.712 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.868 9.076 u_confreg/u_int_ctrl/p_0_in SLICE_X65Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.540 17.712 u_confreg/u_int_ctrl/sys_clk SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C clock pessimism -0.435 17.277 clock uncertainty -0.102 17.175 SLICE_X65Y133 FDCE (Recov_fdce_C_CLR) -0.609 16.566 u_confreg/u_int_ctrl/int_in_sync_d1_reg[2] ------------------------------------------------------------------- required time 16.566 arrival time -9.076 ------------------------------------------------------------------- slack 7.490 Slack (MET) : 7.490ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d2_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.649ns (logic 0.668ns (5.734%) route 10.981ns (94.266%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.288ns = ( 17.712 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.868 9.076 u_confreg/u_int_ctrl/p_0_in SLICE_X65Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d2_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.540 17.712 u_confreg/u_int_ctrl/sys_clk SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[2]/C clock pessimism -0.435 17.277 clock uncertainty -0.102 17.175 SLICE_X65Y133 FDCE (Recov_fdce_C_CLR) -0.609 16.566 u_confreg/u_int_ctrl/int_in_sync_d2_reg[2] ------------------------------------------------------------------- required time 16.566 arrival time -9.076 ------------------------------------------------------------------- slack 7.490 Slack (MET) : 7.742ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[23]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.496ns (logic 0.668ns (5.811%) route 10.828ns (94.189%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.715 8.922 u_confreg/u_int_ctrl/p_0_in SLICE_X46Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.552 17.724 u_confreg/u_int_ctrl/sys_clk SLICE_X46Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[23]/C clock pessimism -0.435 17.289 clock uncertainty -0.102 17.187 SLICE_X46Y140 FDCE (Recov_fdce_C_CLR) -0.523 16.664 u_confreg/u_int_ctrl/edge_int_state_reg[23] ------------------------------------------------------------------- required time 16.664 arrival time -8.922 ------------------------------------------------------------------- slack 7.742 Slack (MET) : 7.801ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[21]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.350ns (logic 0.668ns (5.885%) route 10.682ns (94.115%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.569 8.777 u_confreg/u_int_ctrl/p_0_in SLICE_X47Y139 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.552 17.724 u_confreg/u_int_ctrl/sys_clk SLICE_X47Y139 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[21]/C clock pessimism -0.435 17.289 clock uncertainty -0.102 17.187 SLICE_X47Y139 FDCE (Recov_fdce_C_CLR) -0.609 16.578 u_confreg/u_int_ctrl/edge_int_state_reg[21] ------------------------------------------------------------------- required time 16.578 arrival time -8.777 ------------------------------------------------------------------- slack 7.801 Slack (MET) : 7.821ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[29]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.414ns (logic 0.668ns (5.852%) route 10.746ns (94.148%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.139ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 17.722 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.634 8.841 u_confreg/u_int_ctrl/p_0_in SLICE_X56Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 17.722 u_confreg/u_int_ctrl/sys_clk SLICE_X56Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[29]/C clock pessimism -0.435 17.287 clock uncertainty -0.102 17.185 SLICE_X56Y140 FDCE (Recov_fdce_C_CLR) -0.523 16.662 u_confreg/u_int_ctrl/edge_int_state_reg[29] ------------------------------------------------------------------- required time 16.662 arrival time -8.841 ------------------------------------------------------------------- slack 7.821 Slack (MET) : 7.851ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[30]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.298ns (logic 0.668ns (5.912%) route 10.630ns (94.088%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.139ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 17.722 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.517 8.725 u_confreg/u_int_ctrl/p_0_in SLICE_X55Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 17.722 u_confreg/u_int_ctrl/sys_clk SLICE_X55Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[30]/C clock pessimism -0.435 17.287 clock uncertainty -0.102 17.185 SLICE_X55Y140 FDCE (Recov_fdce_C_CLR) -0.609 16.576 u_confreg/u_int_ctrl/edge_int_state_reg[30] ------------------------------------------------------------------- required time 16.576 arrival time -8.725 ------------------------------------------------------------------- slack 7.851 Slack (MET) : 7.963ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[20]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.189ns (logic 0.668ns (5.970%) route 10.521ns (94.030%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.408 8.616 u_confreg/u_int_ctrl/p_0_in SLICE_X49Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.552 17.724 u_confreg/u_int_ctrl/sys_clk SLICE_X49Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[20]/C clock pessimism -0.435 17.289 clock uncertainty -0.102 17.187 SLICE_X49Y140 FDCE (Recov_fdce_C_CLR) -0.609 16.578 u_confreg/u_int_ctrl/edge_int_state_reg[20] ------------------------------------------------------------------- required time 16.578 arrival time -8.616 ------------------------------------------------------------------- slack 7.963 Slack (MET) : 8.025ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.122ns (logic 0.668ns (6.006%) route 10.454ns (93.994%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.342 8.549 u_confreg/u_int_ctrl/p_0_in SLICE_X58Y137 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk SLICE_X58Y137 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[5]/C clock pessimism -0.435 17.285 clock uncertainty -0.102 17.183 SLICE_X58Y137 FDCE (Recov_fdce_C_CLR) -0.609 16.574 u_confreg/u_int_ctrl/edge_int_state_reg[5] ------------------------------------------------------------------- required time 16.574 arrival time -8.549 ------------------------------------------------------------------- slack 8.025 Slack (MET) : 8.025ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.122ns (logic 0.668ns (6.006%) route 10.454ns (93.994%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.342 8.549 u_confreg/u_int_ctrl/p_0_in SLICE_X58Y137 FDCE f u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk SLICE_X58Y137 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/C clock pessimism -0.435 17.285 clock uncertainty -0.102 17.183 SLICE_X58Y137 FDCE (Recov_fdce_C_CLR) -0.609 16.574 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5] ------------------------------------------------------------------- required time 16.574 arrival time -8.549 ------------------------------------------------------------------- slack 8.025 Slack (MET) : 8.046ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[31]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.103ns (logic 0.668ns (6.016%) route 10.435ns (93.984%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 17.721 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.322 8.529 u_confreg/u_int_ctrl/p_0_in SLICE_X57Y138 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[31]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 17.721 u_confreg/u_int_ctrl/sys_clk SLICE_X57Y138 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[31]/C clock pessimism -0.435 17.286 clock uncertainty -0.102 17.184 SLICE_X57Y138 FDCE (Recov_fdce_C_CLR) -0.609 16.575 u_confreg/u_int_ctrl/edge_int_state_reg[31] ------------------------------------------------------------------- required time 16.575 arrival time -8.529 ------------------------------------------------------------------- slack 8.046 Slack (MET) : 8.087ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[22]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.063ns (logic 0.668ns (6.038%) route 10.395ns (93.962%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 17.723 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.282 8.490 u_confreg/u_int_ctrl/p_0_in SLICE_X50Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[22]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.551 17.723 u_confreg/u_int_ctrl/sys_clk SLICE_X50Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[22]/C clock pessimism -0.435 17.288 clock uncertainty -0.102 17.186 SLICE_X50Y140 FDCE (Recov_fdce_C_CLR) -0.609 16.577 u_confreg/u_int_ctrl/edge_int_state_reg[22] ------------------------------------------------------------------- required time 16.577 arrival time -8.490 ------------------------------------------------------------------- slack 8.087 Slack (MET) : 8.111ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.122ns (logic 0.668ns (6.006%) route 10.454ns (93.994%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 17.719 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.341 8.548 u_confreg/u_int_ctrl/p_0_in SLICE_X60Y136 FDCE f u_confreg/u_int_ctrl/int_in_sync_d1_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.547 17.719 u_confreg/u_int_ctrl/sys_clk SLICE_X60Y136 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[5]/C clock pessimism -0.435 17.284 clock uncertainty -0.102 17.182 SLICE_X60Y136 FDCE (Recov_fdce_C_CLR) -0.523 16.659 u_confreg/u_int_ctrl/int_in_sync_d1_reg[5] ------------------------------------------------------------------- required time 16.659 arrival time -8.548 ------------------------------------------------------------------- slack 8.111 Slack (MET) : 8.111ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.122ns (logic 0.668ns (6.006%) route 10.454ns (93.994%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 17.719 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.341 8.548 u_confreg/u_int_ctrl/p_0_in SLICE_X60Y136 FDCE f u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.547 17.719 u_confreg/u_int_ctrl/sys_clk SLICE_X60Y136 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C clock pessimism -0.435 17.284 clock uncertainty -0.102 17.182 SLICE_X60Y136 FDCE (Recov_fdce_C_CLR) -0.523 16.659 u_confreg/u_int_ctrl/int_in_sync_d2_reg[5] ------------------------------------------------------------------- required time 16.659 arrival time -8.548 ------------------------------------------------------------------- slack 8.111 Slack (MET) : 8.197ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[27]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.039ns (logic 0.668ns (6.051%) route 10.371ns (93.949%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.139ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 17.722 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.258 8.465 u_confreg/u_int_ctrl/p_0_in SLICE_X46Y137 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 17.722 u_confreg/u_int_ctrl/sys_clk SLICE_X46Y137 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[27]/C clock pessimism -0.435 17.287 clock uncertainty -0.102 17.185 SLICE_X46Y137 FDCE (Recov_fdce_C_CLR) -0.523 16.662 u_confreg/u_int_ctrl/edge_int_state_reg[27] ------------------------------------------------------------------- required time 16.662 arrival time -8.465 ------------------------------------------------------------------- slack 8.197 Slack (MET) : 8.207ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[28]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.943ns (logic 0.668ns (6.104%) route 10.275ns (93.896%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 17.723 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.163 8.370 u_confreg/u_int_ctrl/p_0_in SLICE_X53Y139 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.551 17.723 u_confreg/u_int_ctrl/sys_clk SLICE_X53Y139 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[28]/C clock pessimism -0.435 17.288 clock uncertainty -0.102 17.186 SLICE_X53Y139 FDCE (Recov_fdce_C_CLR) -0.609 16.577 u_confreg/u_int_ctrl/edge_int_state_reg[28] ------------------------------------------------------------------- required time 16.577 arrival time -8.370 ------------------------------------------------------------------- slack 8.207 Slack (MET) : 8.214ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[15]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.024ns (logic 0.668ns (6.060%) route 10.356ns (93.940%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.243 8.450 u_confreg/u_int_ctrl/p_0_in SLICE_X48Y139 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.552 17.724 u_confreg/u_int_ctrl/sys_clk SLICE_X48Y139 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[15]/C clock pessimism -0.435 17.289 clock uncertainty -0.102 17.187 SLICE_X48Y139 FDCE (Recov_fdce_C_CLR) -0.523 16.664 u_confreg/u_int_ctrl/edge_int_state_reg[15] ------------------------------------------------------------------- required time 16.664 arrival time -8.450 ------------------------------------------------------------------- slack 8.214 Slack (MET) : 8.244ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.947ns (logic 0.668ns (6.102%) route 10.279ns (93.898%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.166 8.374 u_confreg/u_int_ctrl/p_0_in SLICE_X56Y137 FDCE f u_confreg/u_int_ctrl/int_in_sync_d1_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk SLICE_X56Y137 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[4]/C clock pessimism -0.435 17.285 clock uncertainty -0.102 17.183 SLICE_X56Y137 FDCE (Recov_fdce_C_CLR) -0.565 16.618 u_confreg/u_int_ctrl/int_in_sync_d1_reg[4] ------------------------------------------------------------------- required time 16.618 arrival time -8.374 ------------------------------------------------------------------- slack 8.244 Slack (MET) : 8.256ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.851ns (logic 0.668ns (6.156%) route 10.183ns (93.844%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns = ( 17.708 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.070 8.278 u_Axi_CDC/bFifo/popToPushGray_buffercc/p_0_in_1 SLICE_X94Y122 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.536 17.708 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.507 17.201 clock uncertainty -0.102 17.099 SLICE_X94Y122 FDCE (Recov_fdce_C_CLR) -0.565 16.534 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 16.534 arrival time -8.278 ------------------------------------------------------------------- slack 8.256 Slack (MET) : 8.256ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.851ns (logic 0.668ns (6.156%) route 10.183ns (93.844%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns = ( 17.708 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.070 8.278 u_Axi_CDC/bFifo/popToPushGray_buffercc/p_0_in_1 SLICE_X94Y122 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.536 17.708 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.507 17.201 clock uncertainty -0.102 17.099 SLICE_X94Y122 FDCE (Recov_fdce_C_CLR) -0.565 16.534 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 16.534 arrival time -8.278 ------------------------------------------------------------------- slack 8.256 Slack (MET) : 8.256ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.851ns (logic 0.668ns (6.156%) route 10.183ns (93.844%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns = ( 17.708 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.070 8.278 u_Axi_CDC/bFifo/popToPushGray_buffercc/p_0_in_1 SLICE_X94Y122 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.536 17.708 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.507 17.201 clock uncertainty -0.102 17.099 SLICE_X94Y122 FDCE (Recov_fdce_C_CLR) -0.565 16.534 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 16.534 arrival time -8.278 ------------------------------------------------------------------- slack 8.256 Slack (MET) : 8.257ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[24]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.893ns (logic 0.668ns (6.132%) route 10.225ns (93.868%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 17.723 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.112 8.320 u_confreg/u_int_ctrl/p_0_in SLICE_X51Y139 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.551 17.723 u_confreg/u_int_ctrl/sys_clk SLICE_X51Y139 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[24]/C clock pessimism -0.435 17.288 clock uncertainty -0.102 17.186 SLICE_X51Y139 FDCE (Recov_fdce_C_CLR) -0.609 16.577 u_confreg/u_int_ctrl/edge_int_state_reg[24] ------------------------------------------------------------------- required time 16.577 arrival time -8.320 ------------------------------------------------------------------- slack 8.257 Slack (MET) : 8.271ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.839ns (logic 0.668ns (6.163%) route 10.171ns (93.837%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns = ( 17.710 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.058 8.265 u_Axi_CDC/bFifo/p_0_in_1 SLICE_X94Y121 FDCE f u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.538 17.710 u_Axi_CDC/bFifo/sys_clk SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.507 17.203 clock uncertainty -0.102 17.101 SLICE_X94Y121 FDCE (Recov_fdce_C_CLR) -0.565 16.536 u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 16.536 arrival time -8.265 ------------------------------------------------------------------- slack 8.271 Slack (MET) : 8.271ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushCC_pushPtr_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.839ns (logic 0.668ns (6.163%) route 10.171ns (93.837%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns = ( 17.710 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.058 8.265 u_Axi_CDC/bFifo/p_0_in_1 SLICE_X94Y121 FDCE f u_Axi_CDC/bFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.538 17.710 u_Axi_CDC/bFifo/sys_clk SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.507 17.203 clock uncertainty -0.102 17.101 SLICE_X94Y121 FDCE (Recov_fdce_C_CLR) -0.565 16.536 u_Axi_CDC/bFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 16.536 arrival time -8.265 ------------------------------------------------------------------- slack 8.271 Slack (MET) : 8.286ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.947ns (logic 0.668ns (6.102%) route 10.279ns (93.898%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.166 8.374 u_confreg/u_int_ctrl/p_0_in SLICE_X56Y137 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk SLICE_X56Y137 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[4]/C clock pessimism -0.435 17.285 clock uncertainty -0.102 17.183 SLICE_X56Y137 FDCE (Recov_fdce_C_CLR) -0.523 16.660 u_confreg/u_int_ctrl/edge_int_state_reg[4] ------------------------------------------------------------------- required time 16.660 arrival time -8.374 ------------------------------------------------------------------- slack 8.286 Slack (MET) : 8.286ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d2_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.947ns (logic 0.668ns (6.102%) route 10.279ns (93.898%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.166 8.374 u_confreg/u_int_ctrl/p_0_in SLICE_X56Y137 FDCE f u_confreg/u_int_ctrl/int_in_sync_d2_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk SLICE_X56Y137 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[4]/C clock pessimism -0.435 17.285 clock uncertainty -0.102 17.183 SLICE_X56Y137 FDCE (Recov_fdce_C_CLR) -0.523 16.660 u_confreg/u_int_ctrl/int_in_sync_d2_reg[4] ------------------------------------------------------------------- required time 16.660 arrival time -8.374 ------------------------------------------------------------------- slack 8.286 Slack (MET) : 8.286ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.947ns (logic 0.668ns (6.102%) route 10.279ns (93.898%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.166 8.374 u_confreg/u_int_ctrl/p_0_in SLICE_X56Y137 FDCE f u_confreg/u_int_ctrl/int_in_sync_d3_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk SLICE_X56Y137 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[4]/C clock pessimism -0.435 17.285 clock uncertainty -0.102 17.183 SLICE_X56Y137 FDCE (Recov_fdce_C_CLR) -0.523 16.660 u_confreg/u_int_ctrl/int_in_sync_d3_reg[4] ------------------------------------------------------------------- required time 16.660 arrival time -8.374 ------------------------------------------------------------------- slack 8.286 Slack (MET) : 8.298ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.851ns (logic 0.668ns (6.156%) route 10.183ns (93.844%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns = ( 17.708 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.070 8.278 u_Axi_CDC/bFifo/popToPushGray_buffercc/p_0_in_1 SLICE_X94Y122 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.536 17.708 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.507 17.201 clock uncertainty -0.102 17.099 SLICE_X94Y122 FDCE (Recov_fdce_C_CLR) -0.523 16.576 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 16.576 arrival time -8.278 ------------------------------------------------------------------- slack 8.298 Slack (MET) : 8.298ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.851ns (logic 0.668ns (6.156%) route 10.183ns (93.844%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns = ( 17.708 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.070 8.278 u_Axi_CDC/bFifo/popToPushGray_buffercc/p_0_in_1 SLICE_X94Y122 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.536 17.708 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.507 17.201 clock uncertainty -0.102 17.099 SLICE_X94Y122 FDCE (Recov_fdce_C_CLR) -0.523 16.576 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 16.576 arrival time -8.278 ------------------------------------------------------------------- slack 8.298 Slack (MET) : 8.298ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.851ns (logic 0.668ns (6.156%) route 10.183ns (93.844%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns = ( 17.708 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.070 8.278 u_Axi_CDC/bFifo/popToPushGray_buffercc/p_0_in_1 SLICE_X94Y122 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.536 17.708 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.507 17.201 clock uncertainty -0.102 17.099 SLICE_X94Y122 FDCE (Recov_fdce_C_CLR) -0.523 16.576 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 16.576 arrival time -8.278 ------------------------------------------------------------------- slack 8.298 Slack (MET) : 8.313ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.839ns (logic 0.668ns (6.163%) route 10.171ns (93.837%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns = ( 17.710 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.058 8.265 u_Axi_CDC/bFifo/p_0_in_1 SLICE_X94Y121 FDCE f u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.538 17.710 u_Axi_CDC/bFifo/sys_clk SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.507 17.203 clock uncertainty -0.102 17.101 SLICE_X94Y121 FDCE (Recov_fdce_C_CLR) -0.523 16.578 u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 16.578 arrival time -8.265 ------------------------------------------------------------------- slack 8.313 Slack (MET) : 8.313ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.839ns (logic 0.668ns (6.163%) route 10.171ns (93.837%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns = ( 17.710 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.058 8.265 u_Axi_CDC/bFifo/p_0_in_1 SLICE_X94Y121 FDCE f u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.538 17.710 u_Axi_CDC/bFifo/sys_clk SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.507 17.203 clock uncertainty -0.102 17.101 SLICE_X94Y121 FDCE (Recov_fdce_C_CLR) -0.523 16.578 u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 16.578 arrival time -8.265 ------------------------------------------------------------------- slack 8.313 Slack (MET) : 8.313ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushCC_pushPtr_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.839ns (logic 0.668ns (6.163%) route 10.171ns (93.837%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns = ( 17.710 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.058 8.265 u_Axi_CDC/bFifo/p_0_in_1 SLICE_X94Y121 FDCE f u_Axi_CDC/bFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.538 17.710 u_Axi_CDC/bFifo/sys_clk SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.507 17.203 clock uncertainty -0.102 17.101 SLICE_X94Y121 FDCE (Recov_fdce_C_CLR) -0.523 16.578 u_Axi_CDC/bFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 16.578 arrival time -8.265 ------------------------------------------------------------------- slack 8.313 Slack (MET) : 8.408ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.716ns (logic 0.668ns (6.234%) route 10.048ns (93.766%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.209ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.935 8.142 u_fft_mlkem_axi_slave/p_0_in SLICE_X96Y110 FDCE f u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.552 17.724 u_fft_mlkem_axi_slave/sys_clk SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C clock pessimism -0.507 17.217 clock uncertainty -0.102 17.115 SLICE_X96Y110 FDCE (Recov_fdce_C_CLR) -0.565 16.550 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1] ------------------------------------------------------------------- required time 16.550 arrival time -8.142 ------------------------------------------------------------------- slack 8.408 Slack (MET) : 8.448ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[25]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.788ns (logic 0.668ns (6.192%) route 10.120ns (93.808%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.139ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 17.722 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.007 8.214 u_confreg/u_int_ctrl/p_0_in SLICE_X52Y138 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 17.722 u_confreg/u_int_ctrl/sys_clk SLICE_X52Y138 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[25]/C clock pessimism -0.435 17.287 clock uncertainty -0.102 17.185 SLICE_X52Y138 FDCE (Recov_fdce_C_CLR) -0.523 16.662 u_confreg/u_int_ctrl/edge_int_state_reg[25] ------------------------------------------------------------------- required time 16.662 arrival time -8.214 ------------------------------------------------------------------- slack 8.448 Slack (MET) : 8.450ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.716ns (logic 0.668ns (6.234%) route 10.048ns (93.766%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.209ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.935 8.142 u_fft_mlkem_axi_slave/p_0_in SLICE_X96Y110 FDCE f u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.552 17.724 u_fft_mlkem_axi_slave/sys_clk SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C clock pessimism -0.507 17.217 clock uncertainty -0.102 17.115 SLICE_X96Y110 FDCE (Recov_fdce_C_CLR) -0.523 16.592 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0] ------------------------------------------------------------------- required time 16.592 arrival time -8.142 ------------------------------------------------------------------- slack 8.450 Slack (MET) : 8.457ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[26]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.692ns (logic 0.668ns (6.247%) route 10.024ns (93.753%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.139ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 17.722 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.912 8.119 u_confreg/u_int_ctrl/p_0_in SLICE_X49Y137 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 17.722 u_confreg/u_int_ctrl/sys_clk SLICE_X49Y137 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[26]/C clock pessimism -0.435 17.287 clock uncertainty -0.102 17.185 SLICE_X49Y137 FDCE (Recov_fdce_C_CLR) -0.609 16.576 u_confreg/u_int_ctrl/edge_int_state_reg[26] ------------------------------------------------------------------- required time 16.576 arrival time -8.119 ------------------------------------------------------------------- slack 8.457 Slack (MET) : 8.490ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.655ns (logic 0.668ns (6.269%) route 9.987ns (93.731%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.282ns = ( 17.718 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.875 8.082 u_confreg/u_int_ctrl/p_0_in SLICE_X58Y134 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.546 17.718 u_confreg/u_int_ctrl/sys_clk SLICE_X58Y134 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[1]/C clock pessimism -0.435 17.283 clock uncertainty -0.102 17.181 SLICE_X58Y134 FDCE (Recov_fdce_C_CLR) -0.609 16.572 u_confreg/u_int_ctrl/edge_int_state_reg[1] ------------------------------------------------------------------- required time 16.572 arrival time -8.082 ------------------------------------------------------------------- slack 8.490 Slack (MET) : 8.490ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.655ns (logic 0.668ns (6.269%) route 9.987ns (93.731%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.282ns = ( 17.718 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.875 8.082 u_confreg/u_int_ctrl/p_0_in SLICE_X58Y134 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.546 17.718 u_confreg/u_int_ctrl/sys_clk SLICE_X58Y134 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[2]/C clock pessimism -0.435 17.283 clock uncertainty -0.102 17.181 SLICE_X58Y134 FDCE (Recov_fdce_C_CLR) -0.609 16.572 u_confreg/u_int_ctrl/edge_int_state_reg[2] ------------------------------------------------------------------- required time 16.572 arrival time -8.082 ------------------------------------------------------------------- slack 8.490 Slack (MET) : 8.490ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.655ns (logic 0.668ns (6.269%) route 9.987ns (93.731%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.282ns = ( 17.718 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.875 8.082 u_confreg/u_int_ctrl/p_0_in SLICE_X58Y134 FDCE f u_confreg/u_int_ctrl/int_in_sync_d3_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.546 17.718 u_confreg/u_int_ctrl/sys_clk SLICE_X58Y134 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[1]/C clock pessimism -0.435 17.283 clock uncertainty -0.102 17.181 SLICE_X58Y134 FDCE (Recov_fdce_C_CLR) -0.609 16.572 u_confreg/u_int_ctrl/int_in_sync_d3_reg[1] ------------------------------------------------------------------- required time 16.572 arrival time -8.082 ------------------------------------------------------------------- slack 8.490 -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: cpu_clk Max Delay 59 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_cpu/delay_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.617 7.824 pll_clk.u_rst_cpu/p_0_in_0 SLICE_X92Y115 FDCE f pll_clk.u_rst_cpu/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.544 -2.284 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[0]/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_cpu/delay_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.617 7.824 pll_clk.u_rst_cpu/p_0_in_0 SLICE_X92Y115 FDCE f pll_clk.u_rst_cpu/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.544 -2.284 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.617 7.824 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 SLICE_X92Y115 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.544 -2.284 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.617 7.824 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 SLICE_X92Y115 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.544 -2.284 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.208ns (logic 1.344ns (25.806%) route 3.864ns (74.194%)) Logic Levels: 0 Clock Path Skew: 0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns Source Clock Delay (SCD): -2.397ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.053 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 3.864 2.811 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.118ns (logic 1.336ns (26.105%) route 3.782ns (73.895%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.062 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 3.782 2.720 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.096ns (logic 1.317ns (25.844%) route 3.779ns (74.156%)) Logic Levels: 0 Clock Path Skew: 0.104ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.397ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.080 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 3.779 2.699 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.064ns (logic 1.314ns (25.947%) route 3.750ns (74.053%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.084 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O net (fo=1, routed) 3.750 2.667 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.040ns (logic 1.309ns (25.973%) route 3.731ns (74.027%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.089 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 3.731 2.642 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.035ns (logic 1.314ns (26.100%) route 3.721ns (73.900%)) Logic Levels: 0 Clock Path Skew: 0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns Source Clock Delay (SCD): -2.397ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.083 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 3.721 2.638 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.971ns (logic 1.344ns (27.035%) route 3.627ns (72.965%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.054 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 3.627 2.574 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.947ns (logic 1.344ns (27.169%) route 3.603ns (72.831%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.054 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 3.603 2.549 u_Axi_CDC/rFifo/_zz_ram_port10__2[24] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.937ns (logic 1.317ns (26.677%) route 3.620ns (73.323%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.081 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 3.620 2.539 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.925ns (logic 1.309ns (26.579%) route 3.616ns (73.421%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.089 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 3.616 2.527 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.852ns (logic 1.317ns (27.146%) route 3.535ns (72.854%)) Logic Levels: 0 Clock Path Skew: 0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.081 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 3.535 2.454 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] SLICE_X93Y111 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y111 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.709ns (logic 1.336ns (28.372%) route 3.373ns (71.628%)) Logic Levels: 0 Clock Path Skew: 0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.412ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.076 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 3.373 2.297 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.686ns (logic 1.314ns (28.042%) route 3.372ns (71.958%)) Logic Levels: 0 Clock Path Skew: 0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.412ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.098 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 3.372 2.274 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.616ns (logic 1.336ns (28.941%) route 3.280ns (71.059%)) Logic Levels: 0 Clock Path Skew: 0.104ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.397ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.061 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 3.280 2.220 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.560ns (logic 1.343ns (29.450%) route 3.217ns (70.550%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.055 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 3.217 2.163 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.469ns (logic 1.309ns (29.293%) route 3.160ns (70.707%)) Logic Levels: 0 Clock Path Skew: 0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns Source Clock Delay (SCD): -2.397ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.088 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 3.160 2.072 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.451ns (logic 1.344ns (30.195%) route 3.107ns (69.805%)) Logic Levels: 0 Clock Path Skew: 0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.412ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.068 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 3.107 2.040 u_Axi_CDC/rFifo/_zz_ram_port10__2[18] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.433ns (logic 1.343ns (30.296%) route 3.090ns (69.704%)) Logic Levels: 0 Clock Path Skew: 0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns Source Clock Delay (SCD): -2.397ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.054 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 3.090 2.036 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.432ns (logic 1.309ns (29.538%) route 3.123ns (70.462%)) Logic Levels: 0 Clock Path Skew: 0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.412ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.103 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 3.123 2.020 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.415ns (logic 1.309ns (29.648%) route 3.106ns (70.352%)) Logic Levels: 0 Clock Path Skew: 0.120ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns Source Clock Delay (SCD): -2.412ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.103 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 3.106 2.004 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.328ns (logic 1.336ns (30.870%) route 2.992ns (69.130%)) Logic Levels: 0 Clock Path Skew: 0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.412ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.076 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 2.992 1.916 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.304ns (logic 1.344ns (31.229%) route 2.960ns (68.771%)) Logic Levels: 0 Clock Path Skew: 0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.412ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.068 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 2.960 1.892 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.300ns (logic 1.317ns (30.629%) route 2.983ns (69.371%)) Logic Levels: 0 Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.289ns Source Clock Delay (SCD): -2.412ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.095 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 2.983 1.888 u_Axi_CDC/rFifo/_zz_ram_port10__2[21] SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.539 -2.289 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.288ns (logic 1.317ns (30.712%) route 2.971ns (69.288%)) Logic Levels: 0 Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.289ns Source Clock Delay (SCD): -2.412ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.095 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O net (fo=1, routed) 2.971 1.877 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.539 -2.289 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.352ns (logic 1.343ns (30.862%) route 3.009ns (69.138%)) Logic Levels: 0 Clock Path Skew: 0.202ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.495ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.847 -2.495 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y95 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.152 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 3.009 1.857 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.253ns (logic 1.336ns (31.411%) route 2.917ns (68.589%)) Logic Levels: 0 Clock Path Skew: 0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.289ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.062 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 2.917 1.856 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.539 -2.289 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.251ns (logic 1.314ns (30.911%) route 2.937ns (69.089%)) Logic Levels: 0 Clock Path Skew: 0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.084 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 2.937 1.853 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.252ns (logic 1.343ns (31.587%) route 2.909ns (68.413%)) Logic Levels: 0 Clock Path Skew: 0.122ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns Source Clock Delay (SCD): -2.412ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.069 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 2.909 1.840 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.172ns (logic 1.343ns (32.194%) route 2.829ns (67.806%)) Logic Levels: 0 Clock Path Skew: 0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.412ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.069 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 2.829 1.760 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 2.079ns (logic 0.612ns (29.443%) route 1.467ns (70.557%)) Logic Levels: 0 Clock Path Skew: -0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.691ns Source Clock Delay (SCD): -0.380ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.928 -0.380 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y95 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.232 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 1.467 1.698 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.572 -0.691 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_matmul_axi_slave/done_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 2.040ns (logic 0.175ns (8.577%) route 1.865ns (91.423%)) Logic Levels: 0 Clock Path Skew: -0.304ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.682ns Source Clock Delay (SCD): -0.378ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.930 -0.378 u_matmul_axi_slave/sys_clk SLICE_X45Y98 FDRE r u_matmul_axi_slave/done_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y98 FDRE (Prop_fdre_C_Q) 0.175 -0.203 r u_matmul_axi_slave/done_reg/Q net (fo=10, routed) 1.865 1.662 u_cpu/u_csr/interrupt[2] SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.581 -0.682 u_cpu/u_csr/cpu_clk SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.978ns (logic 0.595ns (30.082%) route 1.383ns (69.918%)) Logic Levels: 0 Clock Path Skew: -0.315ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.695ns Source Clock Delay (SCD): -0.380ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.928 -0.380 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y95 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.215 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 1.383 1.598 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.568 -0.695 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 3.967ns (logic 1.343ns (33.856%) route 2.624ns (66.144%)) Logic Levels: 0 Clock Path Skew: 0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.055 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 2.624 1.569 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.776ns (logic 0.480ns (27.033%) route 1.296ns (72.967%)) Logic Levels: 0 Clock Path Skew: -0.341ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.690ns Source Clock Delay (SCD): -0.349ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.959 -0.349 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.131 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 1.296 1.426 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.573 -0.690 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.724ns (logic 0.482ns (27.964%) route 1.242ns (72.036%)) Logic Levels: 0 Clock Path Skew: -0.306ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.691ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X62Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y92 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.097 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O net (fo=1, routed) 1.242 1.338 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.572 -0.691 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.886ns (logic 0.184ns (20.776%) route 0.702ns (79.224%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.682ns Source Clock Delay (SCD): -0.456ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.852 -0.456 u_fft_mlkem_axi_slave/sys_clk SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y110 FDCE (Prop_fdce_C_Q) 0.184 -0.272 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/Q net (fo=1, routed) 0.702 0.429 u_cpu/u_csr/interrupt[3] SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.581 -0.682 u_cpu/u_csr/cpu_clk SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[5]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.644ns (logic 0.204ns (31.675%) route 0.440ns (68.325%)) Logic Levels: 0 Clock Path Skew: -0.295ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.679ns Source Clock Delay (SCD): -0.384ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.924 -0.384 u_Axi_CDC/rFifo/sys_clk SLICE_X62Y94 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y94 FDCE (Prop_fdce_C_Q) 0.204 -0.180 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.440 0.260 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0] SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.584 -0.679 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_cdma_matmul_bridge/seq_done_flag_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.671ns (logic 0.231ns (34.431%) route 0.440ns (65.569%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.694ns Source Clock Delay (SCD): -0.463ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.845 -0.463 u_cdma_matmul_bridge/sys_clk SLICE_X71Y113 FDRE r u_cdma_matmul_bridge/seq_done_flag_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y113 FDRE (Prop_fdre_C_Q) 0.175 -0.288 r u_cdma_matmul_bridge/seq_done_flag_reg/Q net (fo=3, routed) 0.440 0.152 u_snix_axil_cdma_mux_8ch/cdma_matmul_seq_irq SLICE_X75Y119 LUT5 (Prop_lut5_I4_O) 0.056 0.208 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O net (fo=1, routed) 0.000 0.208 u_cpu/u_csr/interrupt[1] SLICE_X75Y119 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.569 -0.694 u_cpu/u_csr/cpu_clk SLICE_X75Y119 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.573ns (logic 0.184ns (32.112%) route 0.389ns (67.888%)) Logic Levels: 0 Clock Path Skew: -0.295ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.679ns Source Clock Delay (SCD): -0.384ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.924 -0.384 u_Axi_CDC/rFifo/sys_clk SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.184 -0.200 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=4, routed) 0.389 0.189 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.584 -0.679 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.514ns (logic 0.204ns (39.659%) route 0.310ns (60.341%)) Logic Levels: 0 Clock Path Skew: -0.295ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.679ns Source Clock Delay (SCD): -0.384ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.924 -0.384 u_Axi_CDC/rFifo/sys_clk SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.204 -0.180 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.310 0.130 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1] SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.584 -0.679 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.506ns (logic 0.204ns (40.341%) route 0.302ns (59.659%)) Logic Levels: 0 Clock Path Skew: -0.295ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.679ns Source Clock Delay (SCD): -0.384ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.924 -0.384 u_Axi_CDC/rFifo/sys_clk SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.204 -0.180 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=2, routed) 0.302 0.122 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2] SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.584 -0.679 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.514ns (logic 0.175ns (34.048%) route 0.339ns (65.952%)) Logic Levels: 0 Clock Path Skew: -0.297ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.695ns Source Clock Delay (SCD): -0.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.910 -0.398 u_Axi_CDC/arFifo/sys_clk SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.175 -0.223 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.339 0.116 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.568 -0.695 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_confreg/int_out_or_q2_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.557ns (logic 0.175ns (31.425%) route 0.382ns (68.575%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.694ns Source Clock Delay (SCD): -0.470ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.838 -0.470 u_confreg/sys_clk SLICE_X78Y141 FDRE r u_confreg/int_out_or_q2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X78Y141 FDRE (Prop_fdre_C_Q) 0.175 -0.295 r u_confreg/int_out_or_q2_reg/Q net (fo=1, routed) 0.382 0.087 u_cpu/u_csr/interrupt[0] SLICE_X84Y149 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.569 -0.694 u_cpu/u_csr/cpu_clk SLICE_X84Y149 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.475ns (logic 0.175ns (36.825%) route 0.300ns (63.175%)) Logic Levels: 0 Clock Path Skew: -0.297ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.695ns Source Clock Delay (SCD): -0.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.910 -0.398 u_Axi_CDC/arFifo/sys_clk SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.175 -0.223 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.300 0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.568 -0.695 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.465ns (logic 0.160ns (34.376%) route 0.305ns (65.624%)) Logic Levels: 0 Clock Path Skew: -0.297ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.695ns Source Clock Delay (SCD): -0.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.910 -0.398 u_Axi_CDC/arFifo/sys_clk SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.160 -0.238 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.305 0.067 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.568 -0.695 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.505ns (logic 0.184ns (36.469%) route 0.321ns (63.531%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.691ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.840 -0.468 u_Axi_CDC/bFifo/sys_clk SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y121 FDCE (Prop_fdce_C_Q) 0.184 -0.284 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.321 0.036 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.572 -0.691 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: mlkem_clk Max Delay 112 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 10.980ns (logic 0.668ns (6.084%) route 10.312ns (93.916%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.301ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.273ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.199 8.406 pll_clk.u_rst_mlkem/p_0_in SLICE_X96Y101 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.555 -2.273 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X96Y101 FDCE r pll_clk.u_rst_mlkem/delay_reg[0]/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 10.561ns (logic 0.668ns (6.325%) route 9.893ns (93.675%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.297ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.780 7.987 pll_clk.u_rst_mlkem/p_0_in SLICE_X92Y102 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.551 -2.277 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 6.643ns (logic 0.668ns (10.055%) route 5.975ns (89.945%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.294ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 2.863 4.070 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.548 -2.280 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 6.643ns (logic 0.668ns (10.055%) route 5.975ns (89.945%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.294ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 2.863 4.070 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.548 -2.280 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.143ns (logic 0.612ns (53.534%) route 0.531ns (46.466%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/O net (fo=1, routed) 0.531 0.756 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[36] SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.059ns (logic 0.612ns (57.810%) route 0.447ns (42.190%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X44Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.447 0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24] SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.002ns (logic 0.595ns (59.409%) route 0.407ns (40.591%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.208 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 0.407 0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[7] SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.994ns (logic 0.612ns (61.564%) route 0.382ns (38.436%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.617ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y97 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/O net (fo=1, routed) 0.382 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[48] SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.982ns (logic 0.612ns (62.344%) route 0.370ns (37.656%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.384ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 0.370 0.597 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[0] SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.966ns (logic 0.612ns (63.335%) route 0.354ns (36.665%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.611ns Source Clock Delay (SCD): -0.380ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/WCLK SLICE_X56Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.232 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/O net (fo=1, routed) 0.354 0.586 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[36] SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.963ns (logic 0.491ns (50.975%) route 0.472ns (49.025%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.384ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.107 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/O net (fo=1, routed) 0.472 0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[2] SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.957ns (logic 0.595ns (62.185%) route 0.362ns (37.815%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.617ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/O net (fo=1, routed) 0.362 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[13] SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.957ns (logic 0.482ns (50.382%) route 0.475ns (49.618%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.617ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/O net (fo=1, routed) 0.475 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[15] SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.954ns (logic 0.482ns (50.537%) route 0.472ns (49.463%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.095 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/O net (fo=1, routed) 0.472 0.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[9] SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.940ns (logic 0.595ns (63.287%) route 0.345ns (36.713%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X44Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y80 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.345 0.551 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[1] SLICE_X42Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X42Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.935ns (logic 0.612ns (65.444%) route 0.323ns (34.556%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/O net (fo=1, routed) 0.323 0.550 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[12] SLICE_X67Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X67Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.927ns (logic 0.595ns (64.162%) route 0.332ns (35.838%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X44Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.332 0.539 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25] SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.925ns (logic 0.595ns (64.303%) route 0.330ns (35.697%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.615ns Source Clock Delay (SCD): -0.391ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X46Y79 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.204 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 0.330 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[7] SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.919ns (logic 0.595ns (64.745%) route 0.324ns (35.255%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X64Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 0.324 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[7] SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.908ns (logic 0.612ns (67.424%) route 0.296ns (32.576%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X70Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y98 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/O net (fo=1, routed) 0.296 0.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[42] SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.911ns (logic 0.612ns (67.168%) route 0.299ns (32.832%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.615ns Source Clock Delay (SCD): -0.391ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X46Y79 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 0.299 0.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[6] SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.889ns (logic 0.482ns (54.189%) route 0.407ns (45.811%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y84 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y84 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/O net (fo=1, routed) 0.407 0.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[3] SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.866ns (logic 0.595ns (68.739%) route 0.271ns (31.261%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X52Y85 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y85 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/O net (fo=1, routed) 0.271 0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[13] SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.858ns (logic 0.480ns (55.963%) route 0.378ns (44.037%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/O net (fo=1, routed) 0.378 0.471 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[11] SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.849ns (logic 0.612ns (72.044%) route 0.237ns (27.956%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X64Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/O net (fo=1, routed) 0.237 0.464 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[6] SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.850ns (logic 0.612ns (72.015%) route 0.238ns (27.985%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/O net (fo=1, routed) 0.238 0.463 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[6] SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.849ns (logic 0.480ns (56.510%) route 0.369ns (43.490%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X44Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y80 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 0.369 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[5] SLICE_X42Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X42Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.847ns (logic 0.612ns (72.292%) route 0.235ns (27.708%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X44Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y80 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 0.235 0.457 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[0] SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.831ns (logic 0.595ns (71.594%) route 0.236ns (28.406%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y84 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y84 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/O net (fo=1, routed) 0.236 0.445 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[1] SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.826ns (logic 0.595ns (72.067%) route 0.231ns (27.933%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.208 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/O net (fo=1, routed) 0.231 0.438 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[37] SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.823ns (logic 0.485ns (58.931%) route 0.338ns (41.069%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X44Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y80 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 0.338 0.434 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[4] SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.816ns (logic 0.485ns (59.415%) route 0.331ns (40.585%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y84 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y84 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/O net (fo=1, routed) 0.331 0.430 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[4] SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.815ns (logic 0.612ns (75.104%) route 0.203ns (24.896%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.612ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X52Y85 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y85 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA/O net (fo=1, routed) 0.203 0.430 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[12] SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.818ns (logic 0.485ns (59.283%) route 0.333ns (40.717%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.333 0.429 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[22] SLICE_X49Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.803ns (logic 0.612ns (76.218%) route 0.191ns (23.782%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/WCLK SLICE_X46Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y82 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/O net (fo=1, routed) 0.191 0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[36] SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.794ns (logic 0.595ns (74.965%) route 0.199ns (25.035%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.611ns Source Clock Delay (SCD): -0.381ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK SLICE_X56Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y91 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/O net (fo=1, routed) 0.199 0.413 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[49] SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.800ns (logic 0.595ns (74.332%) route 0.205ns (25.668%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.615ns Source Clock Delay (SCD): -0.390ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X46Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y80 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.205 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.205 0.410 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[13] SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.794ns (logic 0.491ns (61.813%) route 0.303ns (38.187%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.106 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O net (fo=1, routed) 0.303 0.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14] SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.791ns (logic 0.595ns (75.204%) route 0.196ns (24.796%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.615ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y97 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/O net (fo=1, routed) 0.196 0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[49] SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.789ns (logic 0.482ns (61.059%) route 0.307ns (38.941%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.611ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X52Y85 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y85 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/O net (fo=1, routed) 0.307 0.404 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[15] SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.783ns (logic 0.595ns (75.959%) route 0.188ns (24.041%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.384ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.211 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/O net (fo=1, routed) 0.188 0.399 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[1] SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.785ns (logic 0.595ns (75.763%) route 0.190ns (24.237%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.190 0.397 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[31] SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.777ns (logic 0.491ns (63.166%) route 0.286ns (36.834%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.611ns Source Clock Delay (SCD): -0.381ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X56Y92 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y92 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.110 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/O net (fo=1, routed) 0.286 0.396 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[32] SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.787ns (logic 0.485ns (61.631%) route 0.302ns (38.369%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.391ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X46Y79 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 0.302 0.396 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[10] SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.781ns (logic 0.485ns (62.110%) route 0.296ns (37.890%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.390ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X46Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y80 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.095 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.296 0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[16] SLICE_X50Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X50Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.778ns (logic 0.595ns (76.434%) route 0.183ns (23.566%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.615ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.183 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[19] SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.767ns (logic 0.485ns (63.268%) route 0.282ns (36.732%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X64Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.100 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/O net (fo=1, routed) 0.282 0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[10] SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.758ns (logic 0.491ns (64.744%) route 0.267ns (35.256%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.612ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y84 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y84 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.105 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/O net (fo=1, routed) 0.267 0.372 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[2] SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.759ns (logic 0.485ns (63.921%) route 0.274ns (36.079%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.098 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/O net (fo=1, routed) 0.274 0.372 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[10] SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.751ns (logic 0.612ns (81.523%) route 0.139ns (18.477%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.611ns Source Clock Delay (SCD): -0.381ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK SLICE_X56Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y91 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.231 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/O net (fo=1, routed) 0.139 0.370 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[48] SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: cpu_clk To Clock: sys_clk Max Delay 162 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.425ns (logic 0.485ns (34.039%) route 0.940ns (65.961%)) Logic Levels: 0 Clock Path Skew: -0.207ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.674ns Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X88Y114 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y114 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.018 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/O net (fo=1, routed) 0.940 0.958 u_Axi_CDC/awFifo/_zz_ram_port10[22] SLICE_X52Y101 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.589 -0.674 u_Axi_CDC/awFifo/sys_clk SLICE_X52Y101 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.308ns (logic 0.482ns (36.863%) route 0.826ns (63.137%)) Logic Levels: 0 Clock Path Skew: -0.204ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.681ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.005 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/O net (fo=1, routed) 0.826 0.830 u_Axi_CDC/arFifo/_zz_ram_port10__1[9] SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.582 -0.681 u_Axi_CDC/arFifo/sys_clk SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.238ns (logic 0.485ns (39.176%) route 0.753ns (60.824%)) Logic Levels: 0 Clock Path Skew: -0.204ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.681ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.008 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/O net (fo=1, routed) 0.753 0.761 u_Axi_CDC/arFifo/_zz_ram_port10__1[10] SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.582 -0.681 u_Axi_CDC/arFifo/sys_clk SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.212ns (logic 0.485ns (40.001%) route 0.727ns (59.999%)) Logic Levels: 0 Clock Path Skew: -0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.608ns Source Clock Delay (SCD): -0.458ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X70Y105 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y105 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.027 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/O net (fo=1, routed) 0.727 0.754 u_Axi_CDC/arFifo/_zz_ram_port10__1[22] SLICE_X47Y95 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.654 -0.608 u_Axi_CDC/arFifo/sys_clk SLICE_X47Y95 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.193ns (logic 0.612ns (51.321%) route 0.581ns (48.679%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.702ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X88Y128 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y128 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.138 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 0.581 0.718 u_Axi_CDC/wFifo/_zz_ram_port10__0[18] SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.185ns (logic 0.612ns (51.630%) route 0.573ns (48.370%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.702ns Source Clock Delay (SCD): -0.475ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.833 -0.475 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/WCLK SLICE_X90Y125 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y125 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.137 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/O net (fo=1, routed) 0.573 0.710 u_Axi_CDC/wFifo/_zz_ram_port10__0[36] SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.173ns (logic 0.612ns (52.170%) route 0.561ns (47.830%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.700ns Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X88Y114 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y114 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.145 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/O net (fo=1, routed) 0.561 0.706 u_Axi_CDC/awFifo/_zz_ram_port10[18] SLICE_X82Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.563 -0.700 u_Axi_CDC/awFifo/sys_clk SLICE_X82Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.116ns (logic 0.482ns (43.203%) route 0.634ns (56.797%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.695ns Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X88Y114 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y114 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.015 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/O net (fo=1, routed) 0.634 0.648 u_Axi_CDC/awFifo/_zz_ram_port10[21] SLICE_X81Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.568 -0.695 u_Axi_CDC/awFifo/sys_clk SLICE_X81Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.100ns (logic 0.612ns (55.644%) route 0.488ns (44.356%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.698ns Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.145 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/O net (fo=1, routed) 0.488 0.633 u_Axi_CDC/awFifo/_zz_ram_port10[6] SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.080ns (logic 0.612ns (56.690%) route 0.468ns (43.310%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.698ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.843 -0.465 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X90Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y115 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.147 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 0.468 0.614 u_Axi_CDC/awFifo/_zz_ram_port10[0] SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.075ns (logic 0.485ns (45.122%) route 0.590ns (54.878%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.702ns Source Clock Delay (SCD): -0.471ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X90Y128 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y128 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.014 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.590 0.604 u_Axi_CDC/wFifo/_zz_ram_port10__0[16] SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.070ns (logic 0.612ns (57.190%) route 0.458ns (42.810%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.696ns Source Clock Delay (SCD): -0.471ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X84Y109 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y109 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.141 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/O net (fo=1, routed) 0.458 0.599 u_Axi_CDC/arFifo/_zz_ram_port10__1[24] SLICE_X80Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.567 -0.696 u_Axi_CDC/arFifo/sys_clk SLICE_X80Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.061ns (logic 0.491ns (46.270%) route 0.570ns (53.730%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.698ns Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.024 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/O net (fo=1, routed) 0.570 0.594 u_Axi_CDC/awFifo/_zz_ram_port10[8] SLICE_X82Y111 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk SLICE_X82Y111 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.048ns (logic 0.595ns (56.753%) route 0.453ns (43.247%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.699ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.118 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 0.453 0.571 u_Axi_CDC/arFifo/_zz_ram_port10__1[7] SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.564 -0.699 u_Axi_CDC/arFifo/sys_clk SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.024ns (logic 0.612ns (59.777%) route 0.412ns (40.223%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.680ns Source Clock Delay (SCD): -0.455ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.853 -0.455 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK SLICE_X64Y106 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y106 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.157 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/O net (fo=1, routed) 0.412 0.569 u_Axi_CDC/awFifo/_zz_ram_port10[42] SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.583 -0.680 u_Axi_CDC/awFifo/sys_clk SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.025ns (logic 0.595ns (58.034%) route 0.430ns (41.966%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.703ns Source Clock Delay (SCD): -0.472ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.836 -0.472 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X88Y130 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y130 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.123 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.430 0.553 u_Axi_CDC/wFifo/_zz_ram_port10__0[1] SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.009ns (logic 0.612ns (60.640%) route 0.397ns (39.360%)) Logic Levels: 0 Clock Path Skew: -0.157ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.615ns Source Clock Delay (SCD): -0.458ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X70Y105 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y105 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.154 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/O net (fo=1, routed) 0.397 0.551 u_Axi_CDC/arFifo/_zz_ram_port10__1[18] SLICE_X66Y97 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.647 -0.615 u_Axi_CDC/arFifo/sys_clk SLICE_X66Y97 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.006ns (logic 0.491ns (48.819%) route 0.515ns (51.181%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.699ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.014 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/O net (fo=1, routed) 0.515 0.529 u_Axi_CDC/arFifo/_zz_ram_port10__1[8] SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.564 -0.699 u_Axi_CDC/arFifo/sys_clk SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.992ns (logic 0.612ns (61.686%) route 0.380ns (38.314%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.703ns Source Clock Delay (SCD): -0.472ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.836 -0.472 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X88Y130 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y130 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.140 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 0.380 0.520 u_Axi_CDC/wFifo/_zz_ram_port10__0[0] SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.990ns (logic 0.595ns (60.095%) route 0.395ns (39.905%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.705ns Source Clock Delay (SCD): -0.471ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X88Y131 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y131 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.124 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 0.395 0.519 u_Axi_CDC/wFifo/_zz_ram_port10__0[7] SLICE_X82Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk SLICE_X82Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.992ns (logic 0.480ns (48.370%) route 0.512ns (51.630%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.702ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X88Y128 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y128 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.006 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 0.512 0.518 u_Axi_CDC/wFifo/_zz_ram_port10__0[23] SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.974ns (logic 0.612ns (62.847%) route 0.362ns (37.153%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.683ns Source Clock Delay (SCD): -0.458ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X72Y104 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X72Y104 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.154 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/O net (fo=1, routed) 0.362 0.516 u_Axi_CDC/arFifo/_zz_ram_port10__1[42] SLICE_X71Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.580 -0.683 u_Axi_CDC/arFifo/sys_clk SLICE_X71Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.981ns (logic 0.595ns (60.677%) route 0.386ns (39.323%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.699ns Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X88Y114 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y114 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.128 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/O net (fo=1, routed) 0.386 0.513 u_Axi_CDC/awFifo/_zz_ram_port10[19] SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.564 -0.699 u_Axi_CDC/awFifo/sys_clk SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.972ns (logic 0.482ns (49.575%) route 0.490ns (50.425%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.698ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.843 -0.465 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X90Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y115 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.017 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/O net (fo=1, routed) 0.490 0.507 u_Axi_CDC/awFifo/_zz_ram_port10[3] SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.973ns (logic 0.485ns (49.868%) route 0.488ns (50.132%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.698ns Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.018 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/O net (fo=1, routed) 0.488 0.505 u_Axi_CDC/awFifo/_zz_ram_port10[10] SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.968ns (logic 0.480ns (49.581%) route 0.488ns (50.419%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.700ns Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.013 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC_D1/O net (fo=1, routed) 0.488 0.501 u_Axi_CDC/awFifo/_zz_ram_port10[11] SLICE_X82Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.563 -0.700 u_Axi_CDC/awFifo/sys_clk SLICE_X82Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.957ns (logic 0.595ns (62.152%) route 0.362ns (37.848%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.691ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.843 -0.465 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X90Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y115 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.130 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/O net (fo=1, routed) 0.362 0.492 u_Axi_CDC/awFifo/_zz_ram_port10[1] SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.572 -0.691 u_Axi_CDC/awFifo/sys_clk SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.877ns (logic 0.612ns (69.814%) route 0.265ns (30.186%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.921 -0.387 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X70Y99 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y99 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.225 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/O net (fo=1, routed) 0.265 0.489 u_Axi_CDC/arFifo/_zz_ram_port10__1[48] SLICE_X71Y99 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_Axi_CDC/arFifo/sys_clk SLICE_X71Y99 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.966ns (logic 0.612ns (63.379%) route 0.354ns (36.621%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.699ns Source Clock Delay (SCD): -0.476ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.832 -0.476 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X84Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y115 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.136 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/O net (fo=1, routed) 0.354 0.489 u_Axi_CDC/awFifo/_zz_ram_port10[12] SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.564 -0.699 u_Axi_CDC/awFifo/sys_clk SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.961ns (logic 0.612ns (63.711%) route 0.349ns (36.289%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.705ns Source Clock Delay (SCD): -0.471ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X90Y128 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y128 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.141 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.349 0.489 u_Axi_CDC/wFifo/_zz_ram_port10__0[12] SLICE_X83Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk SLICE_X83Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.938ns (logic 0.612ns (65.272%) route 0.326ns (34.728%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.677ns Source Clock Delay (SCD): -0.451ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.857 -0.451 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X60Y100 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y100 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.161 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/O net (fo=1, routed) 0.326 0.486 u_Axi_CDC/awFifo/_zz_ram_port10[30] SLICE_X59Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.586 -0.677 u_Axi_CDC/awFifo/sys_clk SLICE_X59Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.957ns (logic 0.480ns (50.151%) route 0.477ns (49.849%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.696ns Source Clock Delay (SCD): -0.471ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X84Y109 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y109 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.009 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/O net (fo=1, routed) 0.477 0.486 u_Axi_CDC/arFifo/_zz_ram_port10__1[29] SLICE_X80Y107 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.567 -0.696 u_Axi_CDC/arFifo/sys_clk SLICE_X80Y107 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.954ns (logic 0.612ns (64.150%) route 0.342ns (35.850%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.703ns Source Clock Delay (SCD): -0.469ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X90Y130 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y130 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.143 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.342 0.485 u_Axi_CDC/wFifo/_zz_ram_port10__0[24] SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.934ns (logic 0.595ns (63.705%) route 0.339ns (36.295%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.680ns Source Clock Delay (SCD): -0.455ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.853 -0.455 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK SLICE_X64Y106 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y106 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.140 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/O net (fo=1, routed) 0.339 0.479 u_Axi_CDC/awFifo/_zz_ram_port10[43] SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.583 -0.680 u_Axi_CDC/awFifo/sys_clk SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.957ns (logic 0.612ns (63.965%) route 0.345ns (36.035%)) Logic Levels: 0 Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.697ns Source Clock Delay (SCD): -0.479ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.829 -0.479 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X84Y118 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y118 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.133 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 0.345 0.478 u_Axi_CDC/arFifo/_zz_ram_port10__1[0] SLICE_X85Y110 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.566 -0.697 u_Axi_CDC/arFifo/sys_clk SLICE_X85Y110 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.939ns (logic 0.491ns (52.288%) route 0.448ns (47.712%)) Logic Levels: 0 Clock Path Skew: -0.236ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.705ns Source Clock Delay (SCD): -0.469ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X90Y130 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y130 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.022 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 0.448 0.470 u_Axi_CDC/wFifo/_zz_ram_port10__0[26] SLICE_X82Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk SLICE_X82Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[26]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.918ns (logic 0.595ns (64.781%) route 0.323ns (35.219%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.677ns Source Clock Delay (SCD): -0.451ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.857 -0.451 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X60Y100 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y100 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.144 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/O net (fo=1, routed) 0.323 0.467 u_Axi_CDC/awFifo/_zz_ram_port10[31] SLICE_X59Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.586 -0.677 u_Axi_CDC/awFifo/sys_clk SLICE_X59Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.935ns (logic 0.595ns (63.627%) route 0.340ns (36.373%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.705ns Source Clock Delay (SCD): -0.471ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X90Y128 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y128 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.124 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.340 0.464 u_Axi_CDC/wFifo/_zz_ram_port10__0[13] SLICE_X85Y128 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk SLICE_X85Y128 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.850ns (logic 0.595ns (69.961%) route 0.255ns (30.039%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.921 -0.387 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X70Y99 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y99 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.208 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/O net (fo=1, routed) 0.255 0.463 u_Axi_CDC/arFifo/_zz_ram_port10__1[49] SLICE_X71Y98 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_Axi_CDC/arFifo/sys_clk SLICE_X71Y98 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.909ns (logic 0.480ns (52.817%) route 0.429ns (47.183%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.677ns Source Clock Delay (SCD): -0.451ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.857 -0.451 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X60Y100 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y100 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.029 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/O net (fo=1, routed) 0.429 0.458 u_Axi_CDC/awFifo/_zz_ram_port10[35] SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.586 -0.677 u_Axi_CDC/awFifo/sys_clk SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.900ns (logic 0.491ns (54.536%) route 0.409ns (45.464%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.683ns Source Clock Delay (SCD): -0.458ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X70Y103 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y103 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.033 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/O net (fo=1, routed) 0.409 0.442 u_Axi_CDC/arFifo/_zz_ram_port10__1[32] SLICE_X71Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.580 -0.683 u_Axi_CDC/arFifo/sys_clk SLICE_X71Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.916ns (logic 0.491ns (53.631%) route 0.425ns (46.369%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.700ns Source Clock Delay (SCD): -0.476ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.832 -0.476 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X84Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y115 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.015 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/O net (fo=1, routed) 0.425 0.439 u_Axi_CDC/awFifo/_zz_ram_port10[14] SLICE_X82Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.563 -0.700 u_Axi_CDC/awFifo/sys_clk SLICE_X82Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[14]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[40]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.896ns (logic 0.485ns (54.133%) route 0.411ns (45.867%)) Logic Levels: 0 Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.457ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.851 -0.457 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y100 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y100 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.028 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/O net (fo=1, routed) 0.411 0.439 u_Axi_CDC/arFifo/_zz_ram_port10__1[40] SLICE_X71Y99 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[40]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_Axi_CDC/arFifo/sys_clk SLICE_X71Y99 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[40]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[52]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.826ns (logic 0.485ns (58.744%) route 0.341ns (41.256%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.921 -0.387 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X70Y99 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y99 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.098 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/O net (fo=1, routed) 0.341 0.438 u_Axi_CDC/arFifo/_zz_ram_port10__1[52] SLICE_X71Y98 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[52]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_Axi_CDC/arFifo/sys_clk SLICE_X71Y98 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[52]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.908ns (logic 0.612ns (67.416%) route 0.296ns (32.584%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.702ns Source Clock Delay (SCD): -0.471ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X88Y131 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y131 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.141 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 0.296 0.437 u_Axi_CDC/wFifo/_zz_ram_port10__0[6] SLICE_X87Y131 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk SLICE_X87Y131 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.905ns (logic 0.491ns (54.225%) route 0.414ns (45.775%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.696ns Source Clock Delay (SCD): -0.471ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X84Y109 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y109 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.020 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/O net (fo=1, routed) 0.414 0.434 u_Axi_CDC/arFifo/_zz_ram_port10__1[26] SLICE_X80Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.567 -0.696 u_Axi_CDC/arFifo/sys_clk SLICE_X80Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/C Slack: inf Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Fast Process Corner) Data Path Delay: 0.896ns (logic 0.260ns (29.032%) route 0.636ns (70.968%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.693ns Source Clock Delay (SCD): -0.462ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.846 -0.462 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.204 -0.258 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.241 -0.017 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.056 0.039 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.394 0.433 u_Axi_CDC/awFifo/bufferCC_12/p_0_in SLICE_X92Y123 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C Slack: inf Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Fast Process Corner) Data Path Delay: 0.896ns (logic 0.260ns (29.032%) route 0.636ns (70.968%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.693ns Source Clock Delay (SCD): -0.462ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.846 -0.462 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.204 -0.258 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.241 -0.017 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.056 0.039 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.394 0.433 u_Axi_CDC/awFifo/bufferCC_12/p_0_in SLICE_X92Y123 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.887ns (logic 0.612ns (68.980%) route 0.275ns (31.020%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.683ns Source Clock Delay (SCD): -0.458ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X70Y103 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y103 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.154 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/O net (fo=1, routed) 0.275 0.429 u_Axi_CDC/arFifo/_zz_ram_port10__1[30] SLICE_X68Y103 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.580 -0.683 u_Axi_CDC/arFifo/sys_clk SLICE_X68Y103 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.801ns (logic 0.612ns (76.427%) route 0.189ns (23.573%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.608ns Source Clock Delay (SCD): -0.381ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.927 -0.381 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK SLICE_X60Y98 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y98 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.231 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/O net (fo=1, routed) 0.189 0.420 u_Axi_CDC/awFifo/_zz_ram_port10[48] SLICE_X57Y98 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.654 -0.608 u_Axi_CDC/awFifo/sys_clk SLICE_X57Y98 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: mlkem_clk To Clock: sys_clk Max Delay 61 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 5.746ns (logic 0.642ns (11.174%) route 5.104ns (88.826%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.546ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.123ns Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 2.674 3.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1 SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.705 -2.123 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C Slack: inf Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 5.746ns (logic 0.642ns (11.174%) route 5.104ns (88.826%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.546ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.123ns Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 2.674 3.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1 SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.705 -2.123 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.364ns (logic 0.612ns (44.884%) route 0.752ns (55.116%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 0.752 0.977 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.284ns (logic 0.612ns (47.657%) route 0.672ns (52.343%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 0.672 0.895 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[0] SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.195ns (logic 0.595ns (49.811%) route 0.600ns (50.189%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 0.600 0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7] SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.183ns (logic 0.595ns (50.304%) route 0.588ns (49.696%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.588 0.797 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.169ns (logic 0.612ns (52.356%) route 0.557ns (47.644%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.612ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 0.557 0.780 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.167ns (logic 0.612ns (52.454%) route 0.555ns (47.546%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 0.555 0.779 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.166ns (logic 0.480ns (41.172%) route 0.686ns (58.828%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.092 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 0.686 0.778 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.160ns (logic 0.612ns (52.737%) route 0.548ns (47.263%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.548 0.771 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.139ns (logic 0.612ns (53.734%) route 0.527ns (46.266%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.527 0.750 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.128ns (logic 0.595ns (52.742%) route 0.533ns (47.258%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.533 0.739 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.122ns (logic 0.595ns (53.042%) route 0.527ns (46.958%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.527 0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.103ns (logic 0.482ns (43.685%) route 0.621ns (56.315%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 0.621 0.714 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.093ns (logic 0.485ns (44.377%) route 0.608ns (55.623%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 0.608 0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[10] SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.073ns (logic 0.595ns (55.460%) route 0.478ns (44.540%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.478 0.684 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.071ns (logic 0.595ns (55.545%) route 0.476ns (44.455%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.476 0.682 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25] SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.064ns (logic 0.485ns (45.566%) route 0.579ns (54.434%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 0.579 0.675 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28] SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.051ns (logic 0.485ns (46.153%) route 0.566ns (53.847%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 0.566 0.662 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[4] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.028ns (logic 0.485ns (47.163%) route 0.543ns (52.837%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.543 0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.026ns (logic 0.482ns (46.972%) route 0.544ns (53.028%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O net (fo=1, routed) 0.544 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.007ns (logic 0.491ns (48.781%) route 0.516ns (51.219%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.103 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 0.516 0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.001ns (logic 0.485ns (48.445%) route 0.516ns (51.555%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.516 0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.998ns (logic 0.480ns (48.113%) route 0.518ns (51.887%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 0.518 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5] SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.998ns (logic 0.491ns (49.223%) route 0.507ns (50.777%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 0.507 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[2] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.994ns (logic 0.482ns (48.479%) route 0.512ns (51.521%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 0.512 0.605 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[27] SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.990ns (logic 0.480ns (48.485%) route 0.510ns (51.515%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 0.510 0.601 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[29] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.988ns (logic 0.491ns (49.720%) route 0.497ns (50.280%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.612ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 0.497 0.598 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[14] SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.982ns (logic 0.482ns (49.063%) route 0.500ns (50.937%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 0.500 0.594 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[9] SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.976ns (logic 0.491ns (50.291%) route 0.485ns (49.709%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.612ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 0.485 0.587 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[20] SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.973ns (logic 0.480ns (49.328%) route 0.493ns (50.672%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.612ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/O net (fo=1, routed) 0.493 0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[17] SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.967ns (logic 0.491ns (50.782%) route 0.476ns (49.218%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 0.476 0.578 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.954ns (logic 0.482ns (50.541%) route 0.472ns (49.459%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 0.472 0.564 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.937ns (logic 0.480ns (51.206%) route 0.457ns (48.794%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 0.457 0.548 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.858ns (logic 0.595ns (69.330%) route 0.263ns (30.670%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O net (fo=1, routed) 0.263 0.472 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.855ns (logic 0.612ns (71.580%) route 0.243ns (28.420%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O net (fo=1, routed) 0.243 0.469 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36] SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.817ns (logic 0.480ns (58.732%) route 0.337ns (41.268%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O net (fo=1, routed) 0.337 0.431 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.790ns (logic 0.482ns (60.993%) route 0.308ns (39.007%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O net (fo=1, routed) 0.308 0.404 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] SLICE_X65Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X65Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.750ns (logic 0.485ns (64.709%) route 0.265ns (35.291%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O net (fo=1, routed) 0.265 0.363 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.695ns (logic 0.491ns (70.608%) route 0.204ns (29.392%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.105 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 0.204 0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[32] SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.694ns (logic 0.491ns (70.730%) route 0.203ns (29.270%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.105 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O net (fo=1, routed) 0.203 0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.686ns (logic 0.482ns (70.214%) route 0.204ns (29.786%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O net (fo=1, routed) 0.204 0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.554ns (logic 0.485ns (87.546%) route 0.069ns (12.454%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.381ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y90 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.104 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O net (fo=1, routed) 0.069 0.173 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] SLICE_X53Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk SLICE_X53Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.489ns (logic 0.175ns (35.822%) route 0.314ns (64.178%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.617ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.175 -0.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.314 0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1] SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.475ns (logic 0.175ns (36.832%) route 0.300ns (63.168%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.612ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X50Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y85 FDCE (Prop_fdce_C_Q) 0.175 -0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.300 0.090 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[1] SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.544ns (logic 0.175ns (32.186%) route 0.369ns (67.814%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.682ns Source Clock Delay (SCD): -0.455ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.853 -0.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X93Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y102 FDCE (Prop_fdce_C_Q) 0.175 -0.280 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q net (fo=2, routed) 0.369 0.089 u_fft_mlkem_axi_slave/mlkem_intr_m SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.581 -0.682 u_fft_mlkem_axi_slave/sys_clk SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.458ns (logic 0.175ns (38.242%) route 0.283ns (61.758%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.611ns Source Clock Delay (SCD): -0.381ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X54Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y90 FDCE (Prop_fdce_C_Q) 0.175 -0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.283 0.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.438ns (logic 0.204ns (46.570%) route 0.234ns (53.430%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.621ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y96 FDCE (Prop_fdce_C_Q) 0.204 -0.184 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.234 0.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.422ns (logic 0.160ns (37.932%) route 0.262ns (62.068%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.618ns Source Clock Delay (SCD): -0.390ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.160 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.262 0.032 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.410ns (logic 0.175ns (42.699%) route 0.235ns (57.301%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.618ns Source Clock Delay (SCD): -0.390ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.175 -0.215 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.235 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[3] SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: clkfbout_clk_pll To Clock: Max Delay 1 Endpoint Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT (clock source 'clkfbout_clk_pll' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Path Group: (none) Path Type: Max at Fast Process Corner Data Path Delay: 1.519ns (logic 0.029ns (1.909%) route 1.490ns (98.091%)) Logic Levels: 1 (BUFG=1) Clock Uncertainty: 0.225ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.110ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clkfbout_clk_pll fall edge) 10.000 10.000 f K21 0.000 10.000 f clk (IN) net (fo=0) 0.000 10.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 10.419 f pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 10.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.847 8.053 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT net (fo=1, routed) 0.611 8.663 pll_clk.u_clk_pll/inst/clkfbout_clk_pll BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.029 8.692 f pll_clk.u_clk_pll/inst/clkf_buf/O net (fo=1, routed) 0.880 9.572 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: Max Delay 41 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_axi_dvi/DVI_SQU_DIR_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 15.825ns (logic 6.208ns (39.226%) route 9.618ns (60.774%)) Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.835 -2.507 u_axi_dvi/sys_clk SLICE_X42Y81 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.989 r u_axi_dvi/DVI_SQU_DIR_reg[0]/Q net (fo=5, routed) 1.348 -0.641 u_axi_dvi/DVI_SQU_DIR_reg_n_0_[0] SLICE_X42Y84 LUT2 (Prop_lut2_I0_O) 0.124 -0.517 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/O net (fo=1, routed) 0.000 -0.517 u_axi_dvi/video_red_OBUF[2]_inst_i_264_n_0 SLICE_X42Y84 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 -0.004 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/CO[3] net (fo=1, routed) 0.000 -0.004 u_axi_dvi/video_red_OBUF[2]_inst_i_225_n_0 SLICE_X42Y85 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 0.113 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CO[3] net (fo=1, routed) 0.000 0.113 u_axi_dvi/video_red_OBUF[2]_inst_i_165_n_0 SLICE_X42Y86 CARRY4 (Prop_carry4_CI_O[1]) 0.323 0.436 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/O[1] net (fo=1, routed) 1.222 1.658 u_axi_dvi/video_red_OBUF[2]_inst_i_96_n_6 SLICE_X42Y82 LUT2 (Prop_lut2_I1_O) 0.306 1.964 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/O net (fo=1, routed) 0.000 1.964 u_axi_dvi/video_red_OBUF[2]_inst_i_38_n_0 SLICE_X42Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 2.497 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/CO[3] net (fo=1, routed) 0.000 2.497 u_axi_dvi/video_red_OBUF[2]_inst_i_7_n_0 SLICE_X42Y83 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 2.614 f u_axi_dvi/video_red_OBUF[2]_inst_i_2/CO[3] net (fo=1, routed) 1.354 3.969 u_axi_dvi/video_red_OBUF[2]_inst_i_2_n_0 SLICE_X41Y85 LUT5 (Prop_lut5_I0_O) 0.124 4.093 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 5.693 9.786 video_red_OBUF[0] K23 OBUF (Prop_obuf_I_O) 3.533 13.319 r video_red_OBUF[0]_inst/O net (fo=0) 0.000 13.319 video_red[0] K23 r video_red[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/DVI_SQU_DIR_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 15.712ns (logic 6.235ns (39.686%) route 9.476ns (60.314%)) Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.835 -2.507 u_axi_dvi/sys_clk SLICE_X42Y81 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.989 r u_axi_dvi/DVI_SQU_DIR_reg[0]/Q net (fo=5, routed) 1.348 -0.641 u_axi_dvi/DVI_SQU_DIR_reg_n_0_[0] SLICE_X42Y84 LUT2 (Prop_lut2_I0_O) 0.124 -0.517 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/O net (fo=1, routed) 0.000 -0.517 u_axi_dvi/video_red_OBUF[2]_inst_i_264_n_0 SLICE_X42Y84 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 -0.004 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/CO[3] net (fo=1, routed) 0.000 -0.004 u_axi_dvi/video_red_OBUF[2]_inst_i_225_n_0 SLICE_X42Y85 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 0.113 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CO[3] net (fo=1, routed) 0.000 0.113 u_axi_dvi/video_red_OBUF[2]_inst_i_165_n_0 SLICE_X42Y86 CARRY4 (Prop_carry4_CI_O[1]) 0.323 0.436 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/O[1] net (fo=1, routed) 1.222 1.658 u_axi_dvi/video_red_OBUF[2]_inst_i_96_n_6 SLICE_X42Y82 LUT2 (Prop_lut2_I1_O) 0.306 1.964 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/O net (fo=1, routed) 0.000 1.964 u_axi_dvi/video_red_OBUF[2]_inst_i_38_n_0 SLICE_X42Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 2.497 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/CO[3] net (fo=1, routed) 0.000 2.497 u_axi_dvi/video_red_OBUF[2]_inst_i_7_n_0 SLICE_X42Y83 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 2.614 f u_axi_dvi/video_red_OBUF[2]_inst_i_2/CO[3] net (fo=1, routed) 1.354 3.969 u_axi_dvi/video_red_OBUF[2]_inst_i_2_n_0 SLICE_X41Y85 LUT5 (Prop_lut5_I0_O) 0.124 4.093 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 5.552 9.645 video_red_OBUF[0] F24 OBUF (Prop_obuf_I_O) 3.560 13.205 r video_red_OBUF[1]_inst/O net (fo=0) 0.000 13.205 video_red[1] F24 r video_red[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/DVI_SQU_DIR_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 15.445ns (logic 6.262ns (40.541%) route 9.183ns (59.459%)) Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.835 -2.507 u_axi_dvi/sys_clk SLICE_X42Y81 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.989 r u_axi_dvi/DVI_SQU_DIR_reg[0]/Q net (fo=5, routed) 1.348 -0.641 u_axi_dvi/DVI_SQU_DIR_reg_n_0_[0] SLICE_X42Y84 LUT2 (Prop_lut2_I0_O) 0.124 -0.517 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/O net (fo=1, routed) 0.000 -0.517 u_axi_dvi/video_red_OBUF[2]_inst_i_264_n_0 SLICE_X42Y84 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 -0.004 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/CO[3] net (fo=1, routed) 0.000 -0.004 u_axi_dvi/video_red_OBUF[2]_inst_i_225_n_0 SLICE_X42Y85 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 0.113 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CO[3] net (fo=1, routed) 0.000 0.113 u_axi_dvi/video_red_OBUF[2]_inst_i_165_n_0 SLICE_X42Y86 CARRY4 (Prop_carry4_CI_O[1]) 0.323 0.436 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/O[1] net (fo=1, routed) 1.222 1.658 u_axi_dvi/video_red_OBUF[2]_inst_i_96_n_6 SLICE_X42Y82 LUT2 (Prop_lut2_I1_O) 0.306 1.964 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/O net (fo=1, routed) 0.000 1.964 u_axi_dvi/video_red_OBUF[2]_inst_i_38_n_0 SLICE_X42Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 2.497 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/CO[3] net (fo=1, routed) 0.000 2.497 u_axi_dvi/video_red_OBUF[2]_inst_i_7_n_0 SLICE_X42Y83 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 2.614 f u_axi_dvi/video_red_OBUF[2]_inst_i_2/CO[3] net (fo=1, routed) 1.354 3.969 u_axi_dvi/video_red_OBUF[2]_inst_i_2_n_0 SLICE_X41Y85 LUT5 (Prop_lut5_I0_O) 0.124 4.093 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 5.259 9.352 video_red_OBUF[0] E26 OBUF (Prop_obuf_I_O) 3.587 12.938 r video_red_OBUF[2]_inst/O net (fo=0) 0.000 12.938 video_red[2] E26 r video_red[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 (clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_clk (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.589ns (logic 3.629ns (42.252%) route 4.960ns (57.748%)) Logic Levels: 2 (BUFG=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk fall edge) 10.000 10.000 f K21 0.000 10.000 f clk (IN) net (fo=0) 0.000 10.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 11.463 f pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 12.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 3.725 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 5.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 5.658 f pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 3.123 8.781 video_clk_OBUF H22 OBUF (Prop_obuf_I_O) 3.533 12.314 f video_clk_OBUF_inst/O net (fo=0) 0.000 12.314 video_clk H22 f video_clk (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_vsync (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 12.805ns (logic 4.379ns (34.194%) route 8.427ns (65.806%)) Logic Levels: 4 (LUT2=1 LUT4=1 LUT6=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.838 -2.504 u_axi_dvi/sys_clk SLICE_X47Y82 FDRE r u_axi_dvi/vdata_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y82 FDRE (Prop_fdre_C_Q) 0.456 -2.048 f u_axi_dvi/vdata_reg[6]/Q net (fo=13, routed) 1.558 -0.490 u_axi_dvi/vdata_reg_n_0_[6] SLICE_X49Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.366 f u_axi_dvi/video_vsync_OBUF_inst_i_5/O net (fo=1, routed) 0.667 0.301 u_axi_dvi/video_vsync_OBUF_inst_i_5_n_0 SLICE_X49Y83 LUT6 (Prop_lut6_I5_O) 0.124 0.425 r u_axi_dvi/video_vsync_OBUF_inst_i_3/O net (fo=1, routed) 0.298 0.723 u_axi_dvi/video_vsync_OBUF_inst_i_3_n_0 SLICE_X49Y81 LUT4 (Prop_lut4_I2_O) 0.124 0.847 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O net (fo=1, routed) 5.904 6.751 video_vsync_OBUF H24 OBUF (Prop_obuf_I_O) 3.551 10.302 r video_vsync_OBUF_inst/O net (fo=0) 0.000 10.302 video_vsync H24 r video_vsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_de (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 12.756ns (logic 4.389ns (34.405%) route 8.367ns (65.595%)) Logic Levels: 4 (LUT2=1 LUT6=2 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.836 -2.506 u_axi_dvi/sys_clk SLICE_X47Y81 FDRE r u_axi_dvi/vdata_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y81 FDRE (Prop_fdre_C_Q) 0.456 -2.050 f u_axi_dvi/vdata_reg[3]/Q net (fo=11, routed) 1.027 -1.023 u_axi_dvi/vdata_reg_n_0_[3] SLICE_X48Y83 LUT2 (Prop_lut2_I0_O) 0.124 -0.899 r u_axi_dvi/vdata[11]_i_4/O net (fo=3, routed) 0.717 -0.182 u_axi_dvi/vdata[11]_i_4_n_0 SLICE_X49Y83 LUT6 (Prop_lut6_I2_O) 0.124 -0.058 r u_axi_dvi/video_de_OBUF_inst_i_2/O net (fo=1, routed) 0.863 0.805 u_axi_dvi/video_de_OBUF_inst_i_2_n_0 SLICE_X46Y83 LUT6 (Prop_lut6_I0_O) 0.124 0.929 r u_axi_dvi/video_de_OBUF_inst_i_1/O net (fo=1, routed) 5.761 6.690 video_de_OBUF G24 OBUF (Prop_obuf_I_O) 3.561 10.251 r video_de_OBUF_inst/O net (fo=0) 0.000 10.251 video_de G24 r video_de (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[4]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_hsync (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.845ns (logic 4.311ns (36.394%) route 7.534ns (63.606%)) Logic Levels: 3 (LUT5=2 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.840 -2.502 u_axi_dvi/sys_clk SLICE_X46Y84 FDRE r u_axi_dvi/hdata_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y84 FDRE (Prop_fdre_C_Q) 0.518 -1.984 r u_axi_dvi/hdata_reg[4]/Q net (fo=11, routed) 1.550 -0.433 u_axi_dvi/hdata_reg_n_0_[4] SLICE_X41Y85 LUT5 (Prop_lut5_I4_O) 0.124 -0.309 f u_axi_dvi/video_hsync_OBUF_inst_i_2/O net (fo=1, routed) 0.291 -0.018 u_axi_dvi/video_hsync_OBUF_inst_i_2_n_0 SLICE_X41Y86 LUT5 (Prop_lut5_I4_O) 0.124 0.106 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O net (fo=1, routed) 5.693 5.799 video_hsync_OBUF J24 OBUF (Prop_obuf_I_O) 3.545 9.343 r video_hsync_OBUF_inst/O net (fo=0) 0.000 9.343 video_hsync J24 r video_hsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.827ns (logic 4.074ns (37.631%) route 6.753ns (62.369%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q net (fo=1, routed) 6.753 4.594 dpy0_OBUF[6] B17 OBUF (Prop_obuf_I_O) 3.556 8.151 r dpy0_OBUF[6]_inst/O net (fo=0) 0.000 8.151 dpy0[6] B17 r dpy0[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_TX (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.830ns (logic 4.317ns (39.866%) route 6.513ns (60.134%)) Logic Levels: 2 (LUT3=1 OBUFT=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.638 -2.704 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X80Y133 FDRE r u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y133 FDRE (Prop_fdre_C_Q) 0.478 -2.226 f u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/Q net (fo=13, routed) 1.393 -0.832 u_axi_uart_controller/uart0/regs/transmitter/tf_pop_reg_0[1] SLICE_X77Y137 LUT3 (Prop_lut3_I1_O) 0.295 -0.537 f u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O net (fo=1, routed) 5.119 4.582 UART_TX_IOBUF_inst/T H18 OBUFT (TriStatE_obuft_T_O) 3.544 8.126 r UART_TX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 8.126 UART_TX H18 r UART_TX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.564ns (logic 4.063ns (38.456%) route 6.502ns (61.544%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q net (fo=1, routed) 6.502 4.343 dpy0_OBUF[7] C17 OBUF (Prop_obuf_I_O) 3.545 7.888 r dpy0_OBUF[7]_inst/O net (fo=0) 0.000 7.888 dpy0[7] C17 r dpy0[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.495ns (logic 4.057ns (38.657%) route 6.438ns (61.343%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q net (fo=1, routed) 6.438 4.280 dpy0_OBUF[4] E18 OBUF (Prop_obuf_I_O) 3.539 7.819 r dpy0_OBUF[4]_inst/O net (fo=0) 0.000 7.819 dpy0[4] E18 r dpy0[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_RX (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.517ns (logic 4.100ns (38.989%) route 6.416ns (61.011%)) Logic Levels: 2 (LUT2=1 OBUFT=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.643 -2.699 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X85Y134 FDRE r u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y134 FDRE (Prop_fdre_C_Q) 0.456 -2.243 r u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/Q net (fo=2, routed) 0.810 -1.433 u_axi_uart_controller/uart0/regs/sclk_por SLICE_X86Y135 LUT2 (Prop_lut2_I1_O) 0.124 -1.309 r u_axi_uart_controller/uart0/regs/UART_RX_IOBUF_inst_i_1/O net (fo=1, routed) 5.607 4.298 UART_RX_IOBUF_inst/I J20 OBUFT (Prop_obuft_I_O) 3.520 7.818 r UART_RX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 7.818 UART_RX J20 r UART_RX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.196ns (logic 4.016ns (39.389%) route 6.180ns (60.611%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.666 -2.676 u_confreg/u_digitaltube_controller/sys_clk SLICE_X63Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y141 FDCE (Prop_fdce_C_Q) 0.456 -2.220 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q net (fo=1, routed) 6.180 3.960 dpy0_OBUF[0] B19 OBUF (Prop_obuf_I_O) 3.560 7.520 r dpy0_OBUF[0]_inst/O net (fo=0) 0.000 7.520 dpy0[0] B19 r dpy0[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.115ns (logic 4.038ns (39.923%) route 6.077ns (60.077%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.646 -2.696 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.518 -2.178 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q net (fo=1, routed) 6.077 3.899 dpy1_OBUF[7] G17 OBUF (Prop_obuf_I_O) 3.520 7.419 r dpy1_OBUF[7]_inst/O net (fo=0) 0.000 7.419 dpy1[7] G17 r dpy1[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.022ns (logic 4.002ns (39.929%) route 6.021ns (60.071%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q net (fo=1, routed) 6.021 3.800 dpy0_OBUF[5] C19 OBUF (Prop_obuf_I_O) 3.546 7.346 r dpy0_OBUF[5]_inst/O net (fo=0) 0.000 7.346 dpy0[5] C19 r dpy0[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.920ns (logic 4.091ns (41.241%) route 5.829ns (58.759%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q net (fo=1, routed) 5.829 3.670 dpy0_OBUF[3] A19 OBUF (Prop_obuf_I_O) 3.573 7.243 r dpy0_OBUF[3]_inst/O net (fo=0) 0.000 7.243 dpy0[3] A19 r dpy0[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.911ns (logic 4.032ns (40.684%) route 5.879ns (59.316%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.646 -2.696 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.518 -2.178 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q net (fo=1, routed) 5.879 3.701 dpy1_OBUF[3] F17 OBUF (Prop_obuf_I_O) 3.514 7.215 r dpy1_OBUF[3]_inst/O net (fo=0) 0.000 7.215 dpy1[3] F17 r dpy1[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.858ns (logic 4.055ns (41.135%) route 5.803ns (58.865%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.644 -2.698 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.518 -2.180 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q net (fo=1, routed) 5.803 3.623 dpy1_OBUF[6] F15 OBUF (Prop_obuf_I_O) 3.537 7.160 r dpy1_OBUF[6]_inst/O net (fo=0) 0.000 7.160 dpy1[6] F15 r dpy1[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.779ns (logic 4.052ns (41.435%) route 5.727ns (58.565%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.644 -2.698 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.518 -2.180 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q net (fo=1, routed) 5.727 3.547 dpy1_OBUF[5] G16 OBUF (Prop_obuf_I_O) 3.534 7.081 r dpy1_OBUF[5]_inst/O net (fo=0) 0.000 7.081 dpy1[5] G16 r dpy1[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.775ns (logic 4.060ns (41.529%) route 5.716ns (58.471%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.646 -2.696 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.518 -2.178 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q net (fo=1, routed) 5.716 3.538 dpy1_OBUF[4] E16 OBUF (Prop_obuf_I_O) 3.542 7.079 r dpy1_OBUF[4]_inst/O net (fo=0) 0.000 7.079 dpy1[4] E16 r dpy1[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.705ns (logic 4.067ns (41.907%) route 5.638ns (58.093%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.644 -2.698 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.518 -2.180 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q net (fo=1, routed) 5.638 3.458 dpy1_OBUF[1] D16 OBUF (Prop_obuf_I_O) 3.549 7.007 r dpy1_OBUF[1]_inst/O net (fo=0) 0.000 7.007 dpy1[1] D16 r dpy1[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.696ns (logic 4.083ns (42.113%) route 5.613ns (57.887%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.646 -2.696 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.518 -2.178 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q net (fo=1, routed) 5.613 3.435 dpy1_OBUF[0] A17 OBUF (Prop_obuf_I_O) 3.565 7.000 r dpy1_OBUF[0]_inst/O net (fo=0) 0.000 7.000 dpy1[0] A17 r dpy1[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.645ns (logic 4.014ns (41.623%) route 5.630ns (58.377%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q net (fo=1, routed) 5.630 3.410 dpy0_OBUF[2] B21 OBUF (Prop_obuf_I_O) 3.558 6.968 r dpy0_OBUF[2]_inst/O net (fo=0) 0.000 6.968 dpy0[2] B21 r dpy0[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.634ns (logic 4.001ns (41.531%) route 5.633ns (58.469%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q net (fo=1, routed) 5.633 3.413 dpy0_OBUF[1] D19 OBUF (Prop_obuf_I_O) 3.545 6.958 r dpy0_OBUF[1]_inst/O net (fo=0) 0.000 6.958 dpy0[1] D19 r dpy0[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.306ns (logic 4.060ns (43.623%) route 5.246ns (56.377%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.644 -2.698 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.518 -2.180 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q net (fo=1, routed) 5.246 3.066 dpy1_OBUF[2] E17 OBUF (Prop_obuf_I_O) 3.542 6.608 r dpy1_OBUF[2]_inst/O net (fo=0) 0.000 6.608 dpy1[2] E17 r dpy1[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[14]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[14] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.878ns (logic 4.081ns (45.964%) route 4.798ns (54.036%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.769 -2.573 u_confreg/sys_clk SLICE_X22Y141 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.055 r u_confreg/led_data_reg[14]_lopt_replica/Q net (fo=1, routed) 4.798 2.743 lopt_5 A20 OBUF (Prop_obuf_I_O) 3.563 6.306 r leds_OBUF[14]_inst/O net (fo=0) 0.000 6.306 leds[14] A20 r leds[14] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[6]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.860ns (logic 4.060ns (45.821%) route 4.800ns (54.179%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk SLICE_X12Y142 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.518 -2.051 r u_confreg/led_data_reg[6]_lopt_replica/Q net (fo=1, routed) 4.800 2.749 lopt_12 E20 OBUF (Prop_obuf_I_O) 3.542 6.291 r leds_OBUF[6]_inst/O net (fo=0) 0.000 6.291 leds[6] E20 r leds[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[7]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.741ns (logic 4.090ns (46.792%) route 4.651ns (53.208%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk SLICE_X12Y142 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.518 -2.051 r u_confreg/led_data_reg[7]_lopt_replica/Q net (fo=1, routed) 4.651 2.600 lopt_13 B22 OBUF (Prop_obuf_I_O) 3.572 6.172 r leds_OBUF[7]_inst/O net (fo=0) 0.000 6.172 leds[7] B22 r leds[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[8]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[8] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.684ns (logic 4.079ns (46.970%) route 4.605ns (53.030%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.769 -2.573 u_confreg/sys_clk SLICE_X22Y141 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.055 r u_confreg/led_data_reg[8]_lopt_replica/Q net (fo=1, routed) 4.605 2.551 lopt_14 C23 OBUF (Prop_obuf_I_O) 3.561 6.112 r leds_OBUF[8]_inst/O net (fo=0) 0.000 6.112 leds[8] C23 r leds[8] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[2]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.692ns (logic 4.105ns (47.224%) route 4.587ns (52.776%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.758 -2.584 u_confreg/sys_clk SLICE_X36Y140 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X36Y140 FDRE (Prop_fdre_C_Q) 0.518 -2.066 r u_confreg/led_data_reg[2]_lopt_replica/Q net (fo=1, routed) 4.587 2.522 lopt_8 A24 OBUF (Prop_obuf_I_O) 3.587 6.109 r leds_OBUF[2]_inst/O net (fo=0) 0.000 6.109 leds[2] A24 r leds[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[5]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.677ns (logic 4.071ns (46.921%) route 4.606ns (53.079%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.771 -2.571 u_confreg/sys_clk SLICE_X20Y141 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X20Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.053 r u_confreg/led_data_reg[5]_lopt_replica/Q net (fo=1, routed) 4.606 2.553 lopt_11 C21 OBUF (Prop_obuf_I_O) 3.553 6.107 r leds_OBUF[5]_inst/O net (fo=0) 0.000 6.107 leds[5] C21 r leds[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[4]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.674ns (logic 4.080ns (47.039%) route 4.594ns (52.961%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.769 -2.573 u_confreg/sys_clk SLICE_X22Y141 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.055 r u_confreg/led_data_reg[4]_lopt_replica/Q net (fo=1, routed) 4.594 2.539 lopt_10 C22 OBUF (Prop_obuf_I_O) 3.562 6.101 r leds_OBUF[4]_inst/O net (fo=0) 0.000 6.101 leds[4] C22 r leds[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[13]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[13] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.553ns (logic 4.027ns (47.079%) route 4.526ns (52.921%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk SLICE_X13Y142 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X13Y142 FDRE (Prop_fdre_C_Q) 0.456 -2.113 r u_confreg/led_data_reg[13]_lopt_replica/Q net (fo=1, routed) 4.526 2.414 lopt_4 A22 OBUF (Prop_obuf_I_O) 3.571 5.984 r leds_OBUF[13]_inst/O net (fo=0) 0.000 5.984 leds[13] A22 r leds[13] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[3]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.563ns (logic 4.080ns (47.648%) route 4.483ns (52.352%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.759 -2.583 u_confreg/sys_clk SLICE_X36Y141 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X36Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.065 r u_confreg/led_data_reg[3]_lopt_replica/Q net (fo=1, routed) 4.483 2.418 lopt_9 D23 OBUF (Prop_obuf_I_O) 3.562 5.980 r leds_OBUF[3]_inst/O net (fo=0) 0.000 5.980 leds[3] D23 r leds[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[1]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.399ns (logic 4.059ns (48.331%) route 4.339ns (51.669%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk SLICE_X12Y142 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.518 -2.051 r u_confreg/led_data_reg[1]_lopt_replica/Q net (fo=1, routed) 4.339 2.289 lopt_7 E21 OBUF (Prop_obuf_I_O) 3.541 5.830 r leds_OBUF[1]_inst/O net (fo=0) 0.000 5.830 leds[1] E21 r leds[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[11]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[11] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.149ns (logic 4.085ns (50.125%) route 4.064ns (49.875%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk SLICE_X12Y141 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.051 r u_confreg/led_data_reg[11]_lopt_replica/Q net (fo=1, routed) 4.064 2.014 lopt_2 A18 OBUF (Prop_obuf_I_O) 3.567 5.580 r leds_OBUF[11]_inst/O net (fo=0) 0.000 5.580 leds[11] A18 r leds[11] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[12]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[12] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.027ns (logic 3.998ns (49.809%) route 4.029ns (50.191%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk SLICE_X13Y142 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X13Y142 FDRE (Prop_fdre_C_Q) 0.456 -2.113 r u_confreg/led_data_reg[12]_lopt_replica/Q net (fo=1, routed) 4.029 1.916 lopt_3 D20 OBUF (Prop_obuf_I_O) 3.542 5.459 r leds_OBUF[12]_inst/O net (fo=0) 0.000 5.459 leds[12] D20 r leds[12] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 7.984ns (logic 4.093ns (51.265%) route 3.891ns (48.735%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.769 -2.573 u_confreg/sys_clk SLICE_X22Y141 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.055 r u_confreg/led_data_reg[0]_lopt_replica/Q net (fo=1, routed) 3.891 1.836 lopt B24 OBUF (Prop_obuf_I_O) 3.575 5.411 r leds_OBUF[0]_inst/O net (fo=0) 0.000 5.411 leds[0] B24 r leds[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[10]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[10] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 7.925ns (logic 4.065ns (51.296%) route 3.860ns (48.704%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.771 -2.571 u_confreg/sys_clk SLICE_X20Y141 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X20Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.053 r u_confreg/led_data_reg[10]_lopt_replica/Q net (fo=1, routed) 3.860 1.807 lopt_1 D21 OBUF (Prop_obuf_I_O) 3.547 5.354 r leds_OBUF[10]_inst/O net (fo=0) 0.000 5.354 leds[10] D21 r leds[10] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[15]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[15] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 7.829ns (logic 4.081ns (52.122%) route 3.749ns (47.878%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk SLICE_X12Y142 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.518 -2.051 r u_confreg/led_data_reg[15]_lopt_replica/Q net (fo=1, routed) 3.749 1.698 lopt_6 B20 OBUF (Prop_obuf_I_O) 3.563 5.261 r leds_OBUF[15]_inst/O net (fo=0) 0.000 5.261 leds[15] B20 r leds[15] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[9]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[9] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 7.704ns (logic 4.100ns (53.220%) route 3.604ns (46.780%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk SLICE_X14Y141 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X14Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.051 r u_confreg/led_data_reg[9]_lopt_replica/Q net (fo=1, routed) 3.604 1.553 lopt_15 A23 OBUF (Prop_obuf_I_O) 3.582 5.136 r leds_OBUF[9]_inst/O net (fo=0) 0.000 5.136 leds[9] A23 r leds[9] (OUT) ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: To Clock: sys_clk Max Delay 43 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: dip_sw[22] (input port) Destination: u_confreg/s_rdata_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.330ns (logic 1.710ns (20.531%) route 6.620ns (79.469%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P6 0.000 0.000 r dip_sw[22] (IN) net (fo=0) 0.000 0.000 dip_sw[22] P6 IBUF (Prop_ibuf_I_O) 1.462 1.462 r dip_sw_IBUF[22]_inst/O net (fo=1, routed) 5.658 7.120 u_confreg/dip_sw_IBUF[22] SLICE_X58Y140 LUT5 (Prop_lut5_I4_O) 0.124 7.244 r u_confreg/s_rdata[22]_i_4/O net (fo=1, routed) 0.963 8.206 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 SLICE_X52Y140 LUT6 (Prop_lut6_I4_O) 0.124 8.330 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O net (fo=1, routed) 0.000 8.330 u_confreg/u_int_ctrl_n_9 SLICE_X52Y140 FDRE r u_confreg/s_rdata_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.551 -2.277 u_confreg/sys_clk SLICE_X52Y140 FDRE r u_confreg/s_rdata_reg[22]/C Slack: inf Source: dip_sw[29] (input port) Destination: u_confreg/s_rdata_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.156ns (logic 1.726ns (21.164%) route 6.430ns (78.836%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T5 0.000 0.000 r dip_sw[29] (IN) net (fo=0) 0.000 0.000 dip_sw[29] T5 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[29]_inst/O net (fo=1, routed) 5.466 6.944 u_confreg/dip_sw_IBUF[29] SLICE_X60Y139 LUT5 (Prop_lut5_I4_O) 0.124 7.068 r u_confreg/s_rdata[29]_i_4/O net (fo=1, routed) 0.963 8.032 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 SLICE_X57Y140 LUT6 (Prop_lut6_I4_O) 0.124 8.156 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O net (fo=1, routed) 0.000 8.156 u_confreg/u_int_ctrl_n_2 SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[29]/C Slack: inf Source: dip_sw[19] (input port) Destination: u_confreg/s_rdata_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.100ns (logic 1.726ns (21.311%) route 6.374ns (78.689%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L4 0.000 0.000 r dip_sw[19] (IN) net (fo=0) 0.000 0.000 dip_sw[19] L4 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[19]_inst/O net (fo=1, routed) 5.423 6.901 u_confreg/dip_sw_IBUF[19] SLICE_X54Y136 LUT5 (Prop_lut5_I4_O) 0.124 7.025 r u_confreg/s_rdata[19]_i_4/O net (fo=1, routed) 0.951 7.976 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.124 8.100 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O net (fo=1, routed) 0.000 8.100 u_confreg/u_int_ctrl_n_12 SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[19]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.928ns (logic 1.980ns (24.979%) route 5.948ns (75.021%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) Clock Path Skew: -2.306ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 5.067 6.541 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X79Y136 LUT2 (Prop_lut2_I1_O) 0.152 6.693 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O net (fo=2, routed) 0.881 7.574 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 SLICE_X78Y136 LUT5 (Prop_lut5_I1_O) 0.354 7.928 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O net (fo=1, routed) 0.000 7.928 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 SLICE_X78Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.522 -2.306 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X78Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C Slack: inf Source: dip_sw[14] (input port) Destination: u_confreg/s_rdata_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.857ns (logic 1.763ns (22.438%) route 6.094ns (77.562%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J1 0.000 0.000 r dip_sw[14] (IN) net (fo=0) 0.000 0.000 dip_sw[14] J1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r dip_sw_IBUF[14]_inst/O net (fo=1, routed) 4.730 6.245 u_confreg/dip_sw_IBUF[14] SLICE_X62Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.369 r u_confreg/s_rdata[14]_i_4/O net (fo=1, routed) 1.365 7.733 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 SLICE_X49Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.857 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O net (fo=1, routed) 0.000 7.857 u_confreg/u_int_ctrl_n_17 SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[14]/C Slack: inf Source: dip_sw[27] (input port) Destination: u_confreg/s_rdata_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.823ns (logic 1.753ns (22.406%) route 6.070ns (77.594%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R1 0.000 0.000 r dip_sw[27] (IN) net (fo=0) 0.000 0.000 dip_sw[27] R1 IBUF (Prop_ibuf_I_O) 1.505 1.505 r dip_sw_IBUF[27]_inst/O net (fo=1, routed) 4.956 6.461 u_confreg/dip_sw_IBUF[27] SLICE_X61Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.585 r u_confreg/s_rdata[27]_i_4/O net (fo=1, routed) 1.114 7.699 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 SLICE_X50Y137 LUT6 (Prop_lut6_I4_O) 0.124 7.823 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O net (fo=1, routed) 0.000 7.823 u_confreg/u_int_ctrl_n_4 SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[27]/C Slack: inf Source: dip_sw[15] (input port) Destination: u_confreg/s_rdata_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.701ns (logic 1.742ns (22.623%) route 5.959ns (77.377%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L2 0.000 0.000 r dip_sw[15] (IN) net (fo=0) 0.000 0.000 dip_sw[15] L2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[15]_inst/O net (fo=1, routed) 5.004 6.498 u_confreg/dip_sw_IBUF[15] SLICE_X58Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.622 r u_confreg/s_rdata[15]_i_4/O net (fo=1, routed) 0.955 7.577 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 SLICE_X49Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.701 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O net (fo=1, routed) 0.000 7.701 u_confreg/u_int_ctrl_n_16 SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[15]/C Slack: inf Source: dip_sw[7] (input port) Destination: u_confreg/s_rdata_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.567ns (logic 1.719ns (22.721%) route 5.848ns (77.279%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.286ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N6 0.000 0.000 r dip_sw[7] (IN) net (fo=0) 0.000 0.000 dip_sw[7] N6 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[7]_inst/O net (fo=1, routed) 4.586 6.058 u_confreg/dip_sw_IBUF[7] SLICE_X66Y139 LUT5 (Prop_lut5_I4_O) 0.124 6.182 r u_confreg/s_rdata[7]_i_4/O net (fo=1, routed) 1.261 7.443 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 SLICE_X56Y131 LUT6 (Prop_lut6_I4_O) 0.124 7.567 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O net (fo=1, routed) 0.000 7.567 u_confreg/u_int_ctrl_n_24 SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.542 -2.286 u_confreg/sys_clk SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[7]/C Slack: inf Source: dip_sw[12] (input port) Destination: u_confreg/s_rdata_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.550ns (logic 1.717ns (22.743%) route 5.833ns (77.257%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M5 0.000 0.000 r dip_sw[12] (IN) net (fo=0) 0.000 0.000 dip_sw[12] M5 IBUF (Prop_ibuf_I_O) 1.469 1.469 r dip_sw_IBUF[12]_inst/O net (fo=1, routed) 4.809 6.278 u_confreg/dip_sw_IBUF[12] SLICE_X59Y137 LUT5 (Prop_lut5_I4_O) 0.124 6.402 r u_confreg/s_rdata[12]_i_4/O net (fo=1, routed) 1.024 7.426 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.550 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O net (fo=1, routed) 0.000 7.550 u_confreg/u_int_ctrl_n_19 SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[12]/C Slack: inf Source: dip_sw[16] (input port) Destination: u_confreg/s_rdata_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.532ns (logic 1.748ns (23.209%) route 5.784ns (76.791%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K2 0.000 0.000 r dip_sw[16] (IN) net (fo=0) 0.000 0.000 dip_sw[16] K2 IBUF (Prop_ibuf_I_O) 1.500 1.500 r dip_sw_IBUF[16]_inst/O net (fo=1, routed) 4.874 6.374 u_confreg/dip_sw_IBUF[16] SLICE_X62Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.498 r u_confreg/s_rdata[16]_i_4/O net (fo=1, routed) 0.910 7.408 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.532 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O net (fo=1, routed) 0.000 7.532 u_confreg/u_int_ctrl_n_15 SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[16]/C Slack: inf Source: dip_sw[25] (input port) Destination: u_confreg/s_rdata_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.498ns (logic 1.737ns (23.169%) route 5.761ns (76.831%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R3 0.000 0.000 r dip_sw[25] (IN) net (fo=0) 0.000 0.000 dip_sw[25] R3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[25]_inst/O net (fo=1, routed) 5.036 6.525 u_confreg/dip_sw_IBUF[25] SLICE_X55Y138 LUT5 (Prop_lut5_I4_O) 0.124 6.649 r u_confreg/s_rdata[25]_i_4/O net (fo=1, routed) 0.725 7.374 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 SLICE_X51Y138 LUT6 (Prop_lut6_I4_O) 0.124 7.498 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O net (fo=1, routed) 0.000 7.498 u_confreg/u_int_ctrl_n_6 SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[25]/C Slack: inf Source: dip_sw[24] (input port) Destination: u_confreg/s_rdata_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.497ns (logic 1.714ns (22.868%) route 5.783ns (77.132%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P5 0.000 0.000 r dip_sw[24] (IN) net (fo=0) 0.000 0.000 dip_sw[24] P5 IBUF (Prop_ibuf_I_O) 1.466 1.466 r dip_sw_IBUF[24]_inst/O net (fo=1, routed) 5.182 6.648 u_confreg/dip_sw_IBUF[24] SLICE_X55Y139 LUT5 (Prop_lut5_I4_O) 0.124 6.772 r u_confreg/s_rdata[24]_i_4/O net (fo=1, routed) 0.601 7.373 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 SLICE_X52Y139 LUT6 (Prop_lut6_I4_O) 0.124 7.497 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O net (fo=1, routed) 0.000 7.497 u_confreg/u_int_ctrl_n_7 SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.551 -2.277 u_confreg/sys_clk SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[24]/C Slack: inf Source: dip_sw[4] (input port) Destination: u_confreg/s_rdata_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.485ns (logic 1.736ns (23.197%) route 5.748ns (76.803%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.281ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P4 0.000 0.000 r dip_sw[4] (IN) net (fo=0) 0.000 0.000 dip_sw[4] P4 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[4]_inst/O net (fo=1, routed) 4.844 6.332 u_confreg/dip_sw_IBUF[4] SLICE_X63Y134 LUT5 (Prop_lut5_I4_O) 0.124 6.456 r u_confreg/s_rdata[4]_i_4/O net (fo=1, routed) 0.904 7.361 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 SLICE_X55Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.485 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O net (fo=1, routed) 0.000 7.485 u_confreg/u_int_ctrl_n_27 SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.547 -2.281 u_confreg/sys_clk SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[4]/C Slack: inf Source: dip_sw[8] (input port) Destination: u_confreg/s_rdata_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.481ns (logic 1.724ns (23.040%) route 5.758ns (76.960%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.286ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M6 0.000 0.000 r dip_sw[8] (IN) net (fo=0) 0.000 0.000 dip_sw[8] M6 IBUF (Prop_ibuf_I_O) 1.476 1.476 r dip_sw_IBUF[8]_inst/O net (fo=1, routed) 4.998 6.474 u_confreg/dip_sw_IBUF[8] SLICE_X61Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.598 r u_confreg/s_rdata[8]_i_4/O net (fo=1, routed) 0.760 7.357 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 SLICE_X59Y131 LUT6 (Prop_lut6_I4_O) 0.124 7.481 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O net (fo=1, routed) 0.000 7.481 u_confreg/u_int_ctrl_n_23 SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.542 -2.286 u_confreg/sys_clk SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[8]/C Slack: inf Source: dip_sw[20] (input port) Destination: u_confreg/s_rdata_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.437ns (logic 1.723ns (23.170%) route 5.714ns (76.830%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M4 0.000 0.000 r dip_sw[20] (IN) net (fo=0) 0.000 0.000 dip_sw[20] M4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r dip_sw_IBUF[20]_inst/O net (fo=1, routed) 4.743 6.219 u_confreg/dip_sw_IBUF[20] SLICE_X54Y140 LUT5 (Prop_lut5_I4_O) 0.124 6.343 r u_confreg/s_rdata[20]_i_4/O net (fo=1, routed) 0.970 7.313 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 SLICE_X50Y138 LUT6 (Prop_lut6_I4_O) 0.124 7.437 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O net (fo=1, routed) 0.000 7.437 u_confreg/u_int_ctrl_n_11 SLICE_X50Y138 FDRE r u_confreg/s_rdata_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk SLICE_X50Y138 FDRE r u_confreg/s_rdata_reg[20]/C Slack: inf Source: dip_sw[6] (input port) Destination: u_confreg/s_rdata_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.429ns (logic 1.736ns (23.368%) route 5.693ns (76.632%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L3 0.000 0.000 r dip_sw[6] (IN) net (fo=0) 0.000 0.000 dip_sw[6] L3 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[6]_inst/O net (fo=1, routed) 4.696 6.184 u_confreg/dip_sw_IBUF[6] SLICE_X65Y134 LUT5 (Prop_lut5_I4_O) 0.124 6.308 r u_confreg/s_rdata[6]_i_4/O net (fo=1, routed) 0.997 7.305 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 SLICE_X57Y132 LUT6 (Prop_lut6_I4_O) 0.124 7.429 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O net (fo=1, routed) 0.000 7.429 u_confreg/u_int_ctrl_n_25 SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.544 -2.284 u_confreg/sys_clk SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[6]/C Slack: inf Source: dip_sw[13] (input port) Destination: u_confreg/s_rdata_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.400ns (logic 1.734ns (23.431%) route 5.666ns (76.569%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.283ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K3 0.000 0.000 r dip_sw[13] (IN) net (fo=0) 0.000 0.000 dip_sw[13] K3 IBUF (Prop_ibuf_I_O) 1.486 1.486 r dip_sw_IBUF[13]_inst/O net (fo=1, routed) 5.048 6.534 u_confreg/dip_sw_IBUF[13] SLICE_X58Y139 LUT5 (Prop_lut5_I4_O) 0.124 6.658 r u_confreg/s_rdata[13]_i_4/O net (fo=1, routed) 0.618 7.276 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.124 7.400 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O net (fo=1, routed) 0.000 7.400 u_confreg/u_int_ctrl_n_18 SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.545 -2.283 u_confreg/sys_clk SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[13]/C Slack: inf Source: dip_sw[21] (input port) Destination: u_confreg/s_rdata_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.324ns (logic 1.736ns (23.706%) route 5.588ns (76.294%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N2 0.000 0.000 r dip_sw[21] (IN) net (fo=0) 0.000 0.000 dip_sw[21] N2 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[21]_inst/O net (fo=1, routed) 5.103 6.592 u_confreg/dip_sw_IBUF[21] SLICE_X57Y138 LUT5 (Prop_lut5_I4_O) 0.124 6.716 r u_confreg/s_rdata[21]_i_4/O net (fo=1, routed) 0.484 7.200 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 SLICE_X51Y138 LUT6 (Prop_lut6_I4_O) 0.124 7.324 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O net (fo=1, routed) 0.000 7.324 u_confreg/u_int_ctrl_n_10 SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[21]/C Slack: inf Source: dip_sw[2] (input port) Destination: u_confreg/s_rdata_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.267ns (logic 1.743ns (23.989%) route 5.524ns (76.011%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.286ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M2 0.000 0.000 r dip_sw[2] (IN) net (fo=0) 0.000 0.000 dip_sw[2] M2 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[2]_inst/O net (fo=1, routed) 4.493 5.988 u_confreg/dip_sw_IBUF[2] SLICE_X66Y131 LUT5 (Prop_lut5_I4_O) 0.124 6.112 r u_confreg/s_rdata[2]_i_4/O net (fo=1, routed) 1.030 7.143 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 SLICE_X56Y131 LUT6 (Prop_lut6_I4_O) 0.124 7.267 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O net (fo=1, routed) 0.000 7.267 u_confreg/u_int_ctrl_n_29 SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.542 -2.286 u_confreg/sys_clk SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[2]/C Slack: inf Source: dip_sw[0] (input port) Destination: u_confreg/s_rdata_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.201ns (logic 1.743ns (24.206%) route 5.458ns (75.794%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.283ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T3 0.000 0.000 r dip_sw[0] (IN) net (fo=0) 0.000 0.000 dip_sw[0] T3 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[0]_inst/O net (fo=1, routed) 4.700 6.196 u_confreg/dip_sw_IBUF[0] SLICE_X62Y133 LUT5 (Prop_lut5_I4_O) 0.124 6.320 r u_confreg/s_rdata[0]_i_4/O net (fo=1, routed) 0.758 7.077 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 SLICE_X60Y133 LUT6 (Prop_lut6_I4_O) 0.124 7.201 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O net (fo=1, routed) 0.000 7.201 u_confreg/u_int_ctrl_n_31 SLICE_X60Y133 FDRE r u_confreg/s_rdata_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.545 -2.283 u_confreg/sys_clk SLICE_X60Y133 FDRE r u_confreg/s_rdata_reg[0]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.187ns (logic 1.952ns (27.163%) route 5.235ns (72.837%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1) Clock Path Skew: -2.306ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 5.067 6.541 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X79Y136 LUT2 (Prop_lut2_I1_O) 0.152 6.693 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O net (fo=2, routed) 0.169 6.861 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 SLICE_X79Y136 LUT6 (Prop_lut6_I2_O) 0.326 7.187 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O net (fo=1, routed) 0.000 7.187 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.522 -2.306 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C Slack: inf Source: dip_sw[5] (input port) Destination: u_confreg/s_rdata_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.162ns (logic 1.718ns (23.993%) route 5.444ns (76.007%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L5 0.000 0.000 r dip_sw[5] (IN) net (fo=0) 0.000 0.000 dip_sw[5] L5 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[5]_inst/O net (fo=1, routed) 4.578 6.048 u_confreg/dip_sw_IBUF[5] SLICE_X66Y139 LUT5 (Prop_lut5_I4_O) 0.124 6.172 r u_confreg/s_rdata[5]_i_4/O net (fo=1, routed) 0.866 7.038 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 SLICE_X57Y137 LUT6 (Prop_lut6_I4_O) 0.124 7.162 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O net (fo=1, routed) 0.000 7.162 u_confreg/u_int_ctrl_n_26 SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.548 -2.280 u_confreg/sys_clk SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[5]/C Slack: inf Source: dip_sw[18] (input port) Destination: u_confreg/s_rdata_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.118ns (logic 1.737ns (24.404%) route 5.381ns (75.596%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.285ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.285ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N3 0.000 0.000 r dip_sw[18] (IN) net (fo=0) 0.000 0.000 dip_sw[18] N3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[18]_inst/O net (fo=1, routed) 4.773 6.262 u_confreg/dip_sw_IBUF[18] SLICE_X61Y129 LUT5 (Prop_lut5_I4_O) 0.124 6.386 r u_confreg/s_rdata[18]_i_4/O net (fo=1, routed) 0.608 6.994 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 SLICE_X48Y129 LUT6 (Prop_lut6_I4_O) 0.124 7.118 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O net (fo=1, routed) 0.000 7.118 u_confreg/u_int_ctrl_n_13 SLICE_X48Y129 FDRE r u_confreg/s_rdata_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.543 -2.285 u_confreg/sys_clk SLICE_X48Y129 FDRE r u_confreg/s_rdata_reg[18]/C Slack: inf Source: dip_sw[3] (input port) Destination: u_confreg/s_rdata_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.054ns (logic 1.752ns (24.843%) route 5.301ns (75.157%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.286ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P1 0.000 0.000 r dip_sw[3] (IN) net (fo=0) 0.000 0.000 dip_sw[3] P1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[3]_inst/O net (fo=1, routed) 4.499 6.003 u_confreg/dip_sw_IBUF[3] SLICE_X63Y131 LUT5 (Prop_lut5_I4_O) 0.124 6.127 r u_confreg/s_rdata[3]_i_4/O net (fo=1, routed) 0.802 6.930 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 SLICE_X59Y131 LUT6 (Prop_lut6_I4_O) 0.124 7.054 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O net (fo=1, routed) 0.000 7.054 u_confreg/u_int_ctrl_n_28 SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.542 -2.286 u_confreg/sys_clk SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[3]/C Slack: inf Source: dip_sw[10] (input port) Destination: u_confreg/s_rdata_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.934ns (logic 1.720ns (24.809%) route 5.214ns (75.191%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.281ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M7 0.000 0.000 r dip_sw[10] (IN) net (fo=0) 0.000 0.000 dip_sw[10] M7 IBUF (Prop_ibuf_I_O) 1.472 1.472 r dip_sw_IBUF[10]_inst/O net (fo=1, routed) 3.839 5.312 u_confreg/dip_sw_IBUF[10] SLICE_X62Y139 LUT5 (Prop_lut5_I4_O) 0.124 5.436 r u_confreg/s_rdata[10]_i_4/O net (fo=1, routed) 1.374 6.810 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 SLICE_X55Y135 LUT6 (Prop_lut6_I4_O) 0.124 6.934 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O net (fo=1, routed) 0.000 6.934 u_confreg/u_int_ctrl_n_21 SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.547 -2.281 u_confreg/sys_clk SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[10]/C Slack: inf Source: dip_sw[26] (input port) Destination: u_confreg/s_rdata_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.933ns (logic 1.757ns (25.349%) route 5.175ns (74.651%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T4 0.000 0.000 r dip_sw[26] (IN) net (fo=0) 0.000 0.000 dip_sw[26] T4 IBUF (Prop_ibuf_I_O) 1.509 1.509 r dip_sw_IBUF[26]_inst/O net (fo=1, routed) 4.385 5.894 u_confreg/dip_sw_IBUF[26] SLICE_X52Y137 LUT5 (Prop_lut5_I4_O) 0.124 6.018 r u_confreg/s_rdata[26]_i_4/O net (fo=1, routed) 0.790 6.809 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 SLICE_X50Y137 LUT6 (Prop_lut6_I4_O) 0.124 6.933 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O net (fo=1, routed) 0.000 6.933 u_confreg/u_int_ctrl_n_5 SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[26]/C Slack: inf Source: dip_sw[1] (input port) Destination: u_confreg/s_rdata_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.900ns (logic 1.746ns (25.302%) route 5.154ns (74.698%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.283ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J3 0.000 0.000 r dip_sw[1] (IN) net (fo=0) 0.000 0.000 dip_sw[1] J3 IBUF (Prop_ibuf_I_O) 1.498 1.498 r dip_sw_IBUF[1]_inst/O net (fo=1, routed) 4.204 5.702 u_confreg/dip_sw_IBUF[1] SLICE_X66Y141 LUT5 (Prop_lut5_I4_O) 0.124 5.826 r u_confreg/s_rdata[1]_i_4/O net (fo=1, routed) 0.950 6.776 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.124 6.900 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O net (fo=1, routed) 0.000 6.900 u_confreg/u_int_ctrl_n_30 SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.545 -2.283 u_confreg/sys_clk SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[1]/C Slack: inf Source: dip_sw[30] (input port) Destination: u_confreg/s_rdata_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.720ns (logic 1.707ns (25.404%) route 5.013ns (74.596%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R6 0.000 0.000 r dip_sw[30] (IN) net (fo=0) 0.000 0.000 dip_sw[30] R6 IBUF (Prop_ibuf_I_O) 1.459 1.459 r dip_sw_IBUF[30]_inst/O net (fo=1, routed) 4.861 6.320 u_confreg/dip_sw_IBUF[30] SLICE_X57Y140 LUT5 (Prop_lut5_I4_O) 0.124 6.444 r u_confreg/s_rdata[30]_i_4/O net (fo=1, routed) 0.151 6.596 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 SLICE_X57Y140 LUT6 (Prop_lut6_I4_O) 0.124 6.720 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O net (fo=1, routed) 0.000 6.720 u_confreg/u_int_ctrl_n_1 SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[30]/C Slack: inf Source: dip_sw[9] (input port) Destination: u_confreg/s_rdata_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.697ns (logic 1.718ns (25.648%) route 4.980ns (74.352%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N7 0.000 0.000 r dip_sw[9] (IN) net (fo=0) 0.000 0.000 dip_sw[9] N7 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[9]_inst/O net (fo=1, routed) 4.246 5.716 u_confreg/dip_sw_IBUF[9] SLICE_X58Y135 LUT5 (Prop_lut5_I4_O) 0.124 5.840 r u_confreg/s_rdata[9]_i_4/O net (fo=1, routed) 0.733 6.573 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 SLICE_X57Y132 LUT6 (Prop_lut6_I4_O) 0.124 6.697 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O net (fo=1, routed) 0.000 6.697 u_confreg/u_int_ctrl_n_22 SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.544 -2.284 u_confreg/sys_clk SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[9]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.665ns (logic 1.598ns (23.982%) route 5.067ns (76.018%)) Logic Levels: 2 (IBUF=1 LUT5=1) Clock Path Skew: -2.306ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 r UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 5.067 6.541 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X79Y136 LUT5 (Prop_lut5_I0_O) 0.124 6.665 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O net (fo=1, routed) 0.000 6.665 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.522 -2.306 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C Slack: inf Source: dip_sw[28] (input port) Destination: u_confreg/s_rdata_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.630ns (logic 1.716ns (25.877%) route 4.914ns (74.123%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R5 0.000 0.000 r dip_sw[28] (IN) net (fo=0) 0.000 0.000 dip_sw[28] R5 IBUF (Prop_ibuf_I_O) 1.468 1.468 r dip_sw_IBUF[28]_inst/O net (fo=1, routed) 3.943 5.410 u_confreg/dip_sw_IBUF[28] SLICE_X59Y139 LUT5 (Prop_lut5_I4_O) 0.124 5.534 r u_confreg/s_rdata[28]_i_4/O net (fo=1, routed) 0.971 6.506 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 SLICE_X52Y139 LUT6 (Prop_lut6_I4_O) 0.124 6.630 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O net (fo=1, routed) 0.000 6.630 u_confreg/u_int_ctrl_n_3 SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.551 -2.277 u_confreg/sys_clk SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[28]/C Slack: inf Source: touch_btn[3] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.594ns (logic 1.513ns (22.943%) route 5.081ns (77.057%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -2.286ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- U2 0.000 0.000 r touch_btn[3] (IN) net (fo=0) 0.000 0.000 touch_btn[3] U2 IBUF (Prop_ibuf_I_O) 1.513 1.513 r touch_btn_IBUF[3]_inst/O net (fo=1, routed) 5.081 6.594 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] SLICE_X60Y131 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.542 -2.286 u_confreg/u_int_ctrl/sys_clk SLICE_X60Y131 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C Slack: inf Source: dip_sw[17] (input port) Destination: u_confreg/s_rdata_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.534ns (logic 1.752ns (26.817%) route 4.781ns (73.183%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K1 0.000 0.000 r dip_sw[17] (IN) net (fo=0) 0.000 0.000 dip_sw[17] K1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[17]_inst/O net (fo=1, routed) 4.040 5.544 u_confreg/dip_sw_IBUF[17] SLICE_X56Y136 LUT5 (Prop_lut5_I4_O) 0.124 5.668 r u_confreg/s_rdata[17]_i_4/O net (fo=1, routed) 0.742 6.410 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 SLICE_X49Y136 LUT6 (Prop_lut6_I4_O) 0.124 6.534 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O net (fo=1, routed) 0.000 6.534 u_confreg/u_int_ctrl_n_14 SLICE_X49Y136 FDRE r u_confreg/s_rdata_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk SLICE_X49Y136 FDRE r u_confreg/s_rdata_reg[17]/C Slack: inf Source: touch_btn[0] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.451ns (logic 1.499ns (23.235%) route 4.952ns (76.765%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -2.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T2 0.000 0.000 r touch_btn[0] (IN) net (fo=0) 0.000 0.000 touch_btn[0] T2 IBUF (Prop_ibuf_I_O) 1.499 1.499 r touch_btn_IBUF[0]_inst/O net (fo=1, routed) 4.952 6.451 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] SLICE_X60Y132 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.544 -2.284 u_confreg/u_int_ctrl/sys_clk SLICE_X60Y132 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C Slack: inf Source: dip_sw[11] (input port) Destination: u_confreg/s_rdata_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.415ns (logic 1.719ns (26.800%) route 4.696ns (73.200%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.283ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L7 0.000 0.000 r dip_sw[11] (IN) net (fo=0) 0.000 0.000 dip_sw[11] L7 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[11]_inst/O net (fo=1, routed) 4.076 5.548 u_confreg/dip_sw_IBUF[11] SLICE_X60Y139 LUT5 (Prop_lut5_I4_O) 0.124 5.672 r u_confreg/s_rdata[11]_i_4/O net (fo=1, routed) 0.619 6.291 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.124 6.415 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O net (fo=1, routed) 0.000 6.415 u_confreg/u_int_ctrl_n_20 SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.545 -2.283 u_confreg/sys_clk SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[11]/C Slack: inf Source: UART_RX (input port) Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.183ns (logic 1.590ns (25.709%) route 4.593ns (74.291%)) Logic Levels: 2 (IBUF=1 LUT4=1) Clock Path Skew: -2.297ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.297ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J20 0.000 0.000 r UART_RX (INOUT) net (fo=1, unset) 0.000 0.000 UART_RX_IOBUF_inst/IO J20 IBUF (Prop_ibuf_I_O) 1.466 1.466 r UART_RX_IOBUF_inst/IBUF/O net (fo=1, routed) 4.593 6.059 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_RX_IBUF SLICE_X77Y137 LUT4 (Prop_lut4_I3_O) 0.124 6.183 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O net (fo=1, routed) 0.000 6.183 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i SLICE_X77Y137 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.531 -2.297 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk SLICE_X77Y137 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C Slack: inf Source: dip_sw[31] (input port) Destination: u_confreg/s_rdata_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.133ns (logic 1.742ns (28.400%) route 4.391ns (71.600%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R2 0.000 0.000 r dip_sw[31] (IN) net (fo=0) 0.000 0.000 dip_sw[31] R2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[31]_inst/O net (fo=1, routed) 4.089 5.582 u_confreg/dip_sw_IBUF[31] SLICE_X59Y137 LUT5 (Prop_lut5_I4_O) 0.124 5.706 r u_confreg/s_rdata[31]_i_6/O net (fo=1, routed) 0.302 6.009 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 SLICE_X57Y137 LUT6 (Prop_lut6_I4_O) 0.124 6.133 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O net (fo=1, routed) 0.000 6.133 u_confreg/u_int_ctrl_n_0 SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.548 -2.280 u_confreg/sys_clk SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[31]/C Slack: inf Source: dip_sw[23] (input port) Destination: u_confreg/s_rdata_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.019ns (logic 1.766ns (29.348%) route 4.253ns (70.652%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N1 0.000 0.000 r dip_sw[23] (IN) net (fo=0) 0.000 0.000 dip_sw[23] N1 IBUF (Prop_ibuf_I_O) 1.518 1.518 r dip_sw_IBUF[23]_inst/O net (fo=1, routed) 3.538 5.057 u_confreg/dip_sw_IBUF[23] SLICE_X51Y139 LUT5 (Prop_lut5_I4_O) 0.124 5.181 r u_confreg/s_rdata[23]_i_4/O net (fo=1, routed) 0.714 5.895 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 SLICE_X50Y139 LUT6 (Prop_lut6_I4_O) 0.124 6.019 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O net (fo=1, routed) 0.000 6.019 u_confreg/u_int_ctrl_n_8 SLICE_X50Y139 FDRE r u_confreg/s_rdata_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.551 -2.277 u_confreg/sys_clk SLICE_X50Y139 FDRE r u_confreg/s_rdata_reg[23]/C Slack: inf Source: touch_btn[2] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.014ns (logic 1.487ns (24.725%) route 4.527ns (75.275%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -2.288ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.288ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P3 0.000 0.000 r touch_btn[2] (IN) net (fo=0) 0.000 0.000 touch_btn[2] P3 IBUF (Prop_ibuf_I_O) 1.487 1.487 r touch_btn_IBUF[2]_inst/O net (fo=1, routed) 4.527 6.014 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.540 -2.288 u_confreg/u_int_ctrl/sys_clk SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.898ns (logic 1.598ns (27.102%) route 4.299ns (72.898%)) Logic Levels: 2 (IBUF=1 LUT5=1) Clock Path Skew: -2.297ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.297ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 4.299 5.774 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF SLICE_X77Y137 LUT5 (Prop_lut5_I2_O) 0.124 5.898 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O net (fo=1, routed) 0.000 5.898 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 SLICE_X77Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.531 -2.297 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X77Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C Slack: inf Source: touch_btn[1] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.747ns (logic 1.515ns (26.361%) route 4.232ns (73.639%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -2.294ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.294ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M1 0.000 0.000 r touch_btn[1] (IN) net (fo=0) 0.000 0.000 touch_btn[1] M1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r touch_btn_IBUF[1]_inst/O net (fo=1, routed) 4.232 5.747 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.534 -2.294 u_confreg/u_int_ctrl/sys_clk SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED (internal pin) Destination: pll_clk.u_rst_sys/delay_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 4.333ns (logic 0.124ns (2.862%) route 4.209ns (97.138%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED net (fo=1, routed) 3.680 3.680 pll_clk.u_rst_sys/locked SLICE_X22Y139 LUT1 (Prop_lut1_I0_O) 0.124 3.804 f pll_clk.u_rst_sys/delay[1]_i_1/O net (fo=2, routed) 0.529 4.333 pll_clk.u_rst_sys/delay[1]_i_1_n_0 SLICE_X22Y139 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.649 -2.179 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED (internal pin) Destination: pll_clk.u_rst_sys/delay_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 4.333ns (logic 0.124ns (2.862%) route 4.209ns (97.138%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED net (fo=1, routed) 3.680 3.680 pll_clk.u_rst_sys/locked SLICE_X22Y139 LUT1 (Prop_lut1_I0_O) 0.124 3.804 f pll_clk.u_rst_sys/delay[1]_i_1/O net (fo=2, routed) 0.529 4.333 pll_clk.u_rst_sys/delay[1]_i_1_n_0 SLICE_X22Y139 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.649 -2.179 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C