Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 <<<<<<< Updated upstream | Date : Fri Jul 10 04:14:53 2026 ======= | Date : Sat Jul 11 09:20:55 2026 >>>>>>> Stashed changes | Host : fedora running 64-bit unknown | Command : report_timing_summary -delay_type min -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_summary_hold_full.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 38 input ports with no input delay specified. (HIGH) UART_RX UART_TX dip_sw[0] dip_sw[10] dip_sw[11] dip_sw[12] dip_sw[13] dip_sw[14] dip_sw[15] dip_sw[16] dip_sw[17] dip_sw[18] dip_sw[19] dip_sw[1] dip_sw[20] dip_sw[21] dip_sw[22] dip_sw[23] dip_sw[24] dip_sw[25] dip_sw[26] dip_sw[27] dip_sw[28] dip_sw[29] dip_sw[2] dip_sw[30] dip_sw[31] dip_sw[3] dip_sw[4] dip_sw[5] dip_sw[6] dip_sw[7] dip_sw[8] dip_sw[9] touch_btn[0] touch_btn[1] touch_btn[2] touch_btn[3] There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 40 ports with no output delay specified. (HIGH) UART_RX UART_TX dpy0[0] dpy0[1] dpy0[2] dpy0[3] dpy0[4] dpy0[5] dpy0[6] dpy0[7] dpy1[0] dpy1[1] dpy1[2] dpy1[3] dpy1[4] dpy1[5] dpy1[6] dpy1[7] leds[0] leds[10] leds[11] leds[12] leds[13] leds[14] leds[15] leds[1] leds[2] leds[3] leds[4] leds[5] leds[6] leds[7] leds[8] leds[9] video_de video_hsync video_red[0] video_red[1] video_red[2] video_vsync There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- <<<<<<< Updated upstream 0.040 0.000 0 113333 7.000 0.000 0 42143 ======= 0.024 0.000 0 88843 5.250 0.000 0 33736 >>>>>>> Stashed changes All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk {0.000 10.000} 20.000 50.000 clkfbout_clk_pll {0.000 10.000} 20.000 50.000 <<<<<<< Updated upstream cpu_clk {0.000 15.161} 30.323 32.979 ======= cpu_clk {0.000 15.000} 30.000 33.333 mlkem_clk {0.000 6.500} 13.000 76.923 >>>>>>> Stashed changes sys_clk {0.000 10.000} 20.000 50.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk 7.000 0.000 0 1 clkfbout_clk_pll 17.845 0.000 0 3 <<<<<<< Updated upstream cpu_clk 0.049 0.000 0 17197 13.911 0.000 0 6486 sys_clk 0.040 0.000 0 69558 8.750 0.000 0 35653 ======= cpu_clk 0.040 0.000 0 17197 13.750 0.000 0 6486 mlkem_clk 0.057 0.000 0 31646 5.250 0.000 0 17274 sys_clk 0.024 0.000 0 22307 8.750 0.000 0 9972 >>>>>>> Stashed changes ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- <<<<<<< Updated upstream **async_default** cpu_clk cpu_clk 0.727 0.000 0 67 **async_default** sys_clk sys_clk 0.761 0.000 0 26511 ======= **async_default** cpu_clk cpu_clk 0.681 0.000 0 67 **async_default** mlkem_clk mlkem_clk 0.658 0.000 0 16740 **async_default** sys_clk sys_clk 0.573 0.000 0 886 >>>>>>> Stashed changes ------------------------------------------------------------------------------------------------ | User Ignored Path Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) sys_clk cpu_clk (none) sys_clk mlkem_clk (none) cpu_clk sys_clk (none) mlkem_clk sys_clk ------------------------------------------------------------------------------------------------ | Unconstrained Path Table | ------------------------ ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) clkfbout_clk_pll (none) sys_clk (none) sys_clk ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk To Clock: clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { clk } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_pll To Clock: clkfbout_clk_pll Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_pll Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkf_buf/I Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT --------------------------------------------------------------------------------------------------- From Clock: cpu_clk To Clock: cpu_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : 0 Failing Endpoints, Worst Slack 0.040ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 13.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.040ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_csr/csr_badv_reg[0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.216ns ======= Data Path Delay: 0.405ns (logic 0.186ns (45.911%) route 0.219ns (54.089%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.274ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk SLICE_X113Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/Q net (fo=3, routed) 0.219 -0.314 u_cpu/wb_stage/ms_to_ws_bus_r_reg_n_0_[0] SLICE_X107Y149 LUT6 (Prop_lut6_I2_O) 0.045 -0.269 r u_cpu/wb_stage/csr_badv[0]_i_1/O net (fo=1, routed) 0.000 -0.269 u_cpu/u_csr/csr_badv_reg[31]_4[0] SLICE_X107Y149 FDRE r u_cpu/u_csr/csr_badv_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.863 -0.445 u_cpu/u_csr/cpu_clk SLICE_X107Y149 FDRE r u_cpu/u_csr/csr_badv_reg[0]/C clock pessimism 0.045 -0.400 SLICE_X107Y149 FDRE (Hold_fdre_C_D) 0.091 -0.309 u_cpu/u_csr/csr_badv_reg[0] ------------------------------------------------------------------- required time 0.309 arrival time -0.269 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.049ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns Clock Pessimism Removal (CPR): 0.213ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.650 -0.612 u_cpu/u_csr/cpu_clk SLICE_X97Y50 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.471 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q net (fo=4, routed) 0.068 -0.403 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 SLICE_X96Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.596 -0.667 u_cpu/u_csr/cpu_clk SLICE_X117Y149 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q net (fo=4, routed) 0.068 -0.458 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 SLICE_X116Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.925 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/WCLK SLICE_X96Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/CLK clock pessimism -0.216 -0.599 SLICE_X96Y50 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.452 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA ------------------------------------------------------------------- required time 0.452 arrival time -0.403 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.051ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.867 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK SLICE_X116Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/CLK clock pessimism -0.213 -0.654 SLICE_X116Y149 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA ------------------------------------------------------------------- required time 0.507 arrival time -0.458 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.058ns (arrival time - required time) Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.400ns (logic 0.164ns (40.951%) route 0.236ns (59.049%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.453ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_cpu/mem_stage/cpu_clk SLICE_X98Y152 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y152 FDRE (Prop_fdre_C_Q) 0.164 -0.521 r u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/Q net (fo=2, routed) 0.236 -0.284 u_cpu/wb_stage/ms_to_ws_bus[78] SLICE_X99Y148 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.855 -0.453 u_cpu/wb_stage/cpu_clk SLICE_X99Y148 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/C clock pessimism 0.045 -0.408 SLICE_X99Y148 FDRE (Hold_fdre_C_D) 0.066 -0.342 u_cpu/wb_stage/ms_to_ws_bus_r_reg[114] ------------------------------------------------------------------- required time 0.342 arrival time -0.284 ------------------------------------------------------------------- slack 0.058 Slack (MET) : 0.061ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) >>>>>>> Stashed changes Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.211ns (logic 0.141ns (66.741%) route 0.070ns (33.259%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) <<<<<<< Updated upstream Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.647 -0.615 u_cpu/u_csr/cpu_clk SLICE_X67Y50 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q net (fo=4, routed) 0.070 -0.404 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.922 -0.386 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/CLK clock pessimism -0.216 -0.602 SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.455 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA ------------------------------------------------------------------- required time 0.455 arrival time -0.404 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.084ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.349ns (logic 0.164ns (46.999%) route 0.185ns (53.001%)) Logic Levels: 0 Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.506ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.757 -0.506 u_cpu/u_csr/cpu_clk SLICE_X40Y49 FDRE r u_cpu/u_csr/csr_tlbidx_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 r u_cpu/u_csr/csr_tlbidx_reg[26]/Q net (fo=33, routed) 0.185 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] SLICE_X39Y52 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X39Y52 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/C clock pessimism 0.037 -0.310 SLICE_X39Y52 FDRE (Hold_fdre_C_D) 0.070 -0.240 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2] ------------------------------------------------------------------- required time 0.240 arrival time -0.157 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_cpu/axi_bridge/araddr_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.339ns (logic 0.128ns (37.707%) route 0.211ns (62.293%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.727 -0.536 u_cpu/axi_bridge/cpu_clk SLICE_X47Y47 FDRE r u_cpu/axi_bridge/araddr_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y47 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[5]/Q net (fo=1, routed) 0.211 -0.196 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIC1 SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.930 -0.378 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK clock pessimism 0.037 -0.341 SLICE_X44Y51 RAMD32 (Hold_ramd32_CLK_I) 0.061 -0.280 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1 ------------------------------------------------------------------- required time 0.280 arrival time -0.196 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_cpu/axi_bridge/wstrb_reg[2]/C (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.187ns (logic 0.128ns (68.397%) route 0.059ns (31.603%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.496ns Clock Pessimism Removal (CPR): 0.221ns ======= Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.683ns Clock Pessimism Removal (CPR): 0.212ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_cpu/axi_bridge/cpu_clk SLICE_X15Y41 FDSE r u_cpu/axi_bridge/wstrb_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y41 FDSE (Prop_fdse_C_Q) 0.128 -0.368 r u_cpu/axi_bridge/wstrb_reg[2]/Q net (fo=1, routed) 0.059 -0.309 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0 SLICE_X14Y41 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.580 -0.683 u_cpu/wb_stage/cpu_clk SLICE_X103Y161 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y161 FDRE (Prop_fdre_C_Q) 0.141 -0.542 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/Q net (fo=6, routed) 0.080 -0.462 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/DIA0 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X14Y41 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK clock pessimism -0.221 -0.483 SLICE_X14Y41 RAMD32 (Hold_ramd32_CLK_I) 0.090 -0.393 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC ------------------------------------------------------------------- required time 0.393 arrival time -0.309 ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/CLK clock pessimism -0.212 -0.670 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.523 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA ------------------------------------------------------------------- required time 0.523 arrival time -0.462 >>>>>>> Stashed changes ------------------------------------------------------------------- slack 0.084 <<<<<<< Updated upstream Slack (MET) : 0.086ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbidx_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.347ns (logic 0.141ns (40.688%) route 0.206ns (59.312%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.504ns Clock Pessimism Removal (CPR): -0.037ns ======= Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.355ns (logic 0.128ns (36.084%) route 0.227ns (63.916%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.586 -0.677 u_cpu/exe_stage/cpu_clk SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y150 FDRE (Prop_fdre_C_Q) 0.128 -0.549 r u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/Q net (fo=1, routed) 0.227 -0.322 u_cpu/mem_stage/D[126] SLICE_X106Y149 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.863 -0.445 u_cpu/mem_stage/cpu_clk SLICE_X106Y149 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/C clock pessimism 0.045 -0.400 SLICE_X106Y149 FDRE (Hold_fdre_C_D) 0.016 -0.384 u_cpu/mem_stage/es_to_ms_bus_r_reg[126] ------------------------------------------------------------------- required time 0.384 arrival time -0.322 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.063ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.223ns (logic 0.141ns (63.098%) route 0.082ns (36.902%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.596 -0.667 u_cpu/u_csr/cpu_clk SLICE_X121Y148 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X121Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo0_reg[26]/Q net (fo=4, routed) 0.082 -0.444 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/DIA0 SLICE_X120Y148 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.867 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/WCLK SLICE_X120Y148 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/CLK clock pessimism -0.213 -0.654 SLICE_X120Y148 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA ------------------------------------------------------------------- required time 0.507 arrival time -0.444 ------------------------------------------------------------------- slack 0.063 Slack (MET) : 0.064ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.443ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): 0.213ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.759 -0.504 u_cpu/u_csr/cpu_clk SLICE_X37Y49 FDRE r u_cpu/u_csr/csr_tlbidx_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_tlbidx_reg[27]/Q net (fo=33, routed) 0.206 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[8] SLICE_X37Y50 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.594 -0.669 u_cpu/u_csr/cpu_clk SLICE_X109Y149 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 r u_cpu/u_csr/csr_tlbelo0_reg[5]/Q net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.962 -0.346 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X37Y50 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/C clock pessimism 0.037 -0.309 SLICE_X37Y50 FDRE (Hold_fdre_C_D) 0.066 -0.243 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3] ------------------------------------------------------------------- required time 0.243 arrival time -0.157 ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.865 -0.443 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/WCLK SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/CLK clock pessimism -0.213 -0.656 SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.512 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP ------------------------------------------------------------------- required time 0.512 arrival time -0.448 ------------------------------------------------------------------- slack 0.064 Slack (MET) : 0.066ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.226ns (logic 0.141ns (62.492%) route 0.085ns (37.508%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.596 -0.667 u_cpu/u_csr/cpu_clk SLICE_X117Y147 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[14]/Q net (fo=4, routed) 0.085 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIA0 SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.867 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/WCLK SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/CLK clock pessimism -0.213 -0.654 SLICE_X116Y147 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA ------------------------------------------------------------------- required time 0.507 arrival time -0.441 ------------------------------------------------------------------- slack 0.066 Slack (MET) : 0.084ns (arrival time - required time) Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.403ns (logic 0.164ns (40.684%) route 0.239ns (59.316%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): -0.679ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.584 -0.679 u_cpu/mem_stage/cpu_clk SLICE_X98Y148 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y148 FDRE (Prop_fdre_C_Q) 0.164 -0.515 r u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/Q net (fo=2, routed) 0.239 -0.276 u_cpu/wb_stage/ms_to_ws_bus[69] SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.851 -0.457 u_cpu/wb_stage/cpu_clk SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/C clock pessimism 0.045 -0.412 SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.052 -0.360 u_cpu/wb_stage/ms_to_ws_bus_r_reg[105] ------------------------------------------------------------------- required time 0.360 arrival time -0.276 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.085ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.479ns (logic 0.141ns (29.406%) route 0.338ns (70.594%)) Logic Levels: 0 Clock Path Skew: 0.275ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.444ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.589 -0.674 u_cpu/u_csr/cpu_clk SLICE_X115Y150 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q net (fo=4, routed) 0.338 -0.194 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 SLICE_X112Y141 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.864 -0.444 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/WCLK SLICE_X112Y141 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/CLK clock pessimism 0.045 -0.399 SLICE_X112Y141 RAMD32 (Hold_ramd32_CLK_I) 0.120 -0.279 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 ------------------------------------------------------------------- required time 0.279 arrival time -0.194 >>>>>>> Stashed changes ------------------------------------------------------------------- slack 0.086 <<<<<<< Updated upstream Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns ======= Slack (MET) : 0.089ns (arrival time - required time) Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.415ns (logic 0.141ns (33.953%) route 0.274ns (66.047%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): -0.679ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.584 -0.679 u_cpu/mem_stage/cpu_clk SLICE_X97Y148 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.538 r u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/Q net (fo=2, routed) 0.274 -0.264 u_cpu/wb_stage/ms_to_ws_bus[68] SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.851 -0.457 u_cpu/wb_stage/cpu_clk SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/C clock pessimism 0.045 -0.412 SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.059 -0.353 u_cpu/wb_stage/ms_to_ws_bus_r_reg[104] ------------------------------------------------------------------- required time 0.353 arrival time -0.264 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.091ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.443ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.594 -0.669 u_cpu/u_csr/cpu_clk SLICE_X109Y149 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 r u_cpu/u_csr/csr_tlbelo0_reg[5]/Q net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.865 -0.443 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/WCLK SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/CLK clock pessimism -0.213 -0.656 SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) 0.117 -0.539 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP ------------------------------------------------------------------- required time 0.539 arrival time -0.448 ------------------------------------------------------------------- slack 0.091 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_csr/csr_cntc_reg[1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.802%) route 0.302ns (68.198%)) Logic Levels: 0 Clock Path Skew: 0.278ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.684ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.579 -0.684 u_cpu/wb_stage/cpu_clk SLICE_X101Y154 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y154 FDRE (Prop_fdre_C_Q) 0.141 -0.543 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/Q net (fo=21, routed) 0.302 -0.241 u_cpu/u_csr/wr_csr_data[1] SLICE_X101Y149 FDRE r u_cpu/u_csr/csr_cntc_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.857 -0.451 u_cpu/u_csr/cpu_clk SLICE_X101Y149 FDRE r u_cpu/u_csr/csr_cntc_reg[1]/C clock pessimism 0.045 -0.406 SLICE_X101Y149 FDRE (Hold_fdre_C_D) 0.070 -0.336 u_cpu/u_csr/csr_cntc_reg[1] ------------------------------------------------------------------- required time 0.336 arrival time -0.241 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.096ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.281ns (logic 0.141ns (50.221%) route 0.140ns (49.779%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.447ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.589 -0.674 u_cpu/u_csr/cpu_clk SLICE_X115Y150 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q net (fo=4, routed) 0.140 -0.393 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/DIA0 SLICE_X116Y151 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.861 -0.447 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/WCLK SLICE_X116Y151 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/CLK clock pessimism -0.189 -0.636 SLICE_X116Y151 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.489 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA ------------------------------------------------------------------- required time 0.489 arrival time -0.393 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.258ns (logic 0.141ns (54.698%) route 0.117ns (45.302%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.671ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.592 -0.671 u_cpu/u_csr/cpu_clk SLICE_X106Y147 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.530 r u_cpu/u_csr/csr_tlbelo1_reg[2]/Q net (fo=7, routed) 0.117 -0.413 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/D SLICE_X104Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP/I >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA/CLK clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/CLK clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB/CLK clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/CLK clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC/CLK clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/CLK clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD/CLK clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/CLK clock pessimism -0.217 -0.523 SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.126 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.109 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.090ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[22]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.252ns (logic 0.141ns (55.979%) route 0.111ns (44.021%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.647 -0.615 u_cpu/u_csr/cpu_clk SLICE_X69Y50 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_cpu/u_csr/csr_tlbelo1_reg[22]/Q net (fo=4, routed) 0.111 -0.363 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIB0 SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.922 -0.386 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/CLK clock pessimism -0.213 -0.599 SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.453 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB ------------------------------------------------------------------- required time 0.453 arrival time -0.363 ------------------------------------------------------------------- slack 0.090 Slack (MET) : 0.090ns (arrival time - required time) Source: u_cpu/axi_bridge/araddr_reg[11]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.345ns (logic 0.128ns (37.132%) route 0.217ns (62.868%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.863 -0.445 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/WCLK SLICE_X104Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP/CLK clock pessimism -0.210 -0.655 SLICE_X104Y147 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.509 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP ------------------------------------------------------------------- required time 0.509 arrival time -0.413 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[18]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.256ns (logic 0.141ns (55.072%) route 0.115ns (44.928%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.596 -0.667 u_cpu/u_csr/cpu_clk SLICE_X118Y147 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[18]/Q net (fo=4, routed) 0.115 -0.411 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIC0 SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.867 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/WCLK SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC/CLK clock pessimism -0.210 -0.651 SLICE_X116Y147 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC ------------------------------------------------------------------- required time 0.507 arrival time -0.411 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[24]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.258ns (logic 0.141ns (54.609%) route 0.117ns (45.391%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.442ns Source Clock Delay (SCD): -0.668ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.595 -0.668 u_cpu/u_csr/cpu_clk SLICE_X114Y149 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.527 r u_cpu/u_csr/csr_tlbelo0_reg[24]/Q net (fo=4, routed) 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIC0 SLICE_X112Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.866 -0.442 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/WCLK SLICE_X112Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC/CLK clock pessimism -0.210 -0.652 SLICE_X112Y149 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.508 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC ------------------------------------------------------------------- required time 0.508 arrival time -0.410 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.727 -0.536 u_cpu/axi_bridge/cpu_clk SLICE_X47Y49 FDRE r u_cpu/axi_bridge/araddr_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[11]/Q net (fo=1, routed) 0.217 -0.191 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC1 SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMA/WADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.930 -0.378 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK clock pessimism 0.037 -0.341 SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) 0.060 -0.281 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1 ------------------------------------------------------------------- required time 0.281 arrival time -0.191 ------------------------------------------------------------------- slack 0.090 Slack (MET) : 0.093ns (arrival time - required time) Source: u_cpu/axi_bridge/araddr_reg[9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.358ns (logic 0.128ns (35.706%) route 0.230ns (64.294%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.727 -0.536 u_cpu/axi_bridge/cpu_clk SLICE_X47Y49 FDRE r u_cpu/axi_bridge/araddr_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[9]/Q net (fo=1, routed) 0.230 -0.177 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIB1 SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.930 -0.378 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK clock pessimism 0.037 -0.341 SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) 0.071 -0.270 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1 ------------------------------------------------------------------- required time 0.270 arrival time -0.177 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.094ns (arrival time - required time) Source: u_cpu/axi_bridge/awaddr_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.251ns (logic 0.141ns (56.174%) route 0.110ns (43.826%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.496ns Clock Pessimism Removal (CPR): 0.222ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_cpu/axi_bridge/cpu_clk SLICE_X17Y49 FDRE r u_cpu/axi_bridge/awaddr_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 r u_cpu/axi_bridge/awaddr_reg[10]/Q net (fo=1, routed) 0.110 -0.245 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 SLICE_X16Y49 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X16Y49 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK clock pessimism -0.222 -0.483 SLICE_X16Y49 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- required time 0.339 arrival time -0.245 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/CLK clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/CLK clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/CLK clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/CLK clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC/CLK clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/CLK clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1 ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD/CLK clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/CLK clock pessimism -0.217 -0.523 SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1 ------------------------------------------------------------------- required time 0.214 arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.366ns (logic 0.164ns (44.815%) route 0.202ns (55.185%)) Logic Levels: 0 Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.506ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.757 -0.506 u_cpu/u_csr/cpu_clk SLICE_X40Y49 FDRE r u_cpu/u_csr/csr_tlbidx_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 r u_cpu/u_csr/csr_tlbidx_reg[26]/Q net (fo=33, routed) 0.202 -0.140 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] SLICE_X37Y51 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.962 -0.346 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X37Y51 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/C clock pessimism 0.037 -0.309 SLICE_X37Y51 FDRE (Hold_fdre_C_D) 0.070 -0.239 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2] ------------------------------------------------------------------- required time 0.239 arrival time -0.140 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.287ns Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/CLK clock pessimism -0.218 -0.505 SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 ------------------------------------------------------------------- required time 0.305 arrival time -0.205 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[4]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.286ns (logic 0.141ns (49.244%) route 0.145ns (50.756%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.537ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.726 -0.537 u_cpu/u_csr/cpu_clk SLICE_X50Y43 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_cpu/u_csr/csr_tlbelo0_reg[4]/Q net (fo=7, routed) 0.145 -0.250 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/D SLICE_X48Y43 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.004 -0.304 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/WCLK SLICE_X48Y43 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/CLK clock pessimism -0.196 -0.500 SLICE_X48Y43 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.354 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP ------------------------------------------------------------------- required time 0.354 arrival time -0.250 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/axi_bridge/araddr_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.141ns (31.876%) route 0.301ns (68.124%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMA/CLK clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMA ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.727 -0.536 u_cpu/axi_bridge/cpu_clk SLICE_X47Y49 FDRE r u_cpu/axi_bridge/araddr_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_cpu/axi_bridge/araddr_reg[10]/Q net (fo=1, routed) 0.301 -0.093 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC0 SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1/WADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.930 -0.378 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK clock pessimism 0.037 -0.341 SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.197 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- required time 0.197 arrival time -0.093 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.111ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbidx_reg[24]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.376ns (logic 0.141ns (37.453%) route 0.235ns (62.547%)) Logic Levels: 0 Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.345ns Source Clock Delay (SCD): -0.504ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.759 -0.504 u_cpu/u_csr/cpu_clk SLICE_X37Y49 FDRE r u_cpu/u_csr/csr_tlbidx_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_tlbidx_reg[24]/Q net (fo=33, routed) 0.235 -0.127 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[5] SLICE_X32Y53 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.963 -0.345 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X32Y53 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/C clock pessimism 0.037 -0.308 SLICE_X32Y53 FDRE (Hold_fdre_C_D) 0.070 -0.238 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0] ------------------------------------------------------------------- required time 0.238 arrival time -0.127 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1/CLK clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1 ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMB/WADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.003 -0.305 u_cpu/btb/ras_reg_0_7_6_11/WCLK SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA/CLK clock pessimism -0.217 -0.522 SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA ------------------------------------------------------------------- required time 0.212 arrival time -0.099 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.003 -0.305 u_cpu/btb/ras_reg_0_7_6_11/WCLK SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/CLK clock pessimism -0.217 -0.522 SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1 ------------------------------------------------------------------- required time 0.212 arrival time -0.099 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMB/CLK clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMB ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1/CLK clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1 ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMC/CLK clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMC ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1/CLK clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1 ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMS32 r u_cpu/btb/ras_reg_0_7_12_17/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK SLICE_X132Y164 RAMS32 r u_cpu/btb/ras_reg_0_7_12_17/RAMD/CLK clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMD ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 SLICE_X132Y164 RAMS32 r u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK SLICE_X132Y164 RAMS32 r u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1/CLK clock pessimism -0.210 -0.661 SLICE_X132Y164 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1 ------------------------------------------------------------------- required time 0.351 arrival time -0.248 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/CLK clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1/CLK clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB/CLK clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1/CLK clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC/CLK clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1/CLK clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD/ADR4 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMS32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD/ADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK SLICE_X102Y161 RAMS32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD/CLK clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMS32 (Hold_rams32_CLK_ADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1/ADR4 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 SLICE_X102Y161 RAMS32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1/ADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK SLICE_X102Y161 RAMS32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1/CLK clock pessimism 0.045 -0.413 SLICE_X102Y161 RAMS32 (Hold_rams32_CLK_ADR4) 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1 ------------------------------------------------------------------- required time 0.213 arrival time -0.110 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.107ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[22]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.269ns (logic 0.141ns (52.500%) route 0.128ns (47.500%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.442ns Source Clock Delay (SCD): -0.668ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.595 -0.668 u_cpu/u_csr/cpu_clk SLICE_X115Y149 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.527 r u_cpu/u_csr/csr_tlbelo0_reg[22]/Q net (fo=4, routed) 0.128 -0.399 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIB0 SLICE_X112Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.866 -0.442 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/WCLK SLICE_X112Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB/CLK clock pessimism -0.210 -0.652 SLICE_X112Y149 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.506 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB ------------------------------------------------------------------- required time 0.506 arrival time -0.399 ------------------------------------------------------------------- slack 0.107 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/u_csr/timer_64_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.586 -0.677 u_cpu/u_csr/cpu_clk SLICE_X106Y151 FDRE r u_cpu/u_csr/timer_64_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/A1 SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.862 -0.446 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/WCLK SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP/CLK clock pessimism 0.045 -0.401 SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP ------------------------------------------------------------------- required time 0.092 arrival time 0.016 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/u_csr/timer_64_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.586 -0.677 u_cpu/u_csr/cpu_clk SLICE_X106Y151 FDRE r u_cpu/u_csr/timer_64_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/A1 SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.862 -0.446 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/WCLK SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP/CLK clock pessimism 0.045 -0.401 SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP ------------------------------------------------------------------- required time 0.092 arrival time 0.016 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/u_csr/timer_64_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.586 -0.677 u_cpu/u_csr/cpu_clk SLICE_X106Y151 FDRE r u_cpu/u_csr/timer_64_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/A1 SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.862 -0.446 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/WCLK SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP/CLK clock pessimism 0.045 -0.401 SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP ------------------------------------------------------------------- required time 0.092 arrival time 0.016 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/u_csr/timer_64_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.586 -0.677 u_cpu/u_csr/cpu_clk SLICE_X106Y151 FDRE r u_cpu/u_csr/timer_64_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/A1 SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.862 -0.446 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/WCLK SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP/CLK clock pessimism 0.045 -0.401 SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP ------------------------------------------------------------------- required time 0.092 arrival time 0.016 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.003 -0.305 u_cpu/btb/ras_reg_0_7_6_11/WCLK SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB/CLK clock pessimism -0.217 -0.522 SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB ------------------------------------------------------------------- required time 0.212 arrival time -0.099 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.855 -0.452 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/CLK clock pessimism -0.210 -0.662 SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMA ------------------------------------------------------------------- required time 0.352 arrival time -0.244 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.003 -0.305 u_cpu/btb/ras_reg_0_7_6_11/WCLK SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/CLK clock pessimism -0.217 -0.522 SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1 ------------------------------------------------------------------- required time 0.212 arrival time -0.099 ------------------------------------------------------------------- slack 0.113 ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.855 -0.452 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/CLK clock pessimism -0.210 -0.662 SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 ------------------------------------------------------------------- required time 0.352 arrival time -0.244 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.855 -0.452 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/CLK clock pessimism -0.210 -0.662 SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMB ------------------------------------------------------------------- required time 0.352 arrival time -0.244 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.855 -0.452 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/CLK clock pessimism -0.210 -0.662 SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 ------------------------------------------------------------------- required time 0.352 arrival time -0.244 ------------------------------------------------------------------- slack 0.108 >>>>>>> Stashed changes Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: cpu_clk Waveform(ns): { 0.000 15.000 } Period(ns): 30.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin <<<<<<< Updated upstream Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y3 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y3 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y5 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y5 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y0 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y0 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y1 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y1 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y2 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y2 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y4 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y4 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y6 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y6 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y7 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y7 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y5 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y5 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y8 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y8 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y20 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y20 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y18 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y18 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X3Y20 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X3Y20 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X3Y21 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X3Y21 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout1_buf/I Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.323 29.074 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y1 u_cpu/btb/btb_add_entry_index_r_reg[0]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X41Y3 u_cpu/btb/btb_add_entry_index_r_reg[1]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X47Y0 u_cpu/btb/btb_add_entry_index_r_reg[2]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y6 u_cpu/btb/btb_add_entry_index_r_reg[3]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y6 u_cpu/btb/btb_add_entry_index_r_reg[4]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X41Y6 u_cpu/btb/btb_add_entry_r_reg/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X5Y45 pll_clk.u_rst_cpu/delay_reg[0]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X5Y45 pll_clk.u_rst_cpu/delay_reg[1]/C Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y57 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y57 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y8 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y8 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK ======= Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y47 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y47 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y46 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y46 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y48 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y48 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y49 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y49 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y50 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y50 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y51 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y51 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y48 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y48 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y49 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y49 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y52 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y52 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y51 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y51 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y52 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y52 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y51 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y51 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X7Y50 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X7Y50 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X7Y51 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X7Y51 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X6Y48 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X6Y48 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X6Y49 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X6Y49 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 30.000 27.845 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkout1_buf/I Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.000 28.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X140Y147 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[10][9]/C Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X143Y140 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][0]/C Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X143Y140 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][10]/C Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X142Y141 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][11]/C Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X142Y141 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][12]/C Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X145Y142 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][13]/C Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X143Y143 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][14]/C Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X142Y141 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][15]/C Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.000 130.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X124Y169 u_cpu/btb/btb_target_reg_0_31_22_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X124Y169 u_cpu/btb/btb_target_reg_0_31_22_23/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- From Clock: mlkem_clk To Clock: mlkem_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : 0 Failing Endpoints, Worst Slack 0.057ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 5.250ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.057ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.276ns (logic 0.141ns (51.000%) route 0.135ns (49.000%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.593 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk SLICE_X135Y114 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X135Y114 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/Q net (fo=7, routed) 0.135 -0.394 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[6] SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.863 -0.445 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK clock pessimism -0.189 -0.634 SLICE_X136Y113 SRL16E (Hold_srl16e_CLK_D) 0.183 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.451 arrival time -0.394 ------------------------------------------------------------------- slack 0.057 Slack (MET) : 0.062ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.455ns (logic 0.164ns (36.015%) route 0.291ns (63.985%)) Logic Levels: 0 Clock Path Skew: 0.334ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.375ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.594 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X108Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/Q net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[16] SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.933 -0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/C clock pessimism 0.040 -0.335 SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.059 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16] ------------------------------------------------------------------- required time 0.276 arrival time -0.214 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.069ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.455ns (logic 0.164ns (36.017%) route 0.291ns (63.983%)) Logic Levels: 0 Clock Path Skew: 0.334ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.375ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.594 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X108Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/Q net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[17] SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.933 -0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/C clock pessimism 0.040 -0.335 SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.052 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17] ------------------------------------------------------------------- required time 0.283 arrival time -0.214 ------------------------------------------------------------------- slack 0.069 Slack (MET) : 0.085ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.281ns (logic 0.141ns (50.089%) route 0.140ns (49.911%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.211ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.593 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk SLICE_X133Y115 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/Q net (fo=6, routed) 0.140 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[7] SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.862 -0.446 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK clock pessimism -0.211 -0.657 SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) 0.183 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.474 arrival time -0.388 ------------------------------------------------------------------- slack 0.085 Slack (MET) : 0.089ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[5] RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mlkem_clk RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK clock pessimism 0.040 -0.333 RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.061 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.089ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[5] RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mlkem_clk RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK clock pessimism 0.040 -0.333 RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.061 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.103ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.233ns (logic 0.141ns (60.420%) route 0.092ns (39.580%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.211ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.593 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk SLICE_X133Y115 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/Q net (fo=7, routed) 0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[2] SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.862 -0.446 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK clock pessimism -0.211 -0.657 SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) 0.117 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.540 arrival time -0.437 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[7] RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mlkem_clk RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK clock pessimism 0.040 -0.333 RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.040 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[7] RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mlkem_clk RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK clock pessimism 0.040 -0.333 RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.040 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.303ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/Q[6] RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.005 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mlkem_clk RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKARDCLK clock pessimism -0.214 -0.517 RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg ------------------------------------------------------------------- required time 0.334 arrival time -0.223 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.303ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/Q[6] RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.005 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mlkem_clk RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKARDCLK clock pessimism -0.214 -0.517 RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg ------------------------------------------------------------------- required time 0.334 arrival time -0.223 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.373ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/Q net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[19] SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.935 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/C clock pessimism -0.229 -0.602 SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.078 -0.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19] ------------------------------------------------------------------- required time 0.524 arrival time -0.405 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.301ns (logic 0.141ns (46.859%) route 0.160ns (53.141%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X57Y91 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y91 FDRE (Prop_fdre_C_Q) 0.141 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/Q net (fo=1, routed) 0.160 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIC0 SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK clock pessimism -0.192 -0.573 SLICE_X52Y90 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.429 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC ------------------------------------------------------------------- required time 0.429 arrival time -0.309 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.410ns (logic 0.186ns (45.405%) route 0.224ns (54.595%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.198ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.442ns Source Clock Delay (SCD): -0.600ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.662 -0.600 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X118Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y99 FDCE (Prop_fdce_C_Q) 0.141 -0.459 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/Q net (fo=29, routed) 0.224 -0.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0[0] SLICE_X114Y100 LUT6 (Prop_lut6_I1_O) 0.045 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/O net (fo=1, routed) 0.000 -0.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_next0[5] SLICE_X114Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.866 -0.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X114Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/C clock pessimism 0.040 -0.402 SLICE_X114Y100 FDCE (Hold_fdce_C_D) 0.091 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5] ------------------------------------------------------------------- required time 0.311 arrival time -0.191 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) Logic Levels: 0 Clock Path Skew: 0.401ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.665ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.598 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X138Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg_0[4] RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.004 -0.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mlkem_clk RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKBWRCLK clock pessimism 0.040 -0.263 RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg ------------------------------------------------------------------- required time 0.080 arrival time 0.040 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) Logic Levels: 0 Clock Path Skew: 0.401ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.665ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.598 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X138Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg_0[4] RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.004 -0.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mlkem_clk RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKBWRCLK clock pessimism 0.040 -0.263 RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg ------------------------------------------------------------------- required time 0.080 arrival time 0.040 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.373ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/Q net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[18] SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.935 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/C clock pessimism -0.229 -0.602 SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.076 -0.526 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18] ------------------------------------------------------------------- required time 0.526 arrival time -0.405 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[1] RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mlkem_clk RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK clock pessimism 0.040 -0.333 RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.029 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[1] RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mlkem_clk RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK clock pessimism 0.040 -0.333 RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.029 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1 ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1 ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC/CLK clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1/CLK clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1 ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD/CLK clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1/CLK clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1 ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[0] SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.229 -0.612 SLICE_X59Y91 FDCE (Hold_fdce_C_D) 0.075 -0.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.537 arrival time -0.415 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[1] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.229 -0.616 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.075 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.541 arrival time -0.419 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[2] SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.229 -0.617 SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.542 arrival time -0.420 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.454ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/Q net (fo=1, routed) 0.056 -0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0 SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.854 -0.454 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C clock pessimism -0.226 -0.680 SLICE_X65Y102 FDCE (Hold_fdce_C_D) 0.075 -0.605 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg ------------------------------------------------------------------- required time 0.605 arrival time -0.483 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.124ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.200ns (logic 0.141ns (70.589%) route 0.059ns (29.411%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.059 -0.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.226 -0.613 SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.076 -0.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.537 arrival time -0.414 ------------------------------------------------------------------- slack 0.124 Slack (MET) : 0.125ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.577ns (logic 0.231ns (40.066%) route 0.346ns (59.934%)) Logic Levels: 2 (LUT3=1 LUT6=1) Clock Path Skew: 0.345ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.290ns Source Clock Delay (SCD): -0.598ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.664 -0.598 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk SLICE_X135Y50 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/C ------------------------------------------------------------------- ------------------- SLICE_X135Y50 FDCE (Prop_fdce_C_Q) 0.141 -0.457 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/Q net (fo=2, routed) 0.126 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/data31[9] SLICE_X135Y48 LUT6 (Prop_lut6_I0_O) 0.045 -0.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[753]_i_2/O net (fo=1, routed) 0.220 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[493] SLICE_X135Y48 LUT3 (Prop_lut3_I1_O) 0.045 -0.022 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[753]_i_1/O net (fo=1, routed) 0.000 -0.022 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[753] SLICE_X135Y48 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.018 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X135Y48 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753]/C clock pessimism 0.037 -0.253 SLICE_X135Y48 FDCE (Hold_fdce_C_D) 0.107 -0.146 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753] ------------------------------------------------------------------- required time 0.146 arrival time -0.022 ------------------------------------------------------------------- slack 0.125 Slack (MET) : 0.125ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.512ns (logic 0.164ns (32.024%) route 0.348ns (67.976%)) Logic Levels: 0 Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.594 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X108Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y100 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/Q net (fo=1, routed) 0.348 -0.157 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[15] SLICE_X103Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X103Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15]/C clock pessimism 0.040 -0.339 SLICE_X103Y99 FDCE (Hold_fdce_C_D) 0.057 -0.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15] ------------------------------------------------------------------- required time 0.282 arrival time -0.157 ------------------------------------------------------------------- slack 0.125 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[2] SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.229 -0.612 SLICE_X59Y91 FDCE (Hold_fdce_C_D) 0.071 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.541 arrival time -0.415 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.373ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/Q net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[17] SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.935 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17]/C clock pessimism -0.229 -0.602 SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.071 -0.531 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17] ------------------------------------------------------------------- required time 0.531 arrival time -0.405 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.603ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.659 -0.603 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X115Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.462 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/Q net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[1] SLICE_X115Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X115Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1]/C clock pessimism -0.229 -0.603 SLICE_X115Y91 FDCE (Hold_fdce_C_D) 0.071 -0.532 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1] ------------------------------------------------------------------- required time 0.532 arrival time -0.406 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.373ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X115Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/Q net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[21] SLICE_X115Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.935 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X115Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21]/C clock pessimism -0.229 -0.602 SLICE_X115Y96 FDCE (Hold_fdce_C_D) 0.071 -0.531 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21] ------------------------------------------------------------------- required time 0.531 arrival time -0.405 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.127ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[5] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.711ns (logic 0.141ns (19.823%) route 0.570ns (80.177%)) Logic Levels: 0 Clock Path Skew: 0.401ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.665ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.598 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X137Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/Q net (fo=10, routed) 0.570 0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg_0[1] RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[5] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.004 -0.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mlkem_clk RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKBWRCLK clock pessimism 0.040 -0.263 RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[5]) 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg ------------------------------------------------------------------- required time 0.080 arrival time 0.046 ------------------------------------------------------------------- slack 0.127 Slack (MET) : 0.127ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[5] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.711ns (logic 0.141ns (19.823%) route 0.570ns (80.177%)) Logic Levels: 0 Clock Path Skew: 0.401ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.665ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.598 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X137Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/Q net (fo=10, routed) 0.570 0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg_0[1] RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[5] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.004 -0.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mlkem_clk RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKBWRCLK clock pessimism 0.040 -0.263 RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[5]) 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg ------------------------------------------------------------------- required time 0.080 arrival time 0.046 ------------------------------------------------------------------- slack 0.127 Slack (MET) : 0.128ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q net (fo=1, routed) 0.058 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[1] SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.226 -0.613 SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.071 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.542 arrival time -0.415 ------------------------------------------------------------------- slack 0.128 Slack (MET) : 0.129ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.255ns (logic 0.141ns (55.379%) route 0.114ns (44.621%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.443ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.593 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/mlkem_clk SLICE_X123Y110 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X123Y110 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/Q net (fo=7, routed) 0.114 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r[3] SLICE_X120Y109 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.865 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/mlkem_clk SLICE_X120Y109 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK clock pessimism -0.210 -0.653 SLICE_X120Y109 SRL16E (Hold_srl16e_CLK_D) 0.109 -0.544 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.544 arrival time -0.415 ------------------------------------------------------------------- slack 0.129 Slack (MET) : 0.130ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.282ns (logic 0.141ns (49.987%) route 0.141ns (50.013%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.594 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk SLICE_X134Y112 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X134Y112 FDCE (Prop_fdce_C_Q) 0.141 -0.528 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/Q net (fo=5, routed) 0.141 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[0] SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.863 -0.445 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK clock pessimism -0.189 -0.634 SLICE_X136Y113 SRL16E (Hold_srl16e_CLK_D) 0.117 -0.517 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.517 arrival time -0.387 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.130ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.313ns (logic 0.141ns (45.032%) route 0.172ns (54.968%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X57Y91 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y91 FDRE (Prop_fdre_C_Q) 0.141 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/Q net (fo=1, routed) 0.172 -0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIB0 SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK clock pessimism -0.192 -0.573 SLICE_X52Y90 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.427 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB ------------------------------------------------------------------- required time 0.427 arrival time -0.297 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.130ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.544ns (logic 0.141ns (25.911%) route 0.403ns (74.090%)) Logic Levels: 0 Clock Path Skew: 0.343ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.371ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.589 -0.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk SLICE_X103Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/C ------------------------------------------------------------------- ------------------- SLICE_X103Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.533 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/Q net (fo=1, routed) 0.403 -0.130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0_n_0 SLICE_X117Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.937 -0.371 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk SLICE_X117Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1/C clock pessimism 0.040 -0.331 SLICE_X117Y99 FDCE (Hold_fdce_C_D) 0.071 -0.260 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1 ------------------------------------------------------------------- required time 0.260 arrival time -0.130 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.131ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.065 -0.407 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.226 -0.613 SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.075 -0.538 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.538 arrival time -0.407 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.382ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.470 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q net (fo=1, routed) 0.065 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[1] SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.229 -0.611 SLICE_X54Y88 FDCE (Hold_fdce_C_D) 0.075 -0.536 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.536 arrival time -0.405 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.132ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.237ns (logic 0.186ns (78.504%) route 0.051ns (21.496%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/Q net (fo=1, routed) 0.051 -0.421 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_burst_reg[1]_0[14] SLICE_X55Y85 LUT4 (Prop_lut4_I0_O) 0.045 -0.376 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1/O net (fo=1, routed) 0.000 -0.376 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1_n_0 SLICE_X55Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X55Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14]/C clock pessimism -0.215 -0.600 SLICE_X55Y85 FDRE (Hold_fdre_C_D) 0.092 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14] ------------------------------------------------------------------- required time 0.508 arrival time -0.376 ------------------------------------------------------------------- slack 0.132 Slack (MET) : 0.133ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.530ns (logic 0.141ns (26.621%) route 0.389ns (73.379%)) Logic Levels: 0 Clock Path Skew: 0.338ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.370ns Source Clock Delay (SCD): -0.668ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.595 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/mlkem_clk SLICE_X122Y105 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y105 FDCE (Prop_fdce_C_Q) 0.141 -0.527 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/Q net (fo=14, routed) 0.389 -0.138 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[23]_1[16] SLICE_X128Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.938 -0.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/mlkem_clk SLICE_X128Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16]/C clock pessimism 0.040 -0.330 SLICE_X128Y99 FDCE (Hold_fdce_C_D) 0.059 -0.271 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16] ------------------------------------------------------------------- required time 0.271 arrival time -0.138 ------------------------------------------------------------------- slack 0.133 Slack (MET) : 0.133ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[22]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[24]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.466ns (logic 0.327ns (70.202%) route 0.139ns (29.798%)) Logic Levels: 2 (CARRY4=2) Clock Path Skew: 0.198ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.449ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.655 -0.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X103Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y99 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[22]/Q net (fo=2, routed) 0.138 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4[22] SLICE_X102Y99 CARRY4 (Prop_carry4_DI[2]_CO[3]) 0.133 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[23]_i_1/CO[3] net (fo=1, routed) 0.001 -0.195 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[23]_i_1_n_0 SLICE_X102Y100 CARRY4 (Prop_carry4_CI_O[0]) 0.053 -0.142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[24]_i_1/O[0] net (fo=1, routed) 0.000 -0.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s50[24] SLICE_X102Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[24]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.859 -0.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X102Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[24]/C clock pessimism 0.040 -0.409 SLICE_X102Y100 FDCE (Hold_fdce_C_D) 0.134 -0.275 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[24] ------------------------------------------------------------------- required time 0.275 arrival time -0.142 ------------------------------------------------------------------- slack 0.133 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: mlkem_clk Waveform(ns): { 0.000 6.500 } Period(ns): 13.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y39 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y38 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y40 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y41 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB36_X7Y14 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y37 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X8Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X6Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y44 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y43 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y42 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y45 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y39 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y38 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y40 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y41 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB36_X7Y14 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y37 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X8Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X6Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y44 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y43 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y42 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y45 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 13.000 10.845 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout3_buf/I Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 13.000 11.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X160Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[0]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[1]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[2]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[3]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[4]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X160Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[5]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[6]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[7]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X102Y84 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[94]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X105Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[95]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X102Y84 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[96]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X107Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[97]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X109Y78 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[98]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X111Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[99]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X127Y86 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[9]/C Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X155Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/snt_ack_reg/C Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 13.000 147.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK >>>>>>> Stashed changes --------------------------------------------------------------------------------------------------- From Clock: sys_clk To Clock: sys_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA <<<<<<< Updated upstream Hold : 0 Failing Endpoints, Worst Slack 0.040ns, Total Violation 0.000ns ======= Hold : 0 Failing Endpoints, Worst Slack 0.024ns, Total Violation 0.000ns >>>>>>> Stashed changes PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- <<<<<<< Updated upstream Slack (MET) : 0.040ns (arrival time - required time) Source: u_matmul_axi_slave/m_in_b_reg[1][23]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.835%) route 0.302ns (68.165%)) Logic Levels: 0 Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.589 -0.674 u_matmul_axi_slave/sys_clk SLICE_X47Y102 FDRE r u_matmul_axi_slave/m_in_b_reg[1][23]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y102 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_matmul_axi_slave/m_in_b_reg[1][23]/Q net (fo=1, routed) 0.302 -0.231 u_matmul_axi_slave/mult_inst[1].u_mult/Q[23] SLICE_X59Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.927 -0.381 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X59Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/C clock pessimism 0.040 -0.341 SLICE_X59Y98 FDRE (Hold_fdre_C_D) 0.070 -0.271 u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23] ------------------------------------------------------------------- required time 0.271 arrival time -0.231 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.412ns (logic 0.187ns (45.442%) route 0.225ns (54.558%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.413ns Source Clock Delay (SCD): -0.639ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.623 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X82Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.498 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/Q net (fo=3, routed) 0.225 -0.274 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg_n_0_[11] SLICE_X85Y77 LUT3 (Prop_lut3_I2_O) 0.046 -0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/O net (fo=1, routed) 0.000 -0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1_n_0 SLICE_X85Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.895 -0.413 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X85Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/C clock pessimism 0.037 -0.376 SLICE_X85Y77 FDCE (Hold_fdce_C_D) 0.107 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] ------------------------------------------------------------------- required time 0.269 arrival time -0.228 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.049ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.382ns (logic 0.141ns (36.898%) route 0.241ns (63.102%)) Logic Levels: 0 Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.487ns Source Clock Delay (SCD): -0.710ns Clock Pessimism Removal (CPR): -0.040ns ======= Slack (MET) : 0.024ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.553 -0.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/sys_clk SLICE_X85Y170 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y170 FDCE (Prop_fdce_C_Q) 0.141 -0.569 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/Q net (fo=14, routed) 0.241 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[9] SLICE_X81Y171 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D ======= net (fo=9971, routed) 0.652 -0.610 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X57Y90 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.821 -0.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/sys_clk SLICE_X81Y171 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/C clock pessimism 0.040 -0.447 SLICE_X81Y171 FDCE (Hold_fdce_C_D) 0.070 -0.377 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9] ------------------------------------------------------------------- required time 0.377 arrival time -0.328 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.056ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D ======= net (fo=9971, routed) 0.927 -0.381 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK clock pessimism -0.216 -0.597 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.287 arrival time -0.263 ------------------------------------------------------------------- slack 0.024 Slack (MET) : 0.024ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X57Y90 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.927 -0.381 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK clock pessimism -0.216 -0.597 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.287 arrival time -0.263 ------------------------------------------------------------------- slack 0.024 Slack (MET) : 0.067ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D >>>>>>> Stashed changes (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.508ns (logic 0.213ns (41.922%) route 0.295ns (58.078%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.345ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.294ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): -0.037ns ======= Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/sys_clk SLICE_X112Y55 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C ------------------------------------------------------------------- ------------------- SLICE_X112Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.438 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/Q net (fo=5, routed) 0.295 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[8] SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.049 -0.094 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/O net (fo=1, routed) 0.000 -0.094 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[8] SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D ======= net (fo=9971, routed) 0.559 -0.704 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X82Y130 FDRE r u_axi_uart_controller/uart0/regs/dl_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[19]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) 0.063 -0.269 r u_axi_uart_controller/uart0/regs/M_next_carry/O[3] net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.014 -0.294 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/sys_clk SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/C clock pessimism 0.037 -0.257 SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8] ------------------------------------------------------------------- required time 0.150 arrival time -0.094 ------------------------------------------------------------------- slack 0.056 Slack (MET) : 0.061ns (arrival time - required time) Source: u_confreg/confreg_int_set_reg[11]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[11]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.376ns (logic 0.246ns (65.365%) route 0.130ns (34.635%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.335ns Source Clock Delay (SCD): -0.494ns Clock Pessimism Removal (CPR): -0.037ns ======= net (fo=9971, routed) 0.827 -0.481 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/C clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] ------------------------------------------------------------------- required time 0.336 arrival time -0.269 ------------------------------------------------------------------- slack 0.067 Slack (MET) : 0.071ns (arrival time - required time) Source: u_matmul_axi_slave/req_1_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/busy_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.362ns (logic 0.186ns (51.410%) route 0.176ns (48.590%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.040ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.769 -0.494 u_confreg/sys_clk SLICE_X8Y49 FDRE r u_confreg/confreg_int_set_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y49 FDRE (Prop_fdre_C_Q) 0.148 -0.346 r u_confreg/confreg_int_set_reg[11]/Q net (fo=2, routed) 0.130 -0.215 u_confreg/u_int_ctrl/edge_int_state_reg[31]_0[11] SLICE_X8Y51 LUT4 (Prop_lut4_I2_O) 0.098 -0.117 r u_confreg/u_int_ctrl/edge_int_state[11]_i_1/O net (fo=1, routed) 0.000 -0.117 u_confreg/u_int_ctrl/edge_int_state[11]_i_1_n_0 SLICE_X8Y51 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[11]/D ======= net (fo=9971, routed) 0.655 -0.607 u_matmul_axi_slave/sys_clk SLICE_X45Y99 FDRE r u_matmul_axi_slave/req_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.466 r u_matmul_axi_slave/req_1_reg/Q net (fo=19, routed) 0.176 -0.291 u_matmul_axi_slave/p_5_in[1] SLICE_X45Y100 LUT6 (Prop_lut6_I2_O) 0.045 -0.246 r u_matmul_axi_slave/busy_i_1/O net (fo=1, routed) 0.000 -0.246 u_matmul_axi_slave/busy_i_1_n_0 SLICE_X45Y100 FDRE r u_matmul_axi_slave/busy_reg/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.973 -0.335 u_confreg/u_int_ctrl/sys_clk SLICE_X8Y51 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[11]/C clock pessimism 0.037 -0.298 SLICE_X8Y51 FDCE (Hold_fdce_C_D) 0.120 -0.178 u_confreg/u_int_ctrl/edge_int_state_reg[11] ------------------------------------------------------------------- required time 0.178 arrival time -0.117 ------------------------------------------------------------------- slack 0.061 Slack (MET) : 0.074ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D ======= net (fo=9971, routed) 0.860 -0.448 u_matmul_axi_slave/sys_clk SLICE_X45Y100 FDRE r u_matmul_axi_slave/busy_reg/C clock pessimism 0.040 -0.408 SLICE_X45Y100 FDRE (Hold_fdre_C_D) 0.091 -0.317 u_matmul_axi_slave/busy_reg ------------------------------------------------------------------- required time 0.317 arrival time -0.246 ------------------------------------------------------------------- slack 0.071 Slack (MET) : 0.073ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.393ns (logic 0.227ns (57.716%) route 0.166ns (42.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.453ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.650 -0.612 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/sys_clk SLICE_X63Y98 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y98 FDRE (Prop_fdre_C_Q) 0.128 -0.484 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/Q net (fo=7, routed) 0.166 -0.318 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[1] SLICE_X62Y100 LUT6 (Prop_lut6_I1_O) 0.099 -0.219 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/O net (fo=1, routed) 0.000 -0.219 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/p_1_in[2] SLICE_X62Y100 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.855 -0.453 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/sys_clk SLICE_X62Y100 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/C clock pessimism 0.040 -0.413 SLICE_X62Y100 FDRE (Hold_fdre_C_D) 0.121 -0.292 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2] ------------------------------------------------------------------- required time 0.292 arrival time -0.219 ------------------------------------------------------------------- slack 0.073 Slack (MET) : 0.073ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.437ns (logic 0.189ns (43.230%) route 0.248ns (56.770%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.257ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.486ns Source Clock Delay (SCD): -0.703ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk SLICE_X87Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/Q net (fo=21, routed) 0.248 -0.314 u_Axi_CDC/wFifo/Q[27] SLICE_X82Y126 LUT4 (Prop_lut4_I2_O) 0.048 -0.266 r u_Axi_CDC/wFifo/reg_datai_32[19]_i_1/O net (fo=1, routed) 0.000 -0.266 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[19] SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.822 -0.486 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/C clock pessimism 0.040 -0.446 SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.107 -0.339 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19] ------------------------------------------------------------------- required time 0.339 arrival time -0.266 ------------------------------------------------------------------- slack 0.073 Slack (MET) : 0.074ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D >>>>>>> Stashed changes (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.526ns (logic 0.210ns (39.912%) route 0.316ns (60.088%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.345ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.294ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): -0.037ns ======= Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/sys_clk SLICE_X112Y53 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C ------------------------------------------------------------------- ------------------- SLICE_X112Y53 FDRE (Prop_fdre_C_Q) 0.164 -0.438 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/Q net (fo=5, routed) 0.316 -0.122 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[10] SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.046 -0.076 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/O net (fo=1, routed) 0.000 -0.076 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[10] SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D ======= net (fo=9971, routed) 0.559 -0.704 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X82Y130 FDRE r u_axi_uart_controller/uart0/regs/dl_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) 0.070 -0.262 r u_axi_uart_controller/uart0/regs/M_next_carry/O[0] net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.014 -0.294 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/sys_clk SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/C clock pessimism 0.037 -0.257 SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10] ------------------------------------------------------------------- required time 0.150 arrival time -0.076 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.076ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.313ns Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): 0.192ns ======= net (fo=9971, routed) 0.827 -0.481 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/C clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] ------------------------------------------------------------------- required time 0.336 arrival time -0.262 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.074ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.425ns (logic 0.209ns (49.172%) route 0.216ns (50.828%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.259ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.486ns Source Clock Delay (SCD): -0.705ns Clock Pessimism Removal (CPR): -0.040ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.716 -0.546 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X4Y67 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ======= net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk SLICE_X84Y128 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y128 FDRE (Prop_fdre_C_Q) 0.164 -0.541 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/Q net (fo=23, routed) 0.216 -0.325 u_Axi_CDC/wFifo/Q[19] SLICE_X82Y126 LUT6 (Prop_lut6_I3_O) 0.045 -0.280 r u_Axi_CDC/wFifo/reg_datai_32[3]_i_1/O net (fo=1, routed) 0.000 -0.280 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[3] SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.995 -0.313 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK clock pessimism -0.192 -0.505 SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.196 arrival time -0.120 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.076ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.313ns Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): 0.192ns ======= net (fo=9971, routed) 0.822 -0.486 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/C clock pessimism 0.040 -0.446 SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.092 -0.354 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3] ------------------------------------------------------------------- required time 0.354 arrival time -0.280 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.080ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/ier_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.436ns (logic 0.209ns (47.943%) route 0.227ns (52.057%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.476ns Source Clock Delay (SCD): -0.700ns Clock Pessimism Removal (CPR): -0.040ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.716 -0.546 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X4Y67 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ======= net (fo=9971, routed) 0.563 -0.700 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X84Y133 FDRE r u_axi_uart_controller/uart0/regs/ier_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 r u_axi_uart_controller/uart0/regs/ier_reg[3]/Q net (fo=3, routed) 0.227 -0.309 u_axi_uart_controller/uart0/regs/transmitter/Q[0] SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.264 r u_axi_uart_controller/uart0/regs/transmitter/ms_int_pnd_i_1/O net (fo=1, routed) 0.000 -0.264 u_axi_uart_controller/uart0/regs/transmitter_n_1 SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.995 -0.313 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK clock pessimism -0.192 -0.505 SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.196 arrival time -0.120 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.087ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ======= net (fo=9971, routed) 0.832 -0.476 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/C clock pessimism 0.040 -0.436 SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ms_int_pnd_reg ------------------------------------------------------------------- required time 0.344 arrival time -0.264 ------------------------------------------------------------------- slack 0.080 Slack (MET) : 0.081ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.186ns (40.004%) route 0.279ns (59.996%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.705ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk SLICE_X85Y128 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y128 FDRE (Prop_fdre_C_Q) 0.141 -0.564 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/Q net (fo=20, routed) 0.279 -0.285 u_Axi_CDC/wFifo/Q[14] SLICE_X80Y128 LUT5 (Prop_lut5_I4_O) 0.045 -0.240 r u_Axi_CDC/wFifo/reg_datai_32[14]_i_1/O net (fo=1, routed) 0.000 -0.240 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[14] SLICE_X80Y128 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.827 -0.481 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk SLICE_X80Y128 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/C clock pessimism 0.040 -0.441 SLICE_X80Y128 FDRE (Hold_fdre_C_D) 0.120 -0.321 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14] ------------------------------------------------------------------- required time 0.321 arrival time -0.240 ------------------------------------------------------------------- slack 0.081 Slack (MET) : 0.083ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/ier_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.439ns (logic 0.209ns (47.634%) route 0.230ns (52.366%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.476ns Source Clock Delay (SCD): -0.700ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.563 -0.700 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X84Y133 FDRE r u_axi_uart_controller/uart0/regs/ier_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 r u_axi_uart_controller/uart0/regs/ier_reg[0]/Q net (fo=6, routed) 0.230 -0.306 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/Q[0] SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.261 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/ti_int_pnd_i_1/O net (fo=1, routed) 0.000 -0.261 u_axi_uart_controller/uart0/regs/receiver_n_1 SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.832 -0.476 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/C clock pessimism 0.040 -0.436 SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ti_int_pnd_reg ------------------------------------------------------------------- required time 0.344 arrival time -0.261 ------------------------------------------------------------------- slack 0.083 Slack (MET) : 0.084ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk SLICE_X43Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/Q[7] RAMB18_X2Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.962 -0.346 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/sys_clk RAMB18_X2Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK clock pessimism -0.213 -0.559 RAMB18_X2Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.292 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk SLICE_X43Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/Q[7] RAMB18_X2Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.962 -0.346 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/sys_clk RAMB18_X2Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK clock pessimism -0.213 -0.559 RAMB18_X2Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.292 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 >>>>>>> Stashed changes (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns ======= Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.693 -0.569 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X15Y61 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ======= net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.969 -0.339 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK clock pessimism -0.192 -0.531 SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.221 arrival time -0.135 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ======= net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 >>>>>>> Stashed changes (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns ======= Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.693 -0.569 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X15Y61 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ======= net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.969 -0.339 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK clock pessimism -0.192 -0.531 SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.221 arrival time -0.135 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) ======= net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) >>>>>>> Stashed changes Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns ======= Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 ======= net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/CLK clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) ======= net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) >>>>>>> Stashed changes Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns ======= Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 ======= net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/CLK clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1 ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) ======= net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) >>>>>>> Stashed changes Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns ======= Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 ======= net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/CLK clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) ======= net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) >>>>>>> Stashed changes Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns ======= Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 ======= net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/CLK clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1 ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) ======= net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) >>>>>>> Stashed changes Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/CLK clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/CLK clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1 ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns ======= Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 ======= net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/CLK clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) ======= net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) >>>>>>> Stashed changes Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.230ns Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns ======= Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.434ns (logic 0.186ns (42.838%) route 0.248ns (57.162%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.257ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.486ns Source Clock Delay (SCD): -0.703ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk SLICE_X87Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/Q net (fo=21, routed) 0.248 -0.314 u_Axi_CDC/wFifo/Q[27] SLICE_X82Y126 LUT5 (Prop_lut5_I2_O) 0.045 -0.269 r u_Axi_CDC/wFifo/reg_datai_32[11]_i_1/O net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[11] SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.822 -0.486 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11]/C clock pessimism 0.040 -0.446 SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.091 -0.355 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11] ------------------------------------------------------------------- required time 0.355 arrival time -0.269 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.087ns (arrival time - required time) Source: u_matmul_axi_slave/req_0_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/req_0_reg_rep__0/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.378ns (logic 0.186ns (49.193%) route 0.192ns (50.807%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.655 -0.607 u_matmul_axi_slave/sys_clk SLICE_X45Y99 FDRE r u_matmul_axi_slave/req_0_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.466 r u_matmul_axi_slave/req_0_reg/Q net (fo=96, routed) 0.192 -0.274 u_matmul_axi_slave/p_5_in[0] SLICE_X45Y100 LUT6 (Prop_lut6_I4_O) 0.045 -0.229 r u_matmul_axi_slave/req_0_rep_i_1__0/O net (fo=1, routed) 0.000 -0.229 u_matmul_axi_slave/req_0_rep_i_1__0_n_0 SLICE_X45Y100 FDRE r u_matmul_axi_slave/req_0_reg_rep__0/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.860 -0.448 u_matmul_axi_slave/sys_clk SLICE_X45Y100 FDRE r u_matmul_axi_slave/req_0_reg_rep__0/C clock pessimism 0.040 -0.408 SLICE_X45Y100 FDRE (Hold_fdre_C_D) 0.092 -0.316 u_matmul_axi_slave/req_0_reg_rep__0 ------------------------------------------------------------------- required time 0.316 arrival time -0.229 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/enable_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.186ns (42.057%) route 0.256ns (57.943%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.478ns Source Clock Delay (SCD): -0.701ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.562 -0.701 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X86Y132 FDRE r u_axi_uart_controller/uart0/regs/enable_reg/C ------------------------------------------------------------------- ------------------- SLICE_X86Y132 FDRE (Prop_fdre_C_Q) 0.141 -0.560 r u_axi_uart_controller/uart0/regs/enable_reg/Q net (fo=12, routed) 0.256 -0.304 u_axi_uart_controller/uart0/regs/enable SLICE_X83Y133 LUT4 (Prop_lut4_I1_O) 0.045 -0.259 r u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/O net (fo=1, routed) 0.000 -0.259 u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1_n_0 SLICE_X83Y133 FDRE r u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.830 -0.478 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X83Y133 FDRE r u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/C clock pessimism 0.040 -0.438 SLICE_X83Y133 FDRE (Hold_fdre_C_D) 0.092 -0.346 u_axi_uart_controller/uart0/regs/sclk_en_reg_reg ------------------------------------------------------------------- required time 0.346 arrival time -0.259 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.096ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 ======= net (fo=9971, routed) 0.652 -0.610 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X57Y90 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.128 -0.482 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.236 -0.246 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/CLK clock pessimism -0.220 -0.450 SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1 ------------------------------------------------------------------- required time 0.140 arrival time -0.053 ------------------------------------------------------------------- slack 0.087 Slack (MET) : 0.089ns (arrival time - required time) Source: u_confreg/int_out_or_q1_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/int_out_or_q2_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.480ns (logic 0.141ns (29.360%) route 0.339ns (70.640%)) Logic Levels: 0 Clock Path Skew: 0.316ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.260ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk SLICE_X4Y50 FDRE r u_confreg/int_out_or_q1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/int_out_or_q1_reg/Q net (fo=1, routed) 0.339 -0.059 u_confreg/int_out_or_q1 SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.048 -0.260 u_confreg/sys_clk SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/C clock pessimism 0.037 -0.223 SLICE_X9Y47 FDRE (Hold_fdre_C_D) 0.075 -0.148 u_confreg/int_out_or_q2_reg ------------------------------------------------------------------- required time 0.148 arrival time -0.059 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.093ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk SLICE_X103Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[2] RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.961 -0.347 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/sys_clk RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK clock pessimism -0.212 -0.559 RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.283 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.093ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk SLICE_X103Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[2] RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.961 -0.347 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/sys_clk RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK clock pessimism -0.212 -0.559 RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.283 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.097ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.804%) route 0.302ns (68.196%)) Logic Levels: 0 Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.644 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk SLICE_X157Y150 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/Q net (fo=14, routed) 0.302 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[13] SLICE_X159Y138 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk SLICE_X159Y138 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/C clock pessimism 0.045 -0.343 SLICE_X159Y138 FDCE (Hold_fdce_C_D) 0.070 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13] ------------------------------------------------------------------- required time 0.273 arrival time -0.176 ------------------------------------------------------------------- slack 0.097 Slack (MET) : 0.098ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.701ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X83Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C ------------------------------------------------------------------- ------------------- SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/O net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1_n_0 SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.833 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/C clock pessimism 0.040 -0.435 SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.092 -0.343 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4] ------------------------------------------------------------------- required time 0.343 arrival time -0.245 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.099ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.701ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X83Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C ------------------------------------------------------------------- ------------------- SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/O net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1_n_0 SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.833 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/C clock pessimism 0.040 -0.435 SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.091 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3] ------------------------------------------------------------------- required time 0.344 arrival time -0.245 ------------------------------------------------------------------- slack 0.099 Slack (MET) : 0.101ns (arrival time - required time) Source: u_matmul_axi_slave/m_in_a_reg[1][28]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.496ns (logic 0.164ns (33.088%) route 0.332ns (66.911%)) Logic Levels: 0 Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.675ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.588 -0.675 u_matmul_axi_slave/sys_clk SLICE_X44Y105 FDRE r u_matmul_axi_slave/m_in_a_reg[1][28]/C ------------------------------------------------------------------- ------------------- SLICE_X44Y105 FDRE (Prop_fdre_C_Q) 0.164 -0.511 r u_matmul_axi_slave/m_in_a_reg[1][28]/Q net (fo=1, routed) 0.332 -0.179 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[28] SLICE_X56Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.929 -0.379 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X56Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/C clock pessimism 0.040 -0.339 SLICE_X56Y98 FDRE (Hold_fdre_C_D) 0.059 -0.280 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28] ------------------------------------------------------------------- required time 0.280 arrival time -0.179 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.104ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.451ns (logic 0.141ns (31.244%) route 0.310ns (68.756%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.644 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk SLICE_X157Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/Q net (fo=15, routed) 0.310 -0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[18] SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/C clock pessimism 0.045 -0.342 SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.070 -0.272 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18] ------------------------------------------------------------------- required time 0.272 arrival time -0.168 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk SLICE_X102Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[4] RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.961 -0.347 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/sys_clk RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK clock pessimism -0.212 -0.559 RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.270 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk SLICE_X102Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[4] RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.961 -0.347 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/sys_clk RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK clock pessimism -0.212 -0.559 RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.270 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.449ns (logic 0.141ns (31.381%) route 0.308ns (68.619%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.644 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk SLICE_X157Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/Q net (fo=15, routed) 0.308 -0.170 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[17] SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/C clock pessimism 0.045 -0.342 SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.066 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17] ------------------------------------------------------------------- required time 0.276 arrival time -0.170 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.108ns (arrival time - required time) Source: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/buf_addr_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.425ns (logic 0.186ns (43.780%) route 0.239ns (56.220%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.336ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/sys_clk SLICE_X13Y45 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.354 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/Q net (fo=13, routed) 0.239 -0.115 u_Axi_CDC/arFifo/_zz_ram_port1[2] SLICE_X16Y51 LUT5 (Prop_lut5_I1_O) 0.045 -0.070 r u_Axi_CDC/arFifo/buf_addr[2]_i_1/O net (fo=1, routed) 0.000 -0.070 u_confreg/buf_addr_reg[15]_0[2] SLICE_X16Y51 FDRE r u_confreg/buf_addr_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.972 -0.336 u_confreg/sys_clk SLICE_X16Y51 FDRE r u_confreg/buf_addr_reg[2]/C clock pessimism 0.037 -0.299 SLICE_X16Y51 FDRE (Hold_fdre_C_D) 0.121 -0.178 u_confreg/buf_addr_reg[2] ------------------------------------------------------------------- required time 0.178 arrival time -0.070 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.111ns (arrival time - required time) Source: u_confreg/digital_data_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.353ns (logic 0.141ns (39.954%) route 0.212ns (60.046%)) Logic Levels: 0 Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.798 -0.465 u_confreg/sys_clk SLICE_X0Y49 FDRE r u_confreg/digital_data_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.324 r u_confreg/digital_data_reg[1]/Q net (fo=2, routed) 0.212 -0.112 u_confreg/u_digitaltube_controller/dpy1_data_reg[3]_0[1] SLICE_X0Y54 FDRE r u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.002 -0.306 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y54 FDRE r u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/C clock pessimism 0.037 -0.269 SLICE_X0Y54 FDRE (Hold_fdre_C_D) 0.047 -0.222 u_confreg/u_digitaltube_controller/dpy0_data_reg[1] ------------------------------------------------------------------- required time 0.222 arrival time -0.112 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.410ns (logic 0.209ns (50.949%) route 0.201ns (49.051%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.192ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.371ns Source Clock Delay (SCD): -0.527ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.736 -0.527 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/sys_clk SLICE_X116Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C ------------------------------------------------------------------- ------------------- SLICE_X116Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.363 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/Q net (fo=5, routed) 0.201 -0.162 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[3] SLICE_X118Y50 LUT3 (Prop_lut3_I2_O) 0.045 -0.117 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/O net (fo=1, routed) 0.000 -0.117 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[3] SLICE_X118Y50 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.937 -0.371 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/sys_clk SLICE_X118Y50 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/C clock pessimism 0.037 -0.334 SLICE_X118Y50 FDRE (Hold_fdre_C_D) 0.107 -0.227 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3] ------------------------------------------------------------------- required time 0.227 arrival time -0.117 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.112ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.141ns (32.928%) route 0.287ns (67.072%)) Logic Levels: 0 Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.490ns Source Clock Delay (SCD): -0.711ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.552 -0.711 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/sys_clk SLICE_X85Y171 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y171 FDCE (Prop_fdce_C_Q) 0.141 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/Q net (fo=14, routed) 0.287 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[12] SLICE_X81Y173 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.817 -0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/sys_clk SLICE_X81Y173 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/C clock pessimism 0.040 -0.450 SLICE_X81Y173 FDCE (Hold_fdce_C_D) 0.055 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12] ------------------------------------------------------------------- required time 0.395 arrival time -0.283 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.114ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.488ns (logic 0.231ns (47.314%) route 0.257ns (52.686%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.399ns Source Clock Delay (SCD): -0.629ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.633 -0.629 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/sys_clk SLICE_X83Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C ------------------------------------------------------------------- ------------------- SLICE_X83Y93 FDCE (Prop_fdce_C_Q) 0.128 -0.501 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/Q net (fo=118, routed) 0.257 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10_n_0 SLICE_X85Y98 LUT2 (Prop_lut2_I0_O) 0.103 -0.141 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/O net (fo=1, routed) 0.000 -0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1_n_0 SLICE_X85Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.909 -0.399 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/sys_clk SLICE_X85Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/C clock pessimism 0.037 -0.362 SLICE_X85Y98 FDCE (Hold_fdce_C_D) 0.107 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360] ------------------------------------------------------------------- required time 0.255 arrival time -0.141 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.115ns (arrival time - required time) Source: u_confreg/confreg_int_edge_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.798 -0.465 u_confreg/sys_clk SLICE_X2Y49 FDRE r u_confreg/confreg_int_edge_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 r u_confreg/confreg_int_edge_reg[3]/Q net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 SLICE_X3Y50 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.003 -0.305 u_confreg/u_int_ctrl/sys_clk SLICE_X3Y50 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[3]/C clock pessimism 0.037 -0.268 SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] ------------------------------------------------------------------- required time 0.177 arrival time -0.063 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.115ns (arrival time - required time) Source: u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.387ns (logic 0.141ns (36.445%) route 0.246ns (63.555%)) Logic Levels: 0 Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.798 -0.465 u_confreg/u_int_ctrl/sys_clk SLICE_X1Y49 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/Q net (fo=3, routed) 0.246 -0.078 u_confreg/u_int_ctrl/int_in_sync_d2[5] SLICE_X3Y51 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.003 -0.305 u_confreg/u_int_ctrl/sys_clk SLICE_X3Y51 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/C clock pessimism 0.037 -0.268 SLICE_X3Y51 FDCE (Hold_fdce_C_D) 0.075 -0.193 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5] ------------------------------------------------------------------- required time 0.193 arrival time -0.078 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.141ns (30.326%) route 0.324ns (69.674%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.644 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk SLICE_X157Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/Q net (fo=15, routed) 0.324 -0.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[19] SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/C clock pessimism 0.045 -0.342 SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.072 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19] ------------------------------------------------------------------- required time 0.270 arrival time -0.154 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/CLK clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ======= net (fo=9971, routed) 0.927 -0.381 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK clock pessimism -0.216 -0.597 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR1) 0.255 -0.342 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.342 arrival time -0.246 >>>>>>> Stashed changes ------------------------------------------------------------------- slack 0.096 <<<<<<< Updated upstream Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1 ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/CLK clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1 ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/CLK clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/CLK clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1 ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/CLK clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/CLK clock pessimism 0.037 -0.300 SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1 ------------------------------------------------------------------- required time -0.010 arrival time 0.127 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.118ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.475ns (logic 0.209ns (44.013%) route 0.266ns (55.987%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.420ns Source Clock Delay (SCD): -0.640ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.623 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X144Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C ------------------------------------------------------------------- ------------------- SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q net (fo=127, routed) 0.266 -0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.165 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/O net (fo=1, routed) 0.000 -0.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1_n_0 SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.887 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/C clock pessimism 0.045 -0.375 SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.092 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8] ------------------------------------------------------------------- required time 0.283 arrival time -0.165 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.475ns (logic 0.209ns (44.040%) route 0.266ns (55.960%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.403ns Source Clock Delay (SCD): -0.630ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.632 -0.630 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk SLICE_X84Y61 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C ------------------------------------------------------------------- ------------------- SLICE_X84Y61 FDRE (Prop_fdre_C_Q) 0.164 -0.466 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/Q net (fo=6, routed) 0.266 -0.201 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][14]__0_0[7] SLICE_X82Y61 LUT6 (Prop_lut6_I3_O) 0.045 -0.156 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/O net (fo=1, routed) 0.000 -0.156 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_sp_re[7] SLICE_X82Y61 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.905 -0.403 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/sys_clk SLICE_X82Y61 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/C clock pessimism 0.037 -0.366 SLICE_X82Y61 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7] ------------------------------------------------------------------- required time 0.274 arrival time -0.156 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.119ns (arrival time - required time) Source: u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) ======= Slack (MET) : 0.096ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) >>>>>>> Stashed changes Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) Logic Levels: 0 <<<<<<< Updated upstream Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.418ns Source Clock Delay (SCD): -0.645ns Clock Pessimism Removal (CPR): 0.227ns ======= Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.618 -0.645 u_matmul_axi_slave/mult_inst[3].u_mult/sys_clk SLICE_X39Y105 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y105 FDRE (Prop_fdre_C_Q) 0.141 -0.504 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/Q net (fo=1, routed) 0.056 -0.448 u_matmul_axi_slave/mult_inst[3].u_mult/prod[59] SLICE_X39Y105 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D ======= net (fo=9971, routed) 0.652 -0.610 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X57Y90 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.128 -0.482 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.236 -0.246 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.890 -0.418 u_matmul_axi_slave/mult_inst[3].u_mult/sys_clk SLICE_X39Y105 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/C clock pessimism -0.227 -0.645 SLICE_X39Y105 FDRE (Hold_fdre_C_D) 0.078 -0.567 u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59] ------------------------------------------------------------------- required time 0.567 arrival time -0.448 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.476ns (logic 0.209ns (43.921%) route 0.267ns (56.079%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.420ns Source Clock Delay (SCD): -0.640ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.623 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X144Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C ------------------------------------------------------------------- ------------------- SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q net (fo=127, routed) 0.267 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.164 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/O net (fo=1, routed) 0.000 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1_n_0 SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.887 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/C clock pessimism 0.045 -0.375 SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.091 -0.284 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6] ------------------------------------------------------------------- required time 0.284 arrival time -0.164 ------------------------------------------------------------------- slack 0.120 ======= net (fo=9971, routed) 0.927 -0.381 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK clock pessimism -0.216 -0.597 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR1) 0.255 -0.342 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.342 arrival time -0.246 ------------------------------------------------------------------- slack 0.096 >>>>>>> Stashed changes Slack (MET) : 0.100ns (arrival time - required time) Source: u_matmul_axi_slave/m_in_a_reg[1][14]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.368ns (logic 0.141ns (38.301%) route 0.227ns (61.699%)) Logic Levels: 0 <<<<<<< Updated upstream Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.234ns ======= Clock Path Skew: 0.198ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.411ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): -0.040ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X9Y43 FDCE (Prop_fdce_C_Q) 0.141 -0.354 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.298 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ======= net (fo=9971, routed) 0.693 -0.569 u_matmul_axi_slave/sys_clk SLICE_X23Y99 FDRE r u_matmul_axi_slave/m_in_a_reg[1][14]/C ------------------------------------------------------------------- ------------------- SLICE_X23Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.428 r u_matmul_axi_slave/m_in_a_reg[1][14]/Q net (fo=1, routed) 0.227 -0.201 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[14] SLICE_X23Y107 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.234 -0.495 SLICE_X9Y43 FDCE (Hold_fdce_C_D) 0.076 -0.419 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.419 arrival time -0.298 ------------------------------------------------------------------- slack 0.121 ======= net (fo=9971, routed) 0.897 -0.411 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X23Y107 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14]/C clock pessimism 0.040 -0.371 SLICE_X23Y107 FDRE (Hold_fdre_C_D) 0.070 -0.301 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14] ------------------------------------------------------------------- required time 0.301 arrival time -0.201 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.453ns (logic 0.186ns (41.032%) route 0.267ns (58.968%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.262ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.480ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk SLICE_X87Y131 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/Q net (fo=20, routed) 0.267 -0.294 u_Axi_CDC/wFifo/Q[6] SLICE_X81Y129 LUT6 (Prop_lut6_I5_O) 0.045 -0.249 r u_Axi_CDC/wFifo/reg_datai_32[6]_i_1/O net (fo=1, routed) 0.000 -0.249 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[6] SLICE_X81Y129 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.828 -0.480 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk SLICE_X81Y129 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6]/C clock pessimism 0.040 -0.440 SLICE_X81Y129 FDRE (Hold_fdre_C_D) 0.091 -0.349 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6] ------------------------------------------------------------------- required time 0.349 arrival time -0.249 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.102ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.455ns (logic 0.186ns (40.841%) route 0.269ns (59.159%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.482ns Source Clock Delay (SCD): -0.703ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/Q net (fo=20, routed) 0.269 -0.293 u_Axi_CDC/wFifo/Q[0] SLICE_X79Y127 LUT6 (Prop_lut6_I5_O) 0.045 -0.248 r u_Axi_CDC/wFifo/reg_datai_32[0]_i_1/O net (fo=1, routed) 0.000 -0.248 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[0] SLICE_X79Y127 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.826 -0.482 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk SLICE_X79Y127 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0]/C clock pessimism 0.040 -0.442 SLICE_X79Y127 FDRE (Hold_fdre_C_D) 0.092 -0.350 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0] ------------------------------------------------------------------- required time 0.350 arrival time -0.248 ------------------------------------------------------------------- slack 0.102 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1 ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1 ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1 ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/CLK clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 SLICE_X70Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK clock pessimism -0.192 -0.579 SLICE_X70Y97 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1 ------------------------------------------------------------------- required time 0.269 arrival time -0.164 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.106ns (arrival time - required time) Source: u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.240ns (logic 0.186ns (77.466%) route 0.054ns (22.534%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.456ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.581 -0.682 u_cdma_matmul_bridge/sys_clk SLICE_X63Y110 FDRE r u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y110 FDRE (Prop_fdre_C_Q) 0.141 -0.541 r u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/Q net (fo=1, routed) 0.054 -0.487 u_cdma_matmul_bridge/bank_dst_addr_reg[1]_3[20] SLICE_X62Y110 LUT6 (Prop_lut6_I0_O) 0.045 -0.442 r u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1/O net (fo=1, routed) 0.000 -0.442 u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1_n_0 SLICE_X62Y110 FDRE r u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.852 -0.456 u_cdma_matmul_bridge/sys_clk SLICE_X62Y110 FDRE r u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20]/C clock pessimism -0.213 -0.669 SLICE_X62Y110 FDRE (Hold_fdre_C_D) 0.121 -0.548 u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20] ------------------------------------------------------------------- required time 0.548 arrival time -0.442 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.108ns (arrival time - required time) Source: u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.540ns (logic 0.186ns (34.444%) route 0.354ns (65.556%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.340ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.683ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.580 -0.683 u_Axi_CDC/arFifo/sys_clk SLICE_X71Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y100 FDRE (Prop_fdre_C_Q) 0.141 -0.542 r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/Q net (fo=8, routed) 0.354 -0.188 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/_zz_ram_port1_reg[49][1] SLICE_X63Y97 LUT6 (Prop_lut6_I5_O) 0.045 -0.143 r u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/ar_id_reg[1]_i_1/O net (fo=2, routed) 0.000 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/I172[3] SLICE_X63Y97 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk SLICE_X63Y97 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1]/C clock pessimism 0.040 -0.343 SLICE_X63Y97 FDRE (Hold_fdre_C_D) 0.092 -0.251 u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1] ------------------------------------------------------------------- required time 0.251 arrival time -0.143 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.110ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.478ns (logic 0.292ns (61.119%) route 0.186ns (38.881%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.559 -0.704 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X82Y130 FDRE r u_axi_uart_controller/uart0/regs/dl_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[1]) 0.106 -0.226 r u_axi_uart_controller/uart0/regs/M_next_carry/O[1] net (fo=1, routed) 0.000 -0.226 u_axi_uart_controller/uart0/regs/M_next[1] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.827 -0.481 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[1]/C clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[1] ------------------------------------------------------------------- required time 0.336 arrival time -0.226 ------------------------------------------------------------------- slack 0.110 Slack (MET) : 0.112ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK clock pessimism -0.213 -0.599 SLICE_X68Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA ------------------------------------------------------------------- required time 0.289 arrival time -0.178 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK clock pessimism -0.213 -0.599 SLICE_X68Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.178 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB/CLK clock pessimism -0.213 -0.599 SLICE_X68Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB ------------------------------------------------------------------- required time 0.289 arrival time -0.178 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK clock pessimism -0.213 -0.599 SLICE_X68Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.178 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC/CLK clock pessimism -0.213 -0.599 SLICE_X68Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC ------------------------------------------------------------------- required time 0.289 arrival time -0.178 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK clock pessimism -0.213 -0.599 SLICE_X68Y97 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.178 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 SLICE_X68Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X68Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD/CLK clock pessimism -0.213 -0.599 SLICE_X68Y97 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD ------------------------------------------------------------------- required time 0.289 arrival time -0.178 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 SLICE_X68Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X68Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD_D1/CLK clock pessimism -0.213 -0.599 SLICE_X68Y97 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.178 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.115ns (arrival time - required time) Source: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/dl_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.455ns (logic 0.164ns (36.056%) route 0.291ns (63.944%)) Logic Levels: 0 Clock Path Skew: 0.270ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.707ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.556 -0.707 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk SLICE_X80Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y126 FDRE (Prop_fdre_C_Q) 0.164 -0.543 r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_reg[2]/Q net (fo=10, routed) 0.291 -0.252 u_axi_uart_controller/uart0/regs/infrared_reg_0[2] SLICE_X85Y133 FDRE r u_axi_uart_controller/uart0/regs/dl_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X85Y133 FDRE r u_axi_uart_controller/uart0/regs/dl_reg[10]/C clock pessimism 0.040 -0.437 SLICE_X85Y133 FDRE (Hold_fdre_C_D) 0.070 -0.367 u_axi_uart_controller/uart0/regs/dl_reg[10] ------------------------------------------------------------------- required time 0.367 arrival time -0.252 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.119ns (arrival time - required time) Source: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.699ns Clock Pessimism Removal (CPR): 0.222ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.564 -0.699 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y126 FDCE (Prop_fdce_C_Q) 0.141 -0.558 r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q net (fo=1, routed) 0.056 -0.502 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0[3] SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.222 -0.699 SLICE_X89Y126 FDCE (Hold_fdce_C_D) 0.078 -0.621 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.621 arrival time -0.502 ------------------------------------------------------------------- slack 0.119 >>>>>>> Stashed changes Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sys_clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin <<<<<<< Updated upstream Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X5Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X5Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y28 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X1Y28 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB36_X7Y18 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X5Y11 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X5Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y4 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y7 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y8 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X5Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X5Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X7Y18 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[13]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[14]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[15]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[16]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[17]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[18]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[19]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y63 u_cdma_matmul_bridge/load_next_idx_reg[1]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[20]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[21]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[22]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[23]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y69 u_cdma_matmul_bridge/load_next_idx_reg[24]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X141Y157 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[105][11]/C Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y61 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y61 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA_D1/CLK ======= Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X2Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X2Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y9 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X2Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X2Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y6 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y121 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[34]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y121 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[35]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[36]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[37]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[38]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[39]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X11Y112 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[3]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[40]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[41]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[42]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[43]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X69Y104 cdma_axil_b_bridge_reg/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X46Y92 u_matmul_axi_slave/b0_b_reg[0][0]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X72Y108 cdma_axil_r_bridge_reg/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X67Y105 cdma_axil_wr_active_reg/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X69Y105 cdma_axil_wr_bridge_hold_reg/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X12Y105 u_matmul_axi_slave/b0_b_reg[0][10]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X19Y92 u_matmul_axi_slave/b0_b_reg[0][11]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y79 u_matmul_axi_slave/b0_b_reg[0][12]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X4Y86 u_matmul_axi_slave/b0_b_reg[0][13]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X22Y103 u_matmul_axi_slave/b0_b_reg[0][14]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X2Y94 u_matmul_axi_slave/b0_b_reg[0][15]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X4Y86 u_matmul_axi_slave/b0_b_reg[0][16]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X37Y77 u_matmul_axi_slave/b0_b_reg[0][17]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X34Y76 u_matmul_axi_slave/b0_b_reg[0][18]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X47Y74 u_matmul_axi_slave/b0_b_reg[0][19]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X19Y92 u_matmul_axi_slave/b0_b_reg[0][1]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X46Y78 u_matmul_axi_slave/b0_b_reg[0][20]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y69 u_matmul_axi_slave/b0_b_reg[0][21]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X2Y94 u_matmul_axi_slave/b0_b_reg[0][22]/C Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA_D1/CLK >>>>>>> Stashed changes --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: cpu_clk To Clock: cpu_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA <<<<<<< Updated upstream Hold : 0 Failing Endpoints, Worst Slack 0.727ns, Total Violation 0.000ns ======= Hold : 0 Failing Endpoints, Worst Slack 0.681ns, Total Violation 0.000ns >>>>>>> Stashed changes --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- <<<<<<< Updated upstream Slack (MET) : 0.727ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.651ns (logic 0.227ns (34.873%) route 0.424ns (65.127%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.263ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.143 0.154 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X11Y39 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/bFifo/cpu_clk SLICE_X11Y39 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/C clock pessimism -0.218 -0.481 SLICE_X11Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.573 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.573 arrival time 0.154 ------------------------------------------------------------------- slack 0.727 Slack (MET) : 0.727ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.651ns (logic 0.227ns (34.873%) route 0.424ns (65.127%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.263ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.143 0.154 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X11Y39 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/bFifo/cpu_clk SLICE_X11Y39 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C clock pessimism -0.218 -0.481 SLICE_X11Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.573 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.573 arrival time 0.154 ------------------------------------------------------------------- slack 0.727 Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.218 -0.480 SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.547 arrival time 0.218 ------------------------------------------------------------------- slack 0.765 Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.218 -0.480 SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.547 arrival time 0.218 ------------------------------------------------------------------- slack 0.765 Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.218 -0.480 SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.547 arrival time 0.218 ------------------------------------------------------------------- slack 0.765 Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.218 -0.480 SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.547 arrival time 0.218 ------------------------------------------------------------------- slack 0.765 Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.218 -0.480 SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.547 arrival time 0.218 ------------------------------------------------------------------- slack 0.765 Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.218 -0.480 SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.547 arrival time 0.218 ------------------------------------------------------------------- slack 0.765 Slack (MET) : 0.790ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) ======= Slack (MET) : 0.681ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) >>>>>>> Stashed changes Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.736ns (logic 0.227ns (30.836%) route 0.509ns (69.164%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.263ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns ======= Data Path Delay: 0.596ns (logic 0.246ns (41.259%) route 0.350ns (58.741%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.007ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.228 0.239 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y39 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.293 -0.089 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X93Y122 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y39 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.196 -0.459 SLICE_X13Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.551 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.551 arrival time 0.239 ------------------------------------------------------------------- slack 0.790 Slack (MET) : 0.790ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.218 -0.480 SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.572 arrival time 0.218 ------------------------------------------------------------------- slack 0.790 Slack (MET) : 0.790ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/C clock pessimism -0.218 -0.480 SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.572 arrival time 0.218 ------------------------------------------------------------------- slack 0.790 Slack (MET) : 0.790ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.218 -0.480 SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.572 arrival time 0.218 ------------------------------------------------------------------- slack 0.790 Slack (MET) : 0.790ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.218 -0.480 SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.572 arrival time 0.218 ------------------------------------------------------------------- slack 0.790 Slack (MET) : 0.790ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.218 -0.480 SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.572 arrival time 0.218 ------------------------------------------------------------------- slack 0.790 Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.196 -0.457 SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 0.524 arrival time 0.329 ------------------------------------------------------------------- slack 0.853 Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.196 -0.457 SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 0.524 arrival time 0.329 ------------------------------------------------------------------- slack 0.853 Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.196 -0.457 SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 0.524 arrival time 0.329 ------------------------------------------------------------------- slack 0.853 Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.196 -0.457 SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 0.524 arrival time 0.329 ------------------------------------------------------------------- slack 0.853 Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.196 -0.457 SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 0.524 arrival time 0.329 ------------------------------------------------------------------- slack 0.853 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.196 -0.458 SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.525 arrival time 0.392 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.196 -0.457 SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.549 arrival time 0.368 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.196 -0.457 SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.549 arrival time 0.368 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.196 -0.457 SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.549 arrival time 0.368 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.917ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C clock pessimism -0.196 -0.457 SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 0.549 arrival time 0.368 ------------------------------------------------------------------- slack 0.917 Slack (MET) : 0.970ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.196 -0.457 SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.549 arrival time 0.421 ------------------------------------------------------------------- slack 0.970 Slack (MET) : 0.970ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.196 -0.457 SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.549 arrival time 0.421 ------------------------------------------------------------------- slack 0.970 Slack (MET) : 0.970ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.196 -0.457 SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.549 arrival time 0.421 ------------------------------------------------------------------- slack 0.970 Slack (MET) : 0.970ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.196 -0.457 SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.549 arrival time 0.421 ------------------------------------------------------------------- slack 0.970 Slack (MET) : 0.970ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.196 -0.457 SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.549 arrival time 0.421 ------------------------------------------------------------------- slack 0.970 Slack (MET) : 0.970ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.196 -0.457 SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.549 arrival time 0.421 ------------------------------------------------------------------- slack 0.970 Slack (MET) : 0.970ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.196 -0.457 SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.549 arrival time 0.421 ------------------------------------------------------------------- slack 0.970 Slack (MET) : 0.970ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.196 -0.457 SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.549 arrival time 0.421 ------------------------------------------------------------------- slack 0.970 Slack (MET) : 0.994ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.967ns (logic 0.227ns (23.471%) route 0.740ns (76.529%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.459 0.470 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C clock pessimism -0.196 -0.457 SLICE_X14Y43 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.524 arrival time 0.470 ------------------------------------------------------------------- slack 0.994 Slack (MET) : 0.994ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.967ns (logic 0.227ns (23.471%) route 0.740ns (76.529%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.459 0.470 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C clock pessimism -0.196 -0.457 SLICE_X14Y43 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.524 arrival time 0.470 ------------------------------------------------------------------- slack 0.994 Slack (MET) : 0.994ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.967ns (logic 0.227ns (23.471%) route 0.740ns (76.529%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.459 0.470 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C clock pessimism -0.196 -0.457 SLICE_X14Y43 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.524 arrival time 0.470 ------------------------------------------------------------------- slack 0.994 Slack (MET) : 0.994ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.967ns (logic 0.227ns (23.471%) route 0.740ns (76.529%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.497ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.459 0.470 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/C clock pessimism -0.196 -0.457 SLICE_X14Y43 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/rFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- required time 0.524 arrival time 0.470 ------------------------------------------------------------------- slack 0.994 Slack (MET) : 1.109ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.196 -0.458 SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 0.550 arrival time 0.559 ------------------------------------------------------------------- slack 1.109 Slack (MET) : 1.109ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.196 -0.458 SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 0.550 arrival time 0.559 ------------------------------------------------------------------- slack 1.109 Slack (MET) : 1.109ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.196 -0.458 SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 0.550 arrival time 0.559 ------------------------------------------------------------------- slack 1.109 Slack (MET) : 1.109ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C clock pessimism -0.196 -0.458 SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3] ------------------------------------------------------------------- required time 0.550 arrival time 0.559 ------------------------------------------------------------------- slack 1.109 Slack (MET) : 1.109ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y122 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.209 -0.678 SLICE_X93Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.770 arrival time -0.089 ------------------------------------------------------------------- slack 0.681 Slack (MET) : 0.692ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.189 -0.656 SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.723 arrival time -0.031 ------------------------------------------------------------------- slack 0.692 Slack (MET) : 0.692ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/C clock pessimism -0.189 -0.656 SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.723 arrival time -0.031 ------------------------------------------------------------------- slack 0.692 Slack (MET) : 0.692ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C clock pessimism -0.189 -0.656 SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.723 arrival time -0.031 ------------------------------------------------------------------- slack 0.692 Slack (MET) : 0.692ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.189 -0.656 SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.723 arrival time -0.031 ------------------------------------------------------------------- slack 0.692 Slack (MET) : 0.750ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.007ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/bFifo/cpu_clk SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/C clock pessimism -0.209 -0.678 SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.770 arrival time -0.020 ------------------------------------------------------------------- slack 0.750 Slack (MET) : 0.750ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.007ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/bFifo/cpu_clk SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.209 -0.678 SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.770 arrival time -0.020 ------------------------------------------------------------------- slack 0.750 Slack (MET) : 0.750ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.007ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/bFifo/cpu_clk SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.209 -0.678 SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.770 arrival time -0.020 ------------------------------------------------------------------- slack 0.750 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.209 -0.667 SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.734 arrival time 0.074 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.209 -0.667 SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.734 arrival time 0.074 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.209 -0.667 SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.734 arrival time 0.074 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.209 -0.667 SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.734 arrival time 0.074 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.209 -0.667 SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.734 arrival time 0.074 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.209 -0.667 SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.734 arrival time 0.074 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.967ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.474ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.189 -0.663 SLICE_X90Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.730 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.730 arrival time 0.237 ------------------------------------------------------------------- slack 0.967 Slack (MET) : 0.967ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.474ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.189 -0.663 SLICE_X90Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.730 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.730 arrival time 0.237 ------------------------------------------------------------------- slack 0.967 Slack (MET) : 0.967ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.474ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.189 -0.663 SLICE_X90Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.730 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.730 arrival time 0.237 ------------------------------------------------------------------- slack 0.967 Slack (MET) : 0.967ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.474ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.189 -0.663 SLICE_X90Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.730 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.730 arrival time 0.237 ------------------------------------------------------------------- slack 0.967 Slack (MET) : 0.967ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.474ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.189 -0.663 SLICE_X90Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.730 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.730 arrival time 0.237 ------------------------------------------------------------------- slack 0.967 Slack (MET) : 0.967ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.474ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.189 -0.663 SLICE_X90Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.730 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.730 arrival time 0.237 ------------------------------------------------------------------- slack 0.967 Slack (MET) : 0.992ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.474ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X91Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.189 -0.663 SLICE_X91Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.755 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.755 arrival time 0.237 ------------------------------------------------------------------- slack 0.992 Slack (MET) : 0.992ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.474ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X91Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.189 -0.663 SLICE_X91Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.755 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.755 arrival time 0.237 ------------------------------------------------------------------- slack 0.992 Slack (MET) : 1.006ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.940ns (logic 0.209ns (22.242%) route 0.731ns (77.758%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.470ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.530 0.255 u_Axi_CDC/arFifo/p_0_in SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.189 -0.659 SLICE_X86Y105 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 0.751 arrival time 0.255 ------------------------------------------------------------------- slack 1.006 Slack (MET) : 1.006ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.940ns (logic 0.209ns (22.242%) route 0.731ns (77.758%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.470ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.530 0.255 u_Axi_CDC/arFifo/p_0_in SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.189 -0.659 SLICE_X86Y105 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 0.751 arrival time 0.255 ------------------------------------------------------------------- slack 1.006 Slack (MET) : 1.006ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.940ns (logic 0.209ns (22.242%) route 0.731ns (77.758%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.470ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.530 0.255 u_Axi_CDC/arFifo/p_0_in SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.189 -0.659 SLICE_X86Y105 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 0.751 arrival time 0.255 ------------------------------------------------------------------- slack 1.006 Slack (MET) : 1.006ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.940ns (logic 0.209ns (22.242%) route 0.731ns (77.758%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.470ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.530 0.255 u_Axi_CDC/arFifo/p_0_in SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.189 -0.659 SLICE_X86Y105 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 0.751 arrival time 0.255 ------------------------------------------------------------------- slack 1.006 Slack (MET) : 1.006ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.940ns (logic 0.209ns (22.242%) route 0.731ns (77.758%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.470ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.530 0.255 u_Axi_CDC/arFifo/p_0_in SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.189 -0.659 SLICE_X86Y105 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 0.751 arrival time 0.255 ------------------------------------------------------------------- slack 1.006 Slack (MET) : 1.031ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.957ns (logic 0.209ns (21.829%) route 0.748ns (78.171%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.478ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.548 0.272 u_Axi_CDC/wFifo/p_0_in SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.830 -0.478 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.189 -0.667 SLICE_X89Y125 FDCE (Remov_fdce_C_CLR) -0.092 -0.759 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 0.759 arrival time 0.272 ------------------------------------------------------------------- slack 1.031 Slack (MET) : 1.031ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.957ns (logic 0.209ns (21.829%) route 0.748ns (78.171%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.478ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.548 0.272 u_Axi_CDC/wFifo/p_0_in SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.830 -0.478 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.189 -0.667 SLICE_X89Y125 FDCE (Remov_fdce_C_CLR) -0.092 -0.759 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 0.759 arrival time 0.272 ------------------------------------------------------------------- slack 1.031 Slack (MET) : 1.031ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.957ns (logic 0.209ns (21.829%) route 0.748ns (78.171%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.478ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.548 0.272 u_Axi_CDC/wFifo/p_0_in SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.830 -0.478 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C clock pessimism -0.189 -0.667 SLICE_X89Y125 FDCE (Remov_fdce_C_CLR) -0.092 -0.759 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3] ------------------------------------------------------------------- required time 0.759 arrival time 0.272 ------------------------------------------------------------------- slack 1.031 Slack (MET) : 1.031ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.957ns (logic 0.209ns (21.829%) route 0.748ns (78.171%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.478ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.548 0.272 u_Axi_CDC/wFifo/p_0_in SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.830 -0.478 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.189 -0.667 SLICE_X89Y125 FDCE (Remov_fdce_C_CLR) -0.092 -0.759 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 0.759 arrival time 0.272 ------------------------------------------------------------------- slack 1.031 Slack (MET) : 1.031ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.957ns (logic 0.209ns (21.829%) route 0.748ns (78.171%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.478ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.548 0.272 u_Axi_CDC/wFifo/p_0_in SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.830 -0.478 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.189 -0.667 SLICE_X89Y125 FDCE (Remov_fdce_C_CLR) -0.092 -0.759 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 0.759 arrival time 0.272 ------------------------------------------------------------------- slack 1.031 Slack (MET) : 1.060ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.994ns (logic 0.209ns (21.025%) route 0.785ns (78.975%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.470ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.585 0.309 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.189 -0.659 SLICE_X86Y104 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.751 arrival time 0.309 ------------------------------------------------------------------- slack 1.060 Slack (MET) : 1.060ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.994ns (logic 0.209ns (21.025%) route 0.785ns (78.975%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.470ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.585 0.309 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.189 -0.659 SLICE_X86Y104 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.751 arrival time 0.309 ------------------------------------------------------------------- slack 1.060 Slack (MET) : 1.060ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.994ns (logic 0.209ns (21.025%) route 0.785ns (78.975%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.470ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.585 0.309 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.189 -0.659 SLICE_X86Y104 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.751 arrival time 0.309 ------------------------------------------------------------------- slack 1.060 Slack (MET) : 1.060ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.994ns (logic 0.209ns (21.025%) route 0.785ns (78.975%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.470ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.585 0.309 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.189 -0.659 SLICE_X86Y104 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.751 arrival time 0.309 ------------------------------------------------------------------- slack 1.060 Slack (MET) : 1.060ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.994ns (logic 0.209ns (21.025%) route 0.785ns (78.975%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.470ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.585 0.309 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.189 -0.659 SLICE_X86Y104 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.751 arrival time 0.309 ------------------------------------------------------------------- slack 1.060 Slack (MET) : 1.060ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.994ns (logic 0.209ns (21.025%) route 0.785ns (78.975%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.470ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.585 0.309 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.189 -0.659 SLICE_X86Y104 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.751 arrival time 0.309 ------------------------------------------------------------------- slack 1.060 Slack (MET) : 1.090ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.294ns (logic 0.246ns (19.011%) route 1.048ns (80.989%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.271ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.454ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.991 0.609 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.854 -0.454 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C clock pessimism 0.040 -0.414 SLICE_X64Y101 FDCE (Remov_fdce_C_CLR) -0.067 -0.481 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.481 arrival time 0.609 ------------------------------------------------------------------- slack 1.090 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: mlkem_clk To Clock: mlkem_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : 0 Failing Endpoints, Worst Slack 0.658ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.658ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.923ns (logic 0.227ns (24.583%) route 0.696ns (75.417%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.332ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.414 0.243 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X72Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C clock pessimism 0.040 -0.348 SLICE_X72Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.415 arrival time 0.243 ------------------------------------------------------------------- slack 0.658 Slack (MET) : 0.796ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism 0.040 -0.350 SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.417 arrival time 0.379 ------------------------------------------------------------------- slack 0.796 Slack (MET) : 0.796ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism 0.040 -0.350 SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.417 arrival time 0.379 ------------------------------------------------------------------- slack 0.796 Slack (MET) : 0.796ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism 0.040 -0.350 SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.417 arrival time 0.379 ------------------------------------------------------------------- slack 0.796 Slack (MET) : 0.796ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism 0.040 -0.350 SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.417 arrival time 0.379 ------------------------------------------------------------------- slack 0.796 Slack (MET) : 0.807ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C clock pessimism 0.040 -0.351 SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.418 arrival time 0.389 ------------------------------------------------------------------- slack 0.807 Slack (MET) : 0.807ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.196 -0.458 SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 0.550 arrival time 0.559 ------------------------------------------------------------------- slack 1.109 Slack (MET) : 1.109ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C clock pessimism 0.040 -0.351 SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.418 arrival time 0.389 ------------------------------------------------------------------- slack 0.807 Slack (MET) : 0.807ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.196 -0.458 SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 0.550 arrival time 0.559 ------------------------------------------------------------------- slack 1.109 Slack (MET) : 1.109ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.468ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism 0.040 -0.351 SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.418 arrival time 0.389 ------------------------------------------------------------------- slack 0.807 Slack (MET) : 0.807ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C clock pessimism -0.196 -0.458 SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2] ------------------------------------------------------------------- required time 0.550 arrival time 0.559 ------------------------------------------------------------------- slack 1.109 ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism 0.040 -0.351 SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.418 arrival time 0.389 ------------------------------------------------------------------- slack 0.807 Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/C clock pessimism 0.040 -0.351 SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.443 arrival time 0.389 ------------------------------------------------------------------- slack 0.832 Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/C clock pessimism 0.040 -0.351 SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.443 arrival time 0.389 ------------------------------------------------------------------- slack 0.832 Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/C clock pessimism 0.040 -0.351 SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.443 arrival time 0.389 ------------------------------------------------------------------- slack 0.832 Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/C clock pessimism 0.040 -0.351 SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.443 arrival time 0.389 ------------------------------------------------------------------- slack 0.832 Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/C clock pessimism 0.040 -0.345 SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.437 arrival time 0.447 ------------------------------------------------------------------- slack 0.884 Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/C clock pessimism 0.040 -0.345 SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.437 arrival time 0.447 ------------------------------------------------------------------- slack 0.884 Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/C clock pessimism 0.040 -0.345 SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.437 arrival time 0.447 ------------------------------------------------------------------- slack 0.884 Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/C clock pessimism 0.040 -0.345 SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.437 arrival time 0.447 ------------------------------------------------------------------- slack 0.884 Slack (MET) : 0.906ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.080ns (logic 0.226ns (20.934%) route 0.854ns (79.066%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.683 0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X93Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/C clock pessimism 0.040 -0.347 SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15] ------------------------------------------------------------------- required time 0.506 arrival time 0.400 ------------------------------------------------------------------- slack 0.906 Slack (MET) : 0.906ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.080ns (logic 0.226ns (20.934%) route 0.854ns (79.066%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.683 0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X93Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/C clock pessimism 0.040 -0.347 SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53] ------------------------------------------------------------------- required time 0.506 arrival time 0.400 ------------------------------------------------------------------- slack 0.906 Slack (MET) : 0.927ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X100Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/C clock pessimism 0.040 -0.341 SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16] ------------------------------------------------------------------- required time 0.475 arrival time 0.452 ------------------------------------------------------------------- slack 0.927 Slack (MET) : 0.927ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X100Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17]/C clock pessimism 0.040 -0.341 SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17] ------------------------------------------------------------------- required time 0.475 arrival time 0.452 ------------------------------------------------------------------- slack 0.927 Slack (MET) : 0.927ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X100Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18]/C clock pessimism 0.040 -0.341 SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18] ------------------------------------------------------------------- required time 0.475 arrival time 0.452 ------------------------------------------------------------------- slack 0.927 Slack (MET) : 0.927ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X100Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19]/C clock pessimism 0.040 -0.341 SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19] ------------------------------------------------------------------- required time 0.475 arrival time 0.452 ------------------------------------------------------------------- slack 0.927 Slack (MET) : 0.931ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X102Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0]/C clock pessimism 0.040 -0.339 SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0] ------------------------------------------------------------------- required time 0.473 arrival time 0.458 ------------------------------------------------------------------- slack 0.931 Slack (MET) : 0.931ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X102Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16]/C clock pessimism 0.040 -0.339 SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16] ------------------------------------------------------------------- required time 0.473 arrival time 0.458 ------------------------------------------------------------------- slack 0.931 Slack (MET) : 0.931ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X102Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17]/C clock pessimism 0.040 -0.339 SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17] ------------------------------------------------------------------- required time 0.473 arrival time 0.458 ------------------------------------------------------------------- slack 0.931 Slack (MET) : 0.931ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X102Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18]/C clock pessimism 0.040 -0.339 SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18] ------------------------------------------------------------------- required time 0.473 arrival time 0.458 ------------------------------------------------------------------- slack 0.931 Slack (MET) : 0.931ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[19]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X102Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[19]/C clock pessimism 0.040 -0.339 SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[19] ------------------------------------------------------------------- required time 0.473 arrival time 0.458 ------------------------------------------------------------------- slack 0.931 Slack (MET) : 0.935ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[12]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[12]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X100Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[12]/C clock pessimism 0.040 -0.341 SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[12] ------------------------------------------------------------------- required time 0.475 arrival time 0.460 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[13]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X100Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[13]/C clock pessimism 0.040 -0.341 SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[13] ------------------------------------------------------------------- required time 0.475 arrival time 0.460 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[14]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[14]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X100Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[14]/C clock pessimism 0.040 -0.341 SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[14] ------------------------------------------------------------------- required time 0.475 arrival time 0.460 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[15]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X100Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[15]/C clock pessimism 0.040 -0.341 SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[15] ------------------------------------------------------------------- required time 0.475 arrival time 0.460 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.936ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.113ns (logic 0.226ns (20.298%) route 0.887ns (79.702%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.717 0.433 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X99Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X99Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep/C clock pessimism 0.040 -0.344 SLICE_X99Y96 FDCE (Remov_fdce_C_CLR) -0.159 -0.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep ------------------------------------------------------------------- required time 0.503 arrival time 0.433 ------------------------------------------------------------------- slack 0.936 Slack (MET) : 0.936ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep__2/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.113ns (logic 0.226ns (20.298%) route 0.887ns (79.702%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.717 0.433 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X99Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep__2/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X99Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep__2/C clock pessimism 0.040 -0.344 SLICE_X99Y96 FDCE (Remov_fdce_C_CLR) -0.159 -0.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep__2 ------------------------------------------------------------------- required time 0.503 arrival time 0.433 ------------------------------------------------------------------- slack 0.936 Slack (MET) : 0.939ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[55]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.140ns (logic 0.226ns (19.816%) route 0.914ns (80.184%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.744 0.461 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/delay_reg[1] SLICE_X98Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[55]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X98Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[55]/C clock pessimism 0.040 -0.345 SLICE_X98Y91 FDCE (Remov_fdce_C_CLR) -0.134 -0.479 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[55] ------------------------------------------------------------------- required time 0.479 arrival time 0.461 ------------------------------------------------------------------- slack 0.939 Slack (MET) : 0.942ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[54]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.141ns (logic 0.226ns (19.800%) route 0.915ns (80.200%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.745 0.461 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X92Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[54]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X92Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[54]/C clock pessimism 0.040 -0.347 SLICE_X92Y90 FDCE (Remov_fdce_C_CLR) -0.134 -0.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[54] ------------------------------------------------------------------- required time 0.481 arrival time 0.461 ------------------------------------------------------------------- slack 0.942 Slack (MET) : 0.952ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[25]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.148ns (logic 0.226ns (19.693%) route 0.922ns (80.307%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.751 0.468 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X90Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X90Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[25]/C clock pessimism 0.040 -0.350 SLICE_X90Y91 FDCE (Remov_fdce_C_CLR) -0.134 -0.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[25] ------------------------------------------------------------------- required time 0.484 arrival time 0.468 ------------------------------------------------------------------- slack 0.952 Slack (MET) : 0.952ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[56]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.148ns (logic 0.226ns (19.693%) route 0.922ns (80.307%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.751 0.468 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X90Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[56]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X90Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[56]/C clock pessimism 0.040 -0.350 SLICE_X90Y91 FDCE (Remov_fdce_C_CLR) -0.134 -0.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[56] ------------------------------------------------------------------- required time 0.484 arrival time 0.468 ------------------------------------------------------------------- slack 0.952 Slack (MET) : 0.956ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[12]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X103Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[12]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X103Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[12]/C clock pessimism 0.040 -0.339 SLICE_X103Y98 FDCE (Remov_fdce_C_CLR) -0.159 -0.498 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[12] ------------------------------------------------------------------- required time 0.498 arrival time 0.458 ------------------------------------------------------------------- slack 0.956 Slack (MET) : 0.956ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[13]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X103Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X103Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[13]/C clock pessimism 0.040 -0.339 SLICE_X103Y98 FDCE (Remov_fdce_C_CLR) -0.159 -0.498 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[13] ------------------------------------------------------------------- required time 0.498 arrival time 0.458 ------------------------------------------------------------------- slack 0.956 Slack (MET) : 0.956ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[19]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.341ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X103Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X103Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[19]/C clock pessimism 0.040 -0.339 SLICE_X103Y98 FDCE (Remov_fdce_C_CLR) -0.159 -0.498 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[19] ------------------------------------------------------------------- required time 0.498 arrival time 0.458 ------------------------------------------------------------------- slack 0.956 Slack (MET) : 0.964ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[4]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.340ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[4]/C clock pessimism 0.040 -0.340 SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[4] ------------------------------------------------------------------- required time 0.474 arrival time 0.490 ------------------------------------------------------------------- slack 0.964 Slack (MET) : 0.964ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[5]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.340ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[5]/C clock pessimism 0.040 -0.340 SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[5] ------------------------------------------------------------------- required time 0.474 arrival time 0.490 ------------------------------------------------------------------- slack 0.964 Slack (MET) : 0.964ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[6]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.340ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[6]/C clock pessimism 0.040 -0.340 SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[6] ------------------------------------------------------------------- required time 0.474 arrival time 0.490 ------------------------------------------------------------------- slack 0.964 Slack (MET) : 0.964ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[7]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.340ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[7]/C clock pessimism 0.040 -0.340 SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[7] ------------------------------------------------------------------- required time 0.474 arrival time 0.490 ------------------------------------------------------------------- slack 0.964 Slack (MET) : 0.964ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[10]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.340ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[10]/C clock pessimism 0.040 -0.340 SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[10] ------------------------------------------------------------------- required time 0.474 arrival time 0.490 ------------------------------------------------------------------- slack 0.964 Slack (MET) : 0.964ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[11]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.340ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[11]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[11]/C clock pessimism 0.040 -0.340 SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[11] ------------------------------------------------------------------- required time 0.474 arrival time 0.490 ------------------------------------------------------------------- slack 0.964 Slack (MET) : 0.964ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[8]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.340ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[8]/C clock pessimism 0.040 -0.340 SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[8] ------------------------------------------------------------------- required time 0.474 arrival time 0.490 ------------------------------------------------------------------- slack 0.964 Slack (MET) : 0.964ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[9]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.340ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[9]/C clock pessimism 0.040 -0.340 SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[9] ------------------------------------------------------------------- required time 0.474 arrival time 0.490 ------------------------------------------------------------------- slack 0.964 Slack (MET) : 0.964ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[58]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.140ns (logic 0.226ns (19.816%) route 0.914ns (80.184%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.744 0.461 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X99Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[58]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X99Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[58]/C clock pessimism 0.040 -0.345 SLICE_X99Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.504 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[58] ------------------------------------------------------------------- required time 0.504 arrival time 0.461 ------------------------------------------------------------------- slack 0.964 >>>>>>> Stashed changes --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk To Clock: sys_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA <<<<<<< Updated upstream Hold : 0 Failing Endpoints, Worst Slack 0.761ns, Total Violation 0.000ns ======= Hold : 0 Failing Endpoints, Worst Slack 0.573ns, Total Violation 0.000ns >>>>>>> Stashed changes --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- <<<<<<< Updated upstream Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR ======= Slack (MET) : 0.573ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns ======= Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.019ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.196 -0.458 SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.525 arrival time 0.236 ------------------------------------------------------------------- slack 0.761 Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR ======= net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.213 -0.600 SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.667 arrival time -0.094 ------------------------------------------------------------------- slack 0.573 Slack (MET) : 0.573ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns ======= Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.019ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.196 -0.458 SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.525 arrival time 0.236 ------------------------------------------------------------------- slack 0.761 Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR ======= net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.213 -0.600 SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.667 arrival time -0.094 ------------------------------------------------------------------- slack 0.573 Slack (MET) : 0.573ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns ======= Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.019ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.196 -0.458 SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.525 arrival time 0.236 ------------------------------------------------------------------- slack 0.761 Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR ======= net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.213 -0.600 SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.667 arrival time -0.094 ------------------------------------------------------------------- slack 0.573 Slack (MET) : 0.837ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns ======= Data Path Delay: 0.812ns (logic 0.227ns (27.961%) route 0.585ns (72.039%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.192ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.445 0.192 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X64Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C clock pessimism -0.196 -0.458 SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 0.525 arrival time 0.236 ------------------------------------------------------------------- slack 0.761 Slack (MET) : 0.808ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.221 -0.482 SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.574 arrival time 0.234 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.221 -0.482 SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.574 arrival time 0.234 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.221 -0.482 SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.574 arrival time 0.234 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.221 -0.482 SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.574 arrival time 0.234 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.221 -0.482 SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.574 arrival time 0.234 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.808ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.221 -0.482 SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.574 arrival time 0.234 ------------------------------------------------------------------- slack 0.808 Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.196 -0.458 SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.550 arrival time 0.310 ------------------------------------------------------------------- slack 0.860 Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.196 -0.458 SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.550 arrival time 0.310 ------------------------------------------------------------------- slack 0.860 Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.196 -0.458 SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.550 arrival time 0.310 ------------------------------------------------------------------- slack 0.860 Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.196 -0.458 SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.550 arrival time 0.310 ------------------------------------------------------------------- slack 0.860 Slack (MET) : 0.871ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ======= net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X64Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.192 -0.577 SLICE_X64Y95 FDCE (Remov_fdce_C_CLR) -0.067 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.644 arrival time 0.192 ------------------------------------------------------------------- slack 0.837 Slack (MET) : 0.871ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.794ns (logic 0.246ns (30.972%) route 0.548ns (69.028%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.262 0.299 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X9Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X9Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.218 -0.480 SLICE_X9Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.572 arrival time 0.299 ------------------------------------------------------------------- slack 0.871 Slack (MET) : 0.871ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.972%) route 0.548ns (69.028%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.262 0.299 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X9Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X9Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.218 -0.480 SLICE_X9Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.572 arrival time 0.299 ------------------------------------------------------------------- slack 0.871 Slack (MET) : 0.872ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.218 -0.479 SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.571 arrival time 0.301 ------------------------------------------------------------------- slack 0.872 Slack (MET) : 0.872ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.218 -0.479 SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.571 arrival time 0.301 ------------------------------------------------------------------- slack 0.872 Slack (MET) : 0.872ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.218 -0.479 SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.571 arrival time 0.301 ------------------------------------------------------------------- slack 0.872 Slack (MET) : 0.890ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.864ns (logic 0.186ns (21.517%) route 0.678ns (78.483%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.613ns ======= Data Path Delay: 0.822ns (logic 0.227ns (27.605%) route 0.595ns (72.395%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.619ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 0.372 0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in SLICE_X112Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.456 0.203 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X65Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/C clock pessimism -0.192 -0.572 SLICE_X112Y66 FDCE (Remov_fdce_C_CLR) -0.067 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0] ------------------------------------------------------------------- required time 0.639 arrival time 0.251 ------------------------------------------------------------------- slack 0.890 Slack (MET) : 0.914ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ======= net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X65Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/C clock pessimism -0.192 -0.576 SLICE_X65Y99 FDCE (Remov_fdce_C_CLR) -0.092 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.668 arrival time 0.203 ------------------------------------------------------------------- slack 0.871 Slack (MET) : 0.871ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C >>>>>>> Stashed changes (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.786ns (logic 0.249ns (31.687%) route 0.537ns (68.313%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.377ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns ======= Data Path Delay: 0.822ns (logic 0.227ns (27.605%) route 0.595ns (72.395%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.456 0.203 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X65Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X65Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/C clock pessimism -0.192 -0.576 SLICE_X65Y99 FDCE (Remov_fdce_C_CLR) -0.092 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.668 arrival time 0.203 ------------------------------------------------------------------- slack 0.871 Slack (MET) : 0.912ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.189 -0.666 SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.733 arrival time 0.179 ------------------------------------------------------------------- slack 0.912 Slack (MET) : 0.912ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.189 -0.666 SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.733 arrival time 0.179 ------------------------------------------------------------------- slack 0.912 Slack (MET) : 0.912ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.189 -0.666 SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.733 arrival time 0.179 ------------------------------------------------------------------- slack 0.912 Slack (MET) : 0.912ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C clock pessimism -0.189 -0.666 SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 0.733 arrival time 0.179 ------------------------------------------------------------------- slack 0.912 Slack (MET) : 0.919ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.023ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.209 -0.670 SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.737 arrival time 0.182 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.919ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.023ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.209 -0.670 SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.737 arrival time 0.182 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.919ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.023ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.209 -0.670 SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.737 arrival time 0.182 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.919ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.023ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.209 -0.670 SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.737 arrival time 0.182 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.971ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.922ns (logic 0.227ns (24.621%) route 0.695ns (75.379%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.556 0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X66Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X66Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/C clock pessimism -0.213 -0.601 SLICE_X66Y91 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.668 arrival time 0.303 ------------------------------------------------------------------- slack 0.971 Slack (MET) : 0.971ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.922ns (logic 0.227ns (24.621%) route 0.695ns (75.379%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.556 0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X66Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X66Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/C clock pessimism -0.213 -0.601 SLICE_X66Y91 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- required time 0.668 arrival time 0.303 ------------------------------------------------------------------- slack 0.971 Slack (MET) : 0.982ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.939ns (logic 0.246ns (26.196%) route 0.693ns (73.804%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.024ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.371 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X125Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR ======= net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.407 0.246 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X92Y112 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.931 -0.377 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X125Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/C clock pessimism -0.192 -0.569 SLICE_X125Y65 FDCE (Remov_fdce_C_CLR) -0.165 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253] ------------------------------------------------------------------- required time 0.734 arrival time 0.179 ------------------------------------------------------------------- slack 0.914 Slack (MET) : 0.918ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 1.021ns (logic 0.246ns (24.092%) route 0.775ns (75.908%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.336ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.489 0.526 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X11Y53 FDCE f u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.972 -0.336 u_Axi_CDC/wFifo/sys_clk SLICE_X11Y53 FDCE r u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/C clock pessimism 0.037 -0.299 SLICE_X11Y53 FDCE (Remov_fdce_C_CLR) -0.092 -0.391 u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.391 arrival time 0.526 ------------------------------------------------------------------- slack 0.918 Slack (MET) : 0.928ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk SLICE_X9Y44 FDCE r u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.218 -0.479 SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.571 arrival time 0.357 ------------------------------------------------------------------- slack 0.928 Slack (MET) : 0.928ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk SLICE_X9Y44 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/C clock pessimism -0.218 -0.479 SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.571 arrival time 0.357 ------------------------------------------------------------------- slack 0.928 Slack (MET) : 0.928ns (arrival time - required time) ======= net (fo=9971, routed) 0.848 -0.460 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y112 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.209 -0.669 SLICE_X92Y112 FDCE (Remov_fdce_C_CLR) -0.067 -0.736 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.736 arrival time 0.246 ------------------------------------------------------------------- slack 0.982 Slack (MET) : 0.982ns (arrival time - required time) >>>>>>> Stashed changes Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns ======= Data Path Delay: 0.939ns (logic 0.246ns (26.196%) route 0.693ns (73.804%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.024ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR ======= net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.407 0.246 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X92Y112 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk SLICE_X9Y44 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/C clock pessimism -0.218 -0.479 SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.571 arrival time 0.357 ------------------------------------------------------------------- slack 0.928 Slack (MET) : 0.928ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR ======= net (fo=9971, routed) 0.848 -0.460 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y112 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.209 -0.669 SLICE_X92Y112 FDCE (Remov_fdce_C_CLR) -0.067 -0.736 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.736 arrival time 0.246 ------------------------------------------------------------------- slack 0.982 Slack (MET) : 0.987ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk SLICE_X9Y44 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/C clock pessimism -0.218 -0.479 SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.571 arrival time 0.357 ------------------------------------------------------------------- slack 0.928 Slack (MET) : 0.932ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.817ns (logic 0.249ns (30.489%) route 0.568ns (69.511%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.025ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.606ns ======= Data Path Delay: 0.940ns (logic 0.227ns (24.146%) route 0.713ns (75.854%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.382ns Source Clock Delay (SCD): -0.619ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.402 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X112Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.574 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X54Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X112Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/C clock pessimism -0.192 -0.581 SLICE_X112Y75 FDCE (Remov_fdce_C_CLR) -0.140 -0.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10] ------------------------------------------------------------------- required time 0.721 arrival time 0.210 ------------------------------------------------------------------- slack 0.932 Slack (MET) : 0.935ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/CLR ======= net (fo=9971, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.192 -0.574 SLICE_X54Y89 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.666 arrival time 0.321 ------------------------------------------------------------------- slack 0.987 Slack (MET) : 0.987ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.613ns ======= Data Path Delay: 0.940ns (logic 0.227ns (24.146%) route 0.713ns (75.854%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.382ns Source Clock Delay (SCD): -0.619ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.574 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X54Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C clock pessimism -0.192 -0.571 SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0] ------------------------------------------------------------------- required time 0.638 arrival time 0.297 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C ======= net (fo=9971, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.192 -0.574 SLICE_X54Y89 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.666 arrival time 0.321 ------------------------------------------------------------------- slack 0.987 Slack (MET) : 0.987ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.940ns (logic 0.227ns (24.146%) route 0.713ns (75.854%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.382ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.574 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X54Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.192 -0.574 SLICE_X54Y89 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.666 arrival time 0.321 ------------------------------------------------------------------- slack 0.987 Slack (MET) : 0.987ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.940ns (logic 0.227ns (24.146%) route 0.713ns (75.854%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.382ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.574 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X54Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.192 -0.574 SLICE_X54Y89 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.666 arrival time 0.321 ------------------------------------------------------------------- slack 0.987 Slack (MET) : 0.987ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C >>>>>>> Stashed changes (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.613ns ======= Data Path Delay: 0.940ns (logic 0.227ns (24.146%) route 0.713ns (75.854%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.382ns Source Clock Delay (SCD): -0.619ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.574 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X54Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C clock pessimism -0.192 -0.571 SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1] ------------------------------------------------------------------- required time 0.638 arrival time 0.297 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/CLR ======= net (fo=9971, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.192 -0.574 SLICE_X54Y89 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.666 arrival time 0.321 ------------------------------------------------------------------- slack 0.987 Slack (MET) : 0.987ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.613ns ======= Data Path Delay: 0.940ns (logic 0.227ns (24.146%) route 0.713ns (75.854%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.382ns Source Clock Delay (SCD): -0.619ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.574 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X54Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C clock pessimism -0.192 -0.571 SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2] ------------------------------------------------------------------- required time 0.638 arrival time 0.297 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/CLR ======= net (fo=9971, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.192 -0.574 SLICE_X54Y89 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.666 arrival time 0.321 ------------------------------------------------------------------- slack 0.987 Slack (MET) : 1.004ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns ======= Data Path Delay: 0.955ns (logic 0.227ns (23.771%) route 0.728ns (76.229%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.589 0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X68Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C clock pessimism -0.192 -0.571 SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3] ------------------------------------------------------------------- required time 0.638 arrival time 0.297 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.944ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/CLR ======= net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X68Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C clock pessimism -0.213 -0.601 SLICE_X68Y92 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 0.668 arrival time 0.336 ------------------------------------------------------------------- slack 1.004 Slack (MET) : 1.014ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.815ns (logic 0.249ns (30.565%) route 0.566ns (69.435%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns ======= Data Path Delay: 0.976ns (logic 0.246ns (25.203%) route 0.730ns (74.797%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.400 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X127Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/CLR ======= net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.444 0.283 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y127 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X127Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/C clock pessimism -0.192 -0.570 SLICE_X127Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217] ------------------------------------------------------------------- required time 0.735 arrival time 0.208 ------------------------------------------------------------------- slack 0.944 Slack (MET) : 0.944ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.815ns (logic 0.249ns (30.565%) route 0.566ns (69.435%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.400 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X127Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X127Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/C clock pessimism -0.192 -0.570 SLICE_X127Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223] ------------------------------------------------------------------- required time 0.735 arrival time 0.208 ------------------------------------------------------------------- slack 0.944 Slack (MET) : 0.948ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/C clock pessimism -0.192 -0.570 SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233] ------------------------------------------------------------------- required time 0.735 arrival time 0.213 ------------------------------------------------------------------- slack 0.948 Slack (MET) : 0.948ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/C clock pessimism -0.192 -0.570 SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234] ------------------------------------------------------------------- required time 0.735 arrival time 0.213 ------------------------------------------------------------------- slack 0.948 Slack (MET) : 0.948ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/C clock pessimism -0.192 -0.570 SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236] ------------------------------------------------------------------- required time 0.735 arrival time 0.213 ------------------------------------------------------------------- slack 0.948 Slack (MET) : 0.948ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/C clock pessimism -0.192 -0.570 SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237] ------------------------------------------------------------------- required time 0.735 arrival time 0.213 ------------------------------------------------------------------- slack 0.948 Slack (MET) : 0.948ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.378ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/C clock pessimism -0.192 -0.570 SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239] ------------------------------------------------------------------- required time 0.735 arrival time 0.213 ------------------------------------------------------------------- slack 0.948 Slack (MET) : 0.952ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.822ns (logic 0.249ns (30.308%) route 0.573ns (69.692%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.407 0.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X125Y67 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X125Y67 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/C clock pessimism -0.192 -0.571 SLICE_X125Y67 FDCE (Remov_fdce_C_CLR) -0.165 -0.736 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37] ------------------------------------------------------------------- required time 0.736 arrival time 0.215 ------------------------------------------------------------------- slack 0.952 Slack (MET) : 0.955ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ======= net (fo=9971, routed) 0.833 -0.475 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y127 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/C clock pessimism -0.189 -0.664 SLICE_X88Y127 FDCE (Remov_fdce_C_CLR) -0.067 -0.731 u_Axi_CDC/wFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.731 arrival time 0.283 ------------------------------------------------------------------- slack 1.014 Slack (MET) : 1.014ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.925ns (logic 0.246ns (26.589%) route 0.679ns (73.411%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns ======= Data Path Delay: 0.976ns (logic 0.246ns (25.203%) route 0.730ns (74.797%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.393 0.430 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ======= net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.444 0.283 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y127 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.196 -0.458 SLICE_X12Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.525 arrival time 0.430 ------------------------------------------------------------------- slack 0.955 Slack (MET) : 0.955ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ======= net (fo=9971, routed) 0.833 -0.475 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y127 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/C clock pessimism -0.189 -0.664 SLICE_X88Y127 FDCE (Remov_fdce_C_CLR) -0.067 -0.731 u_Axi_CDC/wFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.731 arrival time 0.283 ------------------------------------------------------------------- slack 1.014 Slack (MET) : 1.014ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.925ns (logic 0.246ns (26.589%) route 0.679ns (73.411%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.262ns Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): 0.196ns ======= Data Path Delay: 0.976ns (logic 0.246ns (25.203%) route 0.730ns (74.797%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, routed) 0.393 0.430 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ======= net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.444 0.283 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y127 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.196 -0.458 SLICE_X12Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.525 arrival time 0.430 ------------------------------------------------------------------- slack 0.955 Slack (MET) : 0.957ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/CLR ======= net (fo=9971, routed) 0.833 -0.475 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y127 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/C clock pessimism -0.189 -0.664 SLICE_X88Y127 FDCE (Remov_fdce_C_CLR) -0.067 -0.731 u_Axi_CDC/wFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.731 arrival time 0.283 ------------------------------------------------------------------- slack 1.014 Slack (MET) : 1.014ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.817ns (logic 0.249ns (30.489%) route 0.568ns (69.511%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.025ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.402 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X113Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/C clock pessimism -0.192 -0.581 SLICE_X113Y75 FDCE (Remov_fdce_C_CLR) -0.165 -0.746 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5] ------------------------------------------------------------------- required time 0.746 arrival time 0.210 ------------------------------------------------------------------- slack 0.957 Slack (MET) : 0.957ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.830ns (logic 0.249ns (29.992%) route 0.581ns (70.008%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.376ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.415 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X131Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.932 -0.376 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X131Y64 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/C clock pessimism -0.192 -0.568 SLICE_X131Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90] ------------------------------------------------------------------- required time 0.733 arrival time 0.224 ------------------------------------------------------------------- slack 0.957 Slack (MET) : 0.957ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.830ns (logic 0.249ns (29.992%) route 0.581ns (70.008%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.376ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.415 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X131Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.932 -0.376 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X131Y64 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/C clock pessimism -0.192 -0.568 SLICE_X131Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93] ------------------------------------------------------------------- required time 0.733 arrival time 0.224 ------------------------------------------------------------------- slack 0.957 Slack (MET) : 0.960ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns ======= Data Path Delay: 0.976ns (logic 0.246ns (25.203%) route 0.730ns (74.797%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in SLICE_X113Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR ======= net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.444 0.283 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y127 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X113Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/C clock pessimism -0.192 -0.571 SLICE_X113Y65 FDCE (Remov_fdce_C_CLR) -0.092 -0.663 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2] ------------------------------------------------------------------- required time 0.663 arrival time 0.297 ------------------------------------------------------------------- slack 0.960 Slack (MET) : 0.961ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/CLR ======= net (fo=9971, routed) 0.833 -0.475 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y127 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/C clock pessimism -0.189 -0.664 SLICE_X88Y127 FDCE (Remov_fdce_C_CLR) -0.067 -0.731 u_Axi_CDC/wFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- required time 0.731 arrival time 0.283 ------------------------------------------------------------------- slack 1.014 Slack (MET) : 1.025ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns ======= Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/C clock pessimism -0.192 -0.575 SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1] ------------------------------------------------------------------- required time 0.740 arrival time 0.221 ------------------------------------------------------------------- slack 0.961 Slack (MET) : 0.961ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/CLR ======= net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.213 -0.601 SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.668 arrival time 0.356 ------------------------------------------------------------------- slack 1.025 Slack (MET) : 1.025ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns ======= Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/C clock pessimism -0.192 -0.575 SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2] ------------------------------------------------------------------- required time 0.740 arrival time 0.221 ------------------------------------------------------------------- slack 0.961 Slack (MET) : 0.961ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/CLR ======= net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.213 -0.601 SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.668 arrival time 0.356 ------------------------------------------------------------------- slack 1.025 Slack (MET) : 1.025ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns ======= Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/C clock pessimism -0.192 -0.575 SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3] ------------------------------------------------------------------- required time 0.740 arrival time 0.221 ------------------------------------------------------------------- slack 0.961 Slack (MET) : 0.961ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/CLR ======= net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.213 -0.601 SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.668 arrival time 0.356 ------------------------------------------------------------------- slack 1.025 Slack (MET) : 1.025ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns ======= Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/C clock pessimism -0.192 -0.575 SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4] ------------------------------------------------------------------- required time 0.740 arrival time 0.221 ------------------------------------------------------------------- slack 0.961 Slack (MET) : 0.961ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/CLR ======= net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.213 -0.601 SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.668 arrival time 0.356 ------------------------------------------------------------------- slack 1.025 Slack (MET) : 1.025ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR >>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) <<<<<<< Updated upstream Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns ======= Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/CLR ======= net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/C clock pessimism -0.192 -0.575 SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5] ------------------------------------------------------------------- required time 0.740 arrival time 0.221 ------------------------------------------------------------------- slack 0.961 ======= net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.213 -0.601 SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.668 arrival time 0.356 ------------------------------------------------------------------- slack 1.025 Slack (MET) : 1.025ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.213 -0.601 SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.668 arrival time 0.356 ------------------------------------------------------------------- slack 1.025 Slack (MET) : 1.025ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.213 -0.601 SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.668 arrival time 0.356 ------------------------------------------------------------------- slack 1.025 Slack (MET) : 1.025ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.213 -0.601 SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.668 arrival time 0.356 ------------------------------------------------------------------- slack 1.025 Slack (MET) : 1.058ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 1.017ns (logic 0.246ns (24.197%) route 0.771ns (75.803%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.484 0.324 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X92Y110 FDCE f u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.850 -0.458 u_Axi_CDC/awFifo/sys_clk SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.209 -0.667 SLICE_X92Y110 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.734 arrival time 0.324 ------------------------------------------------------------------- slack 1.058 Slack (MET) : 1.058ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 1.017ns (logic 0.246ns (24.197%) route 0.771ns (75.803%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.484 0.324 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X92Y110 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.850 -0.458 u_Axi_CDC/awFifo/sys_clk SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/C clock pessimism -0.209 -0.667 SLICE_X92Y110 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.734 arrival time 0.324 ------------------------------------------------------------------- slack 1.058 Slack (MET) : 1.058ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 1.017ns (logic 0.246ns (24.197%) route 0.771ns (75.803%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.484 0.324 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X92Y110 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.850 -0.458 u_Axi_CDC/awFifo/sys_clk SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.209 -0.667 SLICE_X92Y110 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.734 arrival time 0.324 ------------------------------------------------------------------- slack 1.058 Slack (MET) : 1.058ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 1.017ns (logic 0.246ns (24.197%) route 0.771ns (75.803%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.484 0.324 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X92Y110 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.850 -0.458 u_Axi_CDC/awFifo/sys_clk SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.209 -0.667 SLICE_X92Y110 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.734 arrival time 0.324 ------------------------------------------------------------------- slack 1.058 Slack (MET) : 1.083ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 1.017ns (logic 0.246ns (24.197%) route 0.771ns (75.803%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.484 0.324 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X93Y110 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.850 -0.458 u_Axi_CDC/awFifo/sys_clk SLICE_X93Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.209 -0.667 SLICE_X93Y110 FDCE (Remov_fdce_C_CLR) -0.092 -0.759 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.759 arrival time 0.324 ------------------------------------------------------------------- slack 1.083 >>>>>>> Stashed changes -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: cpu_clk Max Delay 0 Endpoints Min Delay 59 Endpoints -------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[3]/D <<<<<<< Updated upstream (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.735ns (logic 0.467ns (63.560%) route 0.268ns (36.440%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.495ns Source Clock Delay (SCD): -2.110ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.669ns (logic 0.518ns (77.393%) route 0.151ns (22.607%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.396ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.697ns Source Clock Delay (SCD): -2.301ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.718 -2.110 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X49Y58 FDRE r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y58 FDRE (Prop_fdre_C_Q) 0.367 -1.743 r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/Q net (fo=3, routed) 0.268 -1.476 u_snix_axil_cdma_mux_8ch/ch_done_reg[2]_0 SLICE_X49Y56 LUT5 (Prop_lut5_I0_O) 0.100 -1.376 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O net (fo=1, routed) 0.000 -1.376 u_cpu/u_csr/interrupt[1] SLICE_X49Y56 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D ======= net (fo=9971, routed) 1.527 -2.301 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X74Y119 FDRE r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y119 FDRE (Prop_fdre_C_Q) 0.418 -1.883 r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/Q net (fo=3, routed) 0.151 -1.732 u_snix_axil_cdma_mux_8ch/ch_done_reg[2]_0 SLICE_X75Y119 LUT5 (Prop_lut5_I1_O) 0.100 -1.632 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O net (fo=1, routed) 0.000 -1.632 u_cpu/u_csr/interrupt[1] SLICE_X75Y119 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.847 -2.495 u_cpu/u_csr/cpu_clk SLICE_X49Y56 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.555ns (logic 0.418ns (75.283%) route 0.137ns (24.717%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.209ns Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.998 -1.831 u_Axi_CDC/rFifo/sys_clk SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=2, routed) 0.137 -1.275 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2] SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.559ns (logic 0.418ns (74.744%) route 0.141ns (25.256%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.209ns Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.998 -1.831 u_Axi_CDC/rFifo/sys_clk SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.141 -1.271 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0] SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.644ns (logic 0.367ns (56.976%) route 0.277ns (43.024%)) Logic Levels: 0 Clock Path Skew: -0.377ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.209ns Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/awFifo/sys_clk SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X9Y45 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.277 -1.188 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[0] SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.656ns (logic 0.385ns (58.677%) route 0.271ns (41.323%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.209ns Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.998 -1.831 u_Axi_CDC/rFifo/sys_clk SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.385 -1.446 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=4, routed) 0.271 -1.175 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.645 -2.697 u_cpu/u_csr/cpu_clk SLICE_X75Y119 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C >>>>>>> Stashed changes Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) <<<<<<< Updated upstream Data Path Delay: 0.673ns (logic 0.418ns (62.094%) route 0.255ns (37.906%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.210ns Source Clock Delay (SCD): -1.832ns ======= Data Path Delay: 0.682ns (logic 0.418ns (61.288%) route 0.264ns (38.712%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.694ns Source Clock Delay (SCD): -2.300ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/wFifo/sys_clk SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.255 -1.159 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ======= net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.418 -1.882 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.264 -1.618 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.675ns (logic 0.418ns (61.898%) route 0.257ns (38.102%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.209ns Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.672ns (logic 0.418ns (62.183%) route 0.254ns (37.817%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.685ns Source Clock Delay (SCD): -2.290ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.998 -1.831 u_Axi_CDC/rFifo/sys_clk SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.257 -1.155 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1] SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ======= net (fo=9971, routed) 1.538 -2.290 u_Axi_CDC/bFifo/sys_clk SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y121 FDCE (Prop_fdce_C_Q) 0.418 -1.872 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.254 -1.618 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.686ns (logic 0.418ns (60.908%) route 0.268ns (39.092%)) Logic Levels: 0 Clock Path Skew: -0.379ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.211ns Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/arFifo/sys_clk SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X16Y46 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.268 -1.145 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.698ns (logic 0.385ns (55.120%) route 0.313ns (44.880%)) Logic Levels: 0 Clock Path Skew: -0.377ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.211ns Source Clock Delay (SCD): -1.834ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.995 -1.834 u_Axi_CDC/bFifo/sys_clk SLICE_X8Y40 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y40 FDCE (Prop_fdce_C_Q) 0.385 -1.449 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.313 -1.135 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.715ns (logic 0.418ns (58.464%) route 0.297ns (41.536%)) Logic Levels: 0 Clock Path Skew: -0.377ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.211ns Source Clock Delay (SCD): -1.834ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.995 -1.834 u_Axi_CDC/bFifo/sys_clk SLICE_X8Y40 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y40 FDCE (Prop_fdce_C_Q) 0.418 -1.416 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.297 -1.119 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.657 -2.685 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C >>>>>>> Stashed changes Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) <<<<<<< Updated upstream Data Path Delay: 0.760ns (logic 0.385ns (50.673%) route 0.375ns (49.327%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.210ns Source Clock Delay (SCD): -1.832ns ======= Data Path Delay: 0.776ns (logic 0.385ns (49.618%) route 0.391ns (50.382%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.694ns Source Clock Delay (SCD): -2.300ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/wFifo/sys_clk SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.385 -1.447 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.375 -1.072 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ======= net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.385 -1.915 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.391 -1.524 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.798ns (logic 0.367ns (46.017%) route 0.431ns (53.983%)) Logic Levels: 0 Clock Path Skew: -0.377ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.209ns Source Clock Delay (SCD): -1.832ns ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.803ns (logic 0.418ns (52.045%) route 0.385ns (47.955%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.674ns Source Clock Delay (SCD): -2.280ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/awFifo/sys_clk SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X9Y45 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.431 -1.034 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1] SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ======= net (fo=9971, routed) 1.548 -2.280 u_Axi_CDC/awFifo/sys_clk SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y110 FDCE (Prop_fdce_C_Q) 0.418 -1.862 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.385 -1.477 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[0] SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.815ns (logic 0.385ns (47.225%) route 0.430ns (52.775%)) Logic Levels: 0 Clock Path Skew: -0.379ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.211ns Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/arFifo/sys_clk SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X16Y46 FDCE (Prop_fdce_C_Q) 0.385 -1.447 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.430 -1.016 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.828ns (logic 0.418ns (50.501%) route 0.410ns (49.499%)) Logic Levels: 0 Clock Path Skew: -0.377ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.211ns Source Clock Delay (SCD): -1.834ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.995 -1.834 u_Axi_CDC/bFifo/sys_clk SLICE_X8Y40 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y40 FDCE (Prop_fdce_C_Q) 0.418 -1.416 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.410 -1.006 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C >>>>>>> Stashed changes Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D <<<<<<< Updated upstream (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.826ns (logic 0.418ns (50.576%) route 0.408ns (49.424%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.210ns Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.837ns (logic 0.418ns (49.921%) route 0.419ns (50.079%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.694ns Source Clock Delay (SCD): -2.300ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/wFifo/sys_clk SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.408 -1.005 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[3] SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ======= net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.418 -1.882 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.419 -1.463 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[3] SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.838ns (logic 0.418ns (49.893%) route 0.420ns (50.107%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.674ns Source Clock Delay (SCD): -2.280ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.548 -2.280 u_Axi_CDC/awFifo/sys_clk SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y110 FDCE (Prop_fdce_C_Q) 0.418 -1.862 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.420 -1.442 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1] SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C >>>>>>> Stashed changes Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D <<<<<<< Updated upstream (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.890ns (logic 0.367ns (41.256%) route 0.523ns (58.744%)) Logic Levels: 0 Clock Path Skew: -0.377ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.209ns Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.857ns (logic 0.367ns (42.833%) route 0.490ns (57.167%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.674ns Source Clock Delay (SCD): -2.280ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/awFifo/sys_clk SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X9Y45 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.523 -0.942 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2] SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ======= net (fo=9971, routed) 1.548 -2.280 u_Axi_CDC/awFifo/sys_clk SLICE_X93Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y110 FDCE (Prop_fdce_C_Q) 0.367 -1.913 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.490 -1.423 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2] SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C >>>>>>> Stashed changes Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D <<<<<<< Updated upstream (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.950ns (logic 0.418ns (44.008%) route 0.532ns (55.992%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.210ns Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.968ns (logic 0.418ns (43.176%) route 0.550ns (56.824%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.694ns Source Clock Delay (SCD): -2.300ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/wFifo/sys_clk SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.532 -0.882 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ======= net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.418 -1.882 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.550 -1.332 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.959ns (logic 0.418ns (43.591%) route 0.541ns (56.409%)) Logic Levels: 0 Clock Path Skew: -0.379ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.211ns Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.007ns (logic 0.385ns (38.250%) route 0.622ns (61.750%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.685ns Source Clock Delay (SCD): -2.290ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/arFifo/sys_clk SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X16Y46 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.541 -0.873 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ======= net (fo=9971, routed) 1.538 -2.290 u_Axi_CDC/bFifo/sys_clk SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y121 FDCE (Prop_fdce_C_Q) 0.385 -1.905 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.622 -1.283 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.657 -2.685 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.033ns (logic 0.418ns (40.449%) route 0.615ns (59.551%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.685ns Source Clock Delay (SCD): -2.290ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.538 -2.290 u_Axi_CDC/bFifo/sys_clk SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y121 FDCE (Prop_fdce_C_Q) 0.418 -1.872 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.615 -1.256 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.657 -2.685 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.901ns (logic 0.337ns (37.384%) route 0.564ns (62.616%)) Logic Levels: 0 Clock Path Skew: -0.556ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.692ns Source Clock Delay (SCD): -2.135ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.693 -2.135 u_Axi_CDC/arFifo/sys_clk SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.337 -1.798 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.564 -1.234 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.650 -2.692 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C >>>>>>> Stashed changes Slack: inf Source: u_confreg/int_out_or_q2_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) <<<<<<< Updated upstream Data Path Delay: 1.250ns (logic 0.337ns (26.970%) route 0.913ns (73.030%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.219ns Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.998 -1.831 u_confreg/sys_clk SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y47 FDRE (Prop_fdre_C_Q) 0.337 -1.494 r u_confreg/int_out_or_q2_reg/Q net (fo=1, routed) 0.913 -0.581 u_cpu/u_csr/interrupt[0] SLICE_X9Y33 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.123 -2.219 u_cpu/u_csr/cpu_clk SLICE_X9Y33 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C Slack: inf Source: u_matmul_axi_slave/done_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.161ns (logic 0.367ns (16.979%) route 1.794ns (83.021%)) Logic Levels: 0 Clock Path Skew: -0.457ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.494ns Source Clock Delay (SCD): -2.036ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.792 -2.036 u_matmul_axi_slave/sys_clk SLICE_X41Y78 FDRE r u_matmul_axi_slave/done_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y78 FDRE (Prop_fdre_C_Q) 0.367 -1.669 r u_matmul_axi_slave/done_reg/Q net (fo=11, routed) 1.794 0.125 u_cpu/u_csr/interrupt[2] SLICE_X47Y52 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.848 -2.494 u_cpu/u_csr/cpu_clk SLICE_X47Y52 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.190ns (logic 1.062ns (48.490%) route 1.128ns (51.510%)) Logic Levels: 0 Clock Path Skew: -0.210ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.218ns Source Clock Delay (SCD): -2.007ns ======= Data Path Delay: 1.082ns (logic 0.367ns (33.922%) route 0.715ns (66.078%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.691ns Source Clock Delay (SCD): -2.302ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.821 -2.007 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y54 RAMD32 (Prop_ramd32_CLK_O) 1.062 -0.945 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O net (fo=1, routed) 1.128 0.183 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] SLICE_X16Y34 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D ======= net (fo=9971, routed) 1.526 -2.302 u_confreg/sys_clk SLICE_X78Y141 FDRE r u_confreg/int_out_or_q2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X78Y141 FDRE (Prop_fdre_C_Q) 0.367 -1.935 r u_confreg/int_out_or_q2_reg/Q net (fo=1, routed) 0.715 -1.220 u_cpu/u_csr/interrupt[0] SLICE_X84Y149 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.124 -2.218 u_Axi_CDC/rFifo/cpu_clk SLICE_X16Y34 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.232ns (logic 1.083ns (48.530%) route 1.149ns (51.470%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.224ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.651 -2.691 u_cpu/u_csr/cpu_clk SLICE_X84Y149 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.927ns (logic 0.367ns (39.581%) route 0.560ns (60.419%)) Logic Levels: 0 Clock Path Skew: -0.556ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.692ns Source Clock Delay (SCD): -2.135ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.821 -2.007 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) 1.083 -0.924 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 1.149 0.224 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D ======= net (fo=9971, routed) 1.693 -2.135 u_Axi_CDC/arFifo/sys_clk SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.367 -1.768 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.560 -1.208 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.343ns (logic 1.056ns (45.069%) route 1.287ns (54.931%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.228ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.650 -2.692 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.999ns (logic 0.418ns (41.855%) route 0.581ns (58.145%)) Logic Levels: 0 Clock Path Skew: -0.558ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.674ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.821 -2.007 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.951 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 1.287 0.336 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D ======= net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.418 -1.697 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=2, routed) 0.581 -1.117 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2] SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.114 -2.228 u_Axi_CDC/rFifo/cpu_clk SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.010ns (logic 0.418ns (41.371%) route 0.592ns (58.629%)) Logic Levels: 0 Clock Path Skew: -0.558ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.674ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.418 -1.697 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.592 -1.105 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1] SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.033ns (logic 0.367ns (35.528%) route 0.666ns (64.472%)) Logic Levels: 0 Clock Path Skew: -0.556ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.692ns Source Clock Delay (SCD): -2.135ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.693 -2.135 u_Axi_CDC/arFifo/sys_clk SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.367 -1.768 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.666 -1.102 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.650 -2.692 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.099ns (logic 0.385ns (35.032%) route 0.714ns (64.968%)) Logic Levels: 0 Clock Path Skew: -0.558ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.674ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.385 -1.730 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=4, routed) 0.714 -1.016 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.234ns (logic 0.418ns (33.873%) route 0.816ns (66.127%)) Logic Levels: 0 Clock Path Skew: -0.558ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.674ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk SLICE_X62Y94 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y94 FDCE (Prop_fdce_C_Q) 0.418 -1.697 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.816 -0.881 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0] SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.609ns (logic 0.385ns (23.934%) route 1.224ns (76.066%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.670ns Source Clock Delay (SCD): -2.276ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.552 -2.276 u_fft_mlkem_axi_slave/sys_clk SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y110 FDCE (Prop_fdce_C_Q) 0.385 -1.891 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/Q net (fo=1, routed) 1.224 -0.667 u_cpu/u_csr/interrupt[3] SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.672 -2.670 u_cpu/u_csr/cpu_clk SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[5]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.478ns (logic 0.388ns (26.258%) route 1.090ns (73.742%)) Logic Levels: 0 Clock Path Skew: 0.146ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.648 -0.614 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X62Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y92 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.226 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O net (fo=1, routed) 1.090 0.863 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.522ns (logic 0.386ns (25.368%) route 1.136ns (74.632%)) Logic Levels: 0 Clock Path Skew: 0.112ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.193 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 1.136 0.942 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.546ns (logic 0.394ns (25.488%) route 1.152ns (74.512%)) Logic Levels: 0 Clock Path Skew: 0.100ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.471ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.177 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 1.152 0.974 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C >>>>>>> Stashed changes Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) <<<<<<< Updated upstream Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.348ns (logic 1.084ns (46.168%) route 1.264ns (53.832%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.228ns Source Clock Delay (SCD): -2.007ns ======= Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.695ns (logic 0.478ns (28.202%) route 1.217ns (71.798%)) Logic Levels: 0 Clock Path Skew: 0.137ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.471ns Source Clock Delay (SCD): -0.608ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) <<<<<<< Updated upstream -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.821 -2.007 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) 1.084 -0.923 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 1.264 0.341 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D ======= -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.654 -0.608 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y95 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 1.217 1.087 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) <<<<<<< Updated upstream -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.114 -2.228 u_Axi_CDC/rFifo/cpu_clk SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C ======= -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.713ns (logic 0.386ns (22.535%) route 1.327ns (77.465%)) Logic Levels: 0 Clock Path Skew: 0.100ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.471ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.185 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 1.327 1.142 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C >>>>>>> Stashed changes Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) <<<<<<< Updated upstream Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.406ns (logic 1.084ns (45.052%) route 1.322ns (54.948%)) Logic Levels: 0 Clock Path Skew: -0.208ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.223ns Source Clock Delay (SCD): -2.014ns ======= Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.735ns (logic 0.394ns (22.711%) route 1.341ns (77.289%)) Logic Levels: 0 Clock Path Skew: 0.111ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.579ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) <<<<<<< Updated upstream -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.814 -2.014 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) 1.084 -0.930 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 1.322 0.392 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] SLICE_X17Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D ======= -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.185 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 1.341 1.155 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) <<<<<<< Updated upstream -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.119 -2.223 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C ======= -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.743ns (logic 0.394ns (22.610%) route 1.349ns (77.390%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.471ns Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.185 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 1.349 1.163 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.741ns (logic 0.390ns (22.398%) route 1.351ns (77.602%)) Logic Levels: 0 Clock Path Skew: 0.104ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.181 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 1.351 1.170 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.785ns (logic 0.492ns (27.569%) route 1.293ns (72.431%)) Logic Levels: 0 Clock Path Skew: 0.139ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.654 -0.608 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y95 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.116 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 1.293 1.176 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.793ns (logic 0.394ns (21.978%) route 1.399ns (78.022%)) Logic Levels: 0 Clock Path Skew: 0.137ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.471ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.654 -0.608 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y95 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.214 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 1.399 1.184 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_matmul_axi_slave/done_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.792ns (logic 0.141ns (7.867%) route 1.651ns (92.133%)) Logic Levels: 0 Clock Path Skew: 0.151ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.456ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.655 -0.607 u_matmul_axi_slave/sys_clk SLICE_X45Y98 FDRE r u_matmul_axi_slave/done_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.466 r u_matmul_axi_slave/done_reg/Q net (fo=10, routed) 1.651 1.185 u_cpu/u_csr/interrupt[2] SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.852 -0.456 u_cpu/u_csr/cpu_clk SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.798ns (logic 0.388ns (21.581%) route 1.410ns (78.419%)) Logic Levels: 0 Clock Path Skew: 0.112ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.191 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 1.410 1.218 u_Axi_CDC/rFifo/_zz_ram_port10__2[21] SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.801ns (logic 0.388ns (21.541%) route 1.413ns (78.459%)) Logic Levels: 0 Clock Path Skew: 0.112ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.191 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O net (fo=1, routed) 1.413 1.222 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.823ns (logic 0.390ns (21.395%) route 1.433ns (78.605%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.471ns Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.189 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 1.433 1.243 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.874ns (logic 0.394ns (21.025%) route 1.480ns (78.975%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.570ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.692 -0.570 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.176 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 1.480 1.304 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.931ns (logic 0.492ns (25.483%) route 1.439ns (74.517%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.471ns Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.087 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 1.439 1.351 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.927ns (logic 0.394ns (20.444%) route 1.533ns (79.556%)) Logic Levels: 0 Clock Path Skew: 0.102ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.177 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 1.533 1.356 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.930ns (logic 0.478ns (24.771%) route 1.452ns (75.229%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.570ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.692 -0.570 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.092 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 1.452 1.359 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.952ns (logic 0.478ns (24.493%) route 1.474ns (75.507%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.471ns Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.101 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 1.474 1.372 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C >>>>>>> Stashed changes Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D <<<<<<< Updated upstream (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.432ns (logic 1.056ns (43.427%) route 1.376ns (56.573%)) Logic Levels: 0 Clock Path Skew: -0.210ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.224ns Source Clock Delay (SCD): -2.013ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.962ns (logic 0.478ns (24.362%) route 1.484ns (75.638%)) Logic Levels: 0 Clock Path Skew: 0.110ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 <<<<<<< Updated upstream K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.815 -2.013 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.957 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 1.376 0.418 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D ======= K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.101 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 1.484 1.383 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 <<<<<<< Updated upstream K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.459ns (logic 1.056ns (42.943%) route 1.403ns (57.057%)) Logic Levels: 0 Clock Path Skew: -0.209ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.224ns Source Clock Delay (SCD): -2.014ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.964ns (logic 0.386ns (19.656%) route 1.578ns (80.344%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.471ns Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.193 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 1.578 1.384 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.955ns (logic 0.390ns (19.946%) route 1.565ns (80.054%)) Logic Levels: 0 Clock Path Skew: 0.099ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.471ns Source Clock Delay (SCD): -0.570ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.692 -0.570 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.180 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 1.565 1.385 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.992ns (logic 0.390ns (19.580%) route 1.602ns (80.420%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.471ns Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.189 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 1.602 1.412 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.992ns (logic 0.492ns (24.697%) route 1.500ns (75.303%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.471ns Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.087 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 1.500 1.413 u_Axi_CDC/rFifo/_zz_ram_port10__2[18] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.048ns (logic 0.388ns (18.950%) route 1.660ns (81.050%)) Logic Levels: 0 Clock Path Skew: 0.113ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 1.660 1.476 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] SLICE_X93Y111 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y111 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.130ns (logic 0.388ns (18.217%) route 1.742ns (81.783%)) Logic Levels: 0 Clock Path Skew: 0.102ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 1.742 1.559 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.166ns (logic 0.386ns (17.825%) route 1.780ns (82.175%)) Logic Levels: 0 Clock Path Skew: 0.102ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.570ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.692 -0.570 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.184 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 1.780 1.595 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.172ns (logic 0.388ns (17.864%) route 1.784ns (82.136%)) Logic Levels: 0 Clock Path Skew: 0.099ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.471ns Source Clock Delay (SCD): -0.570ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.692 -0.570 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.182 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 1.784 1.602 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.196ns (logic 0.386ns (17.576%) route 1.810ns (82.424%)) Logic Levels: 0 Clock Path Skew: 0.102ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.185 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O net (fo=1, routed) 1.810 1.625 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.201ns (logic 0.390ns (17.720%) route 1.811ns (82.280%)) Logic Levels: 0 Clock Path Skew: 0.103ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.181 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 1.811 1.629 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: mlkem_clk Max Delay 0 Endpoints Min Delay 112 Endpoints -------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.629ns (logic 0.367ns (58.312%) route 0.262ns (41.688%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.112ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.814 -2.014 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.958 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 1.403 0.445 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r ======= net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk SLICE_X54Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y91 FDCE (Prop_fdce_C_Q) 0.367 -1.745 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.262 -1.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[2] SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.660ns (logic 0.337ns (51.055%) route 0.323ns (48.945%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.504ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X51Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y83 FDCE (Prop_fdce_C_Q) 0.337 -1.780 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.323 -1.457 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C >>>>>>> Stashed changes Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) <<<<<<< Updated upstream Data Path Delay: 2.501ns (logic 1.059ns (42.335%) route 1.442ns (57.665%)) Logic Levels: 0 Clock Path Skew: -0.210ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.224ns Source Clock Delay (SCD): -2.013ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.815 -2.013 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) 1.059 -0.954 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 1.442 0.488 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.513ns (logic 1.059ns (42.141%) route 1.454ns (57.859%)) Logic Levels: 0 Clock Path Skew: -0.209ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.222ns Source Clock Delay (SCD): -2.012ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.816 -2.012 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) 1.059 -0.953 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 1.454 0.501 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.120 -2.222 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.094ns (logic 0.394ns (36.013%) route 0.700ns (63.987%)) Logic Levels: 0 Clock Path Skew: 0.299ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.272ns Source Clock Delay (SCD): -0.571ns ======= Data Path Delay: 0.672ns (logic 0.385ns (57.253%) route 0.287ns (42.747%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.511ns Source Clock Delay (SCD): -2.125ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) <<<<<<< Updated upstream -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.177 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 0.700 0.523 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D ======= -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.703 -2.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X74Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y96 FDCE (Prop_fdce_C_Q) 0.385 -1.740 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.287 -1.453 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 <<<<<<< Updated upstream K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.036 -0.272 u_Axi_CDC/rFifo/cpu_clk SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.095ns (logic 0.390ns (35.601%) route 0.705ns (64.399%)) Logic Levels: 0 Clock Path Skew: 0.293ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.278ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.181 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 0.705 0.524 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.030 -0.278 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.549ns (logic 1.083ns (42.493%) route 1.466ns (57.507%)) Logic Levels: 0 Clock Path Skew: -0.209ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.222ns Source Clock Delay (SCD): -2.012ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.816 -2.012 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) 1.083 -0.929 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 1.466 0.536 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.120 -2.222 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.116ns (logic 0.390ns (34.953%) route 0.726ns (65.047%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.275ns Source Clock Delay (SCD): -0.572ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.182 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 0.726 0.543 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.033 -0.275 u_Axi_CDC/rFifo/cpu_clk SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.116ns (logic 0.390ns (34.933%) route 0.726ns (65.067%)) Logic Levels: 0 Clock Path Skew: 0.295ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.276ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.181 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.726 0.545 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] SLICE_X14Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.032 -0.276 u_Axi_CDC/rFifo/cpu_clk SLICE_X14Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.565ns (logic 1.056ns (41.172%) route 1.509ns (58.828%)) Logic Levels: 0 Clock Path Skew: -0.210ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.225ns Source Clock Delay (SCD): -2.014ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.814 -2.014 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.958 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 1.509 0.551 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.567ns (logic 1.059ns (41.247%) route 1.508ns (58.753%)) Logic Levels: 0 Clock Path Skew: -0.209ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.224ns Source Clock Delay (SCD): -2.014ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.814 -2.014 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) 1.059 -0.955 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 1.508 0.553 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.129ns (logic 0.388ns (34.373%) route 0.741ns (65.627%)) Logic Levels: 0 Clock Path Skew: 0.300ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.272ns Source Clock Delay (SCD): -0.572ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.184 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 0.741 0.556 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.036 -0.272 u_Axi_CDC/rFifo/cpu_clk SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.135ns (logic 0.394ns (34.715%) route 0.741ns (65.285%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.274ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.177 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 0.741 0.564 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.034 -0.274 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.148ns (logic 0.386ns (33.633%) route 0.762ns (66.367%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.274ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.185 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 0.762 0.576 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.034 -0.274 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.151ns (logic 0.390ns (33.893%) route 0.761ns (66.107%)) Logic Levels: 0 Clock Path Skew: 0.299ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.273ns Source Clock Delay (SCD): -0.572ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.182 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.761 0.578 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.035 -0.273 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.151ns (logic 0.394ns (34.237%) route 0.757ns (65.763%)) Logic Levels: 0 Clock Path Skew: 0.295ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.277ns Source Clock Delay (SCD): -0.572ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.178 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 0.757 0.578 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.153ns (logic 0.388ns (33.638%) route 0.765ns (66.362%)) Logic Levels: 0 Clock Path Skew: 0.294ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.277ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O net (fo=1, routed) 0.765 0.582 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] SLICE_X15Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.182ns (logic 0.388ns (32.831%) route 0.794ns (67.169%)) Logic Levels: 0 Clock Path Skew: 0.294ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.277ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 0.794 0.610 u_Axi_CDC/rFifo/_zz_ram_port10__2[21] SLICE_X14Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk SLICE_X14Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.224ns (logic 0.390ns (31.861%) route 0.834ns (68.139%)) Logic Levels: 0 Clock Path Skew: 0.293ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.278ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.181 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 0.834 0.653 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.030 -0.278 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.266ns (logic 0.388ns (30.652%) route 0.878ns (69.348%)) Logic Levels: 0 Clock Path Skew: 0.293ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.278ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 0.878 0.694 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.030 -0.278 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.273ns (logic 0.492ns (38.660%) route 0.781ns (61.340%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.275ns Source Clock Delay (SCD): -0.572ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.080 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.781 0.700 u_Axi_CDC/rFifo/_zz_ram_port10__2[24] SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.033 -0.275 u_Axi_CDC/rFifo/cpu_clk SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.727ns (logic 1.056ns (38.721%) route 1.671ns (61.279%)) Logic Levels: 0 Clock Path Skew: -0.210ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.223ns Source Clock Delay (SCD): -2.012ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.816 -2.012 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.956 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 1.671 0.715 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] SLICE_X13Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.119 -2.223 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.291ns (logic 0.492ns (38.120%) route 0.799ns (61.880%)) Logic Levels: 0 Clock Path Skew: 0.294ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.277ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.079 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 0.799 0.719 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.292ns (logic 0.492ns (38.091%) route 0.800ns (61.909%)) Logic Levels: 0 Clock Path Skew: 0.298ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.273ns Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.079 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 0.800 0.720 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.035 -0.273 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C ======= K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.831 -2.511 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C >>>>>>> Stashed changes Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) <<<<<<< Updated upstream Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.331ns (logic 0.394ns (29.608%) route 0.937ns (70.392%)) Logic Levels: 0 Clock Path Skew: 0.294ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.278ns Source Clock Delay (SCD): -0.572ns ======= Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.673ns (logic 0.418ns (62.094%) route 0.255ns (37.906%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.506ns Source Clock Delay (SCD): -2.120ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) <<<<<<< Updated upstream -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.178 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 0.937 0.758 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] SLICE_X17Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D ======= -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X68Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X68Y92 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.255 -1.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[3] SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 <<<<<<< Updated upstream K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.030 -0.278 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C ======= K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.672ns (logic 0.367ns (54.616%) route 0.305ns (45.384%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.504ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X51Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y83 FDCE (Prop_fdce_C_Q) 0.367 -1.750 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.305 -1.445 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[1] SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.680ns (logic 0.385ns (56.580%) route 0.295ns (43.420%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.385 -1.735 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=4, routed) 0.295 -1.440 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[3] SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.722ns (logic 0.418ns (57.896%) route 0.304ns (42.104%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.304 -1.398 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[0] SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.760ns (logic 0.385ns (50.673%) route 0.375ns (49.327%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.506ns Source Clock Delay (SCD): -2.119ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y93 FDCE (Prop_fdce_C_Q) 0.385 -1.734 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.375 -1.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[2] SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.756ns (logic 0.367ns (48.571%) route 0.389ns (51.429%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.500ns Source Clock Delay (SCD): -2.112ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk SLICE_X54Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y91 FDCE (Prop_fdce_C_Q) 0.367 -1.745 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.389 -1.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[1] SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.842 -2.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.784ns (logic 0.418ns (53.295%) route 0.366ns (46.705%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.505ns Source Clock Delay (SCD): -2.119ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y93 FDCE (Prop_fdce_C_Q) 0.418 -1.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.366 -1.335 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[1] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.837 -2.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.788ns (logic 0.367ns (46.589%) route 0.421ns (53.411%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.504ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X51Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y83 FDCE (Prop_fdce_C_Q) 0.367 -1.750 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.421 -1.330 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[0] SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.801ns (logic 0.418ns (52.179%) route 0.383ns (47.821%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.511ns Source Clock Delay (SCD): -2.125ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.703 -2.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X74Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y96 FDCE (Prop_fdce_C_Q) 0.418 -1.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.383 -1.324 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[1] SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.831 -2.511 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.794ns (logic 0.367ns (46.198%) route 0.427ns (53.802%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.112ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk SLICE_X54Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y91 FDCE (Prop_fdce_C_Q) 0.367 -1.745 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.427 -1.318 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[0] SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.924ns (logic 0.418ns (45.244%) route 0.506ns (54.756%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=2, routed) 0.506 -1.196 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[2] SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.948ns (logic 0.418ns (44.102%) route 0.530ns (55.898%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.513ns Source Clock Delay (SCD): -2.125ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.703 -2.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X74Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y96 FDCE (Prop_fdce_C_Q) 0.418 -1.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.530 -1.177 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[0] SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.829 -2.513 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.961ns (logic 0.418ns (43.489%) route 0.543ns (56.511%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.543 -1.159 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[1] SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.504ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) 1.084 -1.033 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 0.162 -0.871 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[30] SLICE_X49Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.314ns (logic 1.062ns (80.806%) route 0.252ns (19.194%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.119ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.057 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 0.252 -0.805 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[21] SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.326ns (logic 0.418ns (31.525%) route 0.908ns (68.475%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.506ns Source Clock Delay (SCD): -2.119ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y93 FDCE (Prop_fdce_C_Q) 0.418 -1.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.908 -0.793 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[0] SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.332ns (logic 1.062ns (79.740%) route 0.270ns (20.260%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.059 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/O net (fo=1, routed) 0.270 -0.789 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[39] SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.335ns (logic 1.083ns (81.113%) route 0.252ns (18.887%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.038 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/O net (fo=1, routed) 0.252 -0.786 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[38] SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.338ns (logic 1.084ns (81.023%) route 0.254ns (18.977%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.119ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) 1.084 -1.035 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 0.254 -0.781 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[18] SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.336ns (logic 1.059ns (79.280%) route 0.277ns (20.720%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X64Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y97 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.056 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/O net (fo=1, routed) 0.277 -0.779 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[35] SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.338ns (logic 1.062ns (79.382%) route 0.276ns (20.618%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.116ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.712 -2.116 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X64Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.054 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/O net (fo=1, routed) 0.276 -0.778 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[9] SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.344ns (logic 1.056ns (78.582%) route 0.288ns (21.418%)) Logic Levels: 0 Clock Path Skew: -0.382ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.504ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X70Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y98 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.065 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/O net (fo=1, routed) 0.288 -0.777 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[43] SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.338ns (logic 1.078ns (80.540%) route 0.260ns (19.460%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.037 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/O net (fo=1, routed) 0.260 -0.777 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[4] SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.349ns (logic 1.062ns (78.741%) route 0.287ns (21.259%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.505ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.055 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/O net (fo=1, routed) 0.287 -0.769 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[33] SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.837 -2.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.358ns (logic 1.083ns (79.749%) route 0.275ns (20.251%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.506ns Source Clock Delay (SCD): -2.119ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.036 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 0.275 -0.761 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[20] SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.359ns (logic 1.078ns (79.297%) route 0.281ns (20.703%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X64Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y97 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.037 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/O net (fo=1, routed) 0.281 -0.756 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[34] SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.364ns (logic 1.083ns (79.398%) route 0.281ns (20.602%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.034 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/O net (fo=1, routed) 0.281 -0.753 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[8] SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.364ns (logic 1.083ns (79.398%) route 0.281ns (20.602%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X64Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y97 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.032 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/O net (fo=1, routed) 0.281 -0.751 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[32] SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.370ns (logic 1.084ns (79.141%) route 0.286ns (20.859%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.508ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X46Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y80 RAMD32 (Prop_ramd32_CLK_O) 1.084 -1.036 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.286 -0.751 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[12] SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.834 -2.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.365ns (logic 1.084ns (79.431%) route 0.281ns (20.569%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.499ns Source Clock Delay (SCD): -2.112ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK SLICE_X56Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y91 RAMD32 (Prop_ramd32_CLK_O) 1.084 -1.028 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/O net (fo=1, routed) 0.281 -0.748 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[48] SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.375ns (logic 1.083ns (78.791%) route 0.292ns (21.209%)) Logic Levels: 0 Clock Path Skew: -0.382ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.504ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X70Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y98 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.038 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/O net (fo=1, routed) 0.292 -0.747 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[44] SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.372ns (logic 1.084ns (78.983%) route 0.288ns (21.017%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.116ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.712 -2.116 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y84 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y84 RAMD32 (Prop_ramd32_CLK_O) 1.084 -1.032 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 0.288 -0.744 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[0] SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.425ns (logic 1.056ns (74.089%) route 0.369ns (25.911%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.059 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/O net (fo=1, routed) 0.369 -0.690 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[1] SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.427ns (logic 1.056ns (73.983%) route 0.371ns (26.017%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.505ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.061 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.371 -0.690 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[31] SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.837 -2.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.434ns (logic 1.059ns (73.825%) route 0.375ns (26.175%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.508ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X46Y79 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.061 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 0.375 -0.686 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[11] SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.834 -2.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.444ns (logic 1.062ns (73.543%) route 0.382ns (26.457%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.053 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/O net (fo=1, routed) 0.382 -0.671 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[3] SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.451ns (logic 1.056ns (72.768%) route 0.395ns (27.232%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.504ns Source Clock Delay (SCD): -2.118ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.710 -2.118 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y97 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/O net (fo=1, routed) 0.395 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[49] SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.458ns (logic 1.056ns (72.406%) route 0.402ns (27.594%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.506ns Source Clock Delay (SCD): -2.119ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.063 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.402 -0.661 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[19] SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.462ns (logic 1.059ns (72.423%) route 0.403ns (27.577%)) Logic Levels: 0 Clock Path Skew: -0.382ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.504ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/O net (fo=1, routed) 0.403 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[41] SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.461ns (logic 1.056ns (72.257%) route 0.405ns (27.743%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X46Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y80 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.064 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.405 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[13] SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.454ns (logic 1.078ns (74.152%) route 0.376ns (25.848%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.499ns Source Clock Delay (SCD): -2.112ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X56Y92 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y92 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.034 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O net (fo=1, routed) 0.376 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34] SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.457ns (logic 1.062ns (72.891%) route 0.395ns (27.109%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X64Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y97 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.053 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/O net (fo=1, routed) 0.395 -0.658 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[33] SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.463ns (logic 1.062ns (72.614%) route 0.401ns (27.386%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.508ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X46Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y80 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.058 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 0.401 -0.658 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[15] SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.834 -2.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.467ns (logic 1.062ns (72.395%) route 0.405ns (27.605%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.508ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X46Y79 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.058 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 0.405 -0.653 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[9] SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.834 -2.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.463ns (logic 1.059ns (72.373%) route 0.404ns (27.627%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.116ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.712 -2.116 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X64Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.057 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/O net (fo=1, routed) 0.404 -0.653 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[11] SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.470ns (logic 1.078ns (73.317%) route 0.392ns (26.683%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.043 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/O net (fo=1, routed) 0.392 -0.651 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[40] SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.471ns (logic 1.059ns (71.992%) route 0.412ns (28.008%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.505ns Source Clock Delay (SCD): -2.119ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.060 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 0.412 -0.648 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[23] SLICE_X50Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.837 -2.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X50Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/C >>>>>>> Stashed changes -------------------------------------------------------------------------------------- Path Group: (none) From Clock: cpu_clk To Clock: sys_clk Max Delay 0 Endpoints Min Delay 154 Endpoints -------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf <<<<<<< Updated upstream Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.503ns (logic 0.367ns (72.947%) route 0.136ns (27.053%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.209ns Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.514ns (logic 0.367ns (71.372%) route 0.147ns (28.628%)) Logic Levels: 0 Clock Path Skew: -0.396ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.688ns Source Clock Delay (SCD): -2.292ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y43 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.136 -1.328 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[3] SLICE_X12Y43 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/bFifo/cpu_clk SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y122 FDCE (Prop_fdce_C_Q) 0.367 -1.925 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.147 -1.778 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[1] SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 2.133 -2.209 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X12Y43 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.609ns (logic 0.337ns (55.331%) route 0.272ns (44.669%)) Logic Levels: 0 Clock Path Skew: -0.380ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.213ns Source Clock Delay (SCD): -1.833ns ======= net (fo=9971, routed) 1.654 -2.688 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.611ns (logic 0.337ns (55.112%) route 0.274ns (44.888%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.697ns Source Clock Delay (SCD): -2.302ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.996 -1.833 u_Axi_CDC/bFifo/cpu_clk SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X11Y40 FDCE (Prop_fdce_C_Q) 0.337 -1.496 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.272 -1.224 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[2] SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y125 FDCE (Prop_fdce_C_Q) 0.337 -1.965 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=5, routed) 0.274 -1.690 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[3] SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 2.129 -2.213 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C ======= net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.665ns (logic 0.385ns (57.882%) route 0.280ns (42.118%)) Logic Levels: 0 Clock Path Skew: -0.400ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.688ns Source Clock Delay (SCD): -2.288ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.540 -2.288 u_Axi_CDC/bFifo/cpu_clk SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y122 FDCE (Prop_fdce_C_Q) 0.385 -1.903 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.280 -1.623 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[2] SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.654 -2.688 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C >>>>>>> Stashed changes Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) <<<<<<< Updated upstream Data Path Delay: 0.622ns (logic 0.367ns (58.987%) route 0.255ns (41.013%)) Logic Levels: 0 Clock Path Skew: -0.379ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.210ns Source Clock Delay (SCD): -1.831ns ======= Data Path Delay: 0.672ns (logic 0.418ns (62.186%) route 0.254ns (37.814%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.675ns Source Clock Delay (SCD): -2.281ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y43 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.255 -1.209 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[1] SLICE_X12Y42 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.418 -1.863 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.254 -1.609 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[3] SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X12Y42 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.642ns (logic 0.337ns (52.522%) route 0.305ns (47.478%)) Logic Levels: 0 Clock Path Skew: -0.380ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.211ns Source Clock Delay (SCD): -1.831ns ======= net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.738ns (logic 0.337ns (45.657%) route 0.401ns (54.343%)) Logic Levels: 0 Clock Path Skew: -0.402ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.700ns Source Clock Delay (SCD): -2.298ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 -2.298 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y105 FDCE (Prop_fdce_C_Q) 0.337 -1.961 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.401 -1.560 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.642 -2.700 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.779ns (logic 0.367ns (47.087%) route 0.412ns (52.913%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.697ns Source Clock Delay (SCD): -2.302ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/arFifo/cpu_clk SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y47 FDCE (Prop_fdce_C_Q) 0.337 -1.494 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.305 -1.189 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y125 FDCE (Prop_fdce_C_Q) 0.367 -1.935 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=3, routed) 0.412 -1.522 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[2] SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 2.131 -2.211 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.684ns (logic 0.418ns (61.129%) route 0.266ns (38.871%)) Logic Levels: 0 Clock Path Skew: -0.380ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.213ns Source Clock Delay (SCD): -1.833ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.996 -1.833 u_Axi_CDC/bFifo/cpu_clk SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y40 FDCE (Prop_fdce_C_Q) 0.418 -1.415 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.266 -1.149 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[1] SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.129 -2.213 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.754ns (logic 0.367ns (48.681%) route 0.387ns (51.319%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.210ns Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 -1.832 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y42 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.387 -1.078 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[1] SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.782ns (logic 0.385ns (49.223%) route 0.397ns (50.777%)) Logic Levels: 0 Clock Path Skew: -0.380ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.211ns Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/awFifo/cpu_clk SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y44 FDCE (Prop_fdce_C_Q) 0.385 -1.446 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.397 -1.049 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.131 -2.211 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.811ns (logic 0.418ns (51.570%) route 0.393ns (48.430%)) Logic Levels: 0 Clock Path Skew: -0.380ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.211ns Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/awFifo/cpu_clk SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.393 -1.020 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[0] SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.131 -2.211 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.845ns (logic 0.418ns (49.462%) route 0.427ns (50.538%)) Logic Levels: 0 Clock Path Skew: -0.380ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.213ns Source Clock Delay (SCD): -1.833ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.996 -1.833 u_Axi_CDC/bFifo/cpu_clk SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y40 FDCE (Prop_fdce_C_Q) 0.418 -1.415 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.427 -0.988 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[0] SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.129 -2.213 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.844ns (logic 0.418ns (49.514%) route 0.426ns (50.486%)) Logic Levels: 0 Clock Path Skew: -0.380ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.211ns Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/awFifo/cpu_clk SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.426 -0.986 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[1] SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.131 -2.211 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.868ns (logic 0.337ns (38.842%) route 0.531ns (61.158%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.209ns Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y43 FDCE (Prop_fdce_C_Q) 0.337 -1.494 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.531 -0.963 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[2] SLICE_X12Y43 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.133 -2.209 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X12Y43 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.899ns (logic 0.367ns (40.831%) route 0.532ns (59.169%)) Logic Levels: 0 Clock Path Skew: -0.379ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.210ns Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y43 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.532 -0.932 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[0] SLICE_X12Y42 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X12Y42 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.899ns (logic 0.367ns (40.814%) route 0.532ns (59.186%)) Logic Levels: 0 Clock Path Skew: -0.379ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.210ns Source Clock Delay (SCD): -1.831ns ======= net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.781ns (logic 0.367ns (46.998%) route 0.414ns (53.002%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.697ns Source Clock Delay (SCD): -2.302ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/arFifo/cpu_clk SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y47 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.532 -0.931 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[1] SLICE_X16Y47 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y125 FDCE (Prop_fdce_C_Q) 0.367 -1.935 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.414 -1.521 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[0] SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk SLICE_X16Y47 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.019ns (logic 0.367ns (36.005%) route 0.652ns (63.995%)) Logic Levels: 0 Clock Path Skew: -0.380ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.212ns Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.792ns (logic 0.367ns (46.340%) route 0.425ns (53.660%)) Logic Levels: 0 Clock Path Skew: -0.396ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.688ns Source Clock Delay (SCD): -2.292ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 -1.832 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y42 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=3, routed) 0.652 -0.812 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[2] SLICE_X9Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/bFifo/cpu_clk SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y122 FDCE (Prop_fdce_C_Q) 0.367 -1.925 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.425 -1.500 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[0] SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 2.130 -2.212 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X9Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.035ns (logic 0.337ns (32.545%) route 0.698ns (67.455%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.210ns Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= net (fo=9971, routed) 1.654 -2.688 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.791ns (logic 0.367ns (46.425%) route 0.424ns (53.575%)) Logic Levels: 0 Clock Path Skew: -0.393ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.676ns Source Clock Delay (SCD): -2.283ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 -1.832 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y42 FDCE (Prop_fdce_C_Q) 0.337 -1.495 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=5, routed) 0.698 -0.796 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[3] SLICE_X12Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.545 -2.283 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y113 FDCE (Prop_fdce_C_Q) 0.367 -1.916 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.424 -1.492 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[1] SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[34]/D ======= net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.790ns (logic 0.418ns (52.908%) route 0.372ns (47.092%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.676ns Source Clock Delay (SCD): -2.281ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.418 -1.863 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.372 -1.491 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[1] SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.793ns (logic 0.367ns (46.304%) route 0.426ns (53.696%)) Logic Levels: 0 Clock Path Skew: -0.392ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.675ns Source Clock Delay (SCD): -2.283ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.545 -2.283 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y113 FDCE (Prop_fdce_C_Q) 0.367 -1.916 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.426 -1.490 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[0] SLICE_X92Y112 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y112 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.829ns (logic 0.418ns (50.441%) route 0.411ns (49.559%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.676ns Source Clock Delay (SCD): -2.281ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.418 -1.863 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.411 -1.452 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[0] SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.847ns (logic 0.367ns (43.340%) route 0.480ns (56.660%)) Logic Levels: 0 Clock Path Skew: -0.398ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.697ns Source Clock Delay (SCD): -2.299ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.529 -2.299 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y127 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y127 FDCE (Prop_fdce_C_Q) 0.367 -1.932 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.480 -1.452 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[1] SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.870ns (logic 0.367ns (42.168%) route 0.503ns (57.832%)) Logic Levels: 0 Clock Path Skew: -0.402ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.700ns Source Clock Delay (SCD): -2.298ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 -2.298 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y105 FDCE (Prop_fdce_C_Q) 0.367 -1.931 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.503 -1.428 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[1] SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.642 -2.700 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.892ns (logic 0.367ns (41.125%) route 0.525ns (58.875%)) Logic Levels: 0 Clock Path Skew: -0.402ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.700ns Source Clock Delay (SCD): -2.298ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 -2.298 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y105 FDCE (Prop_fdce_C_Q) 0.367 -1.931 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.525 -1.405 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[0] SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.642 -2.700 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.974ns (logic 0.337ns (34.595%) route 0.637ns (65.405%)) Logic Levels: 0 Clock Path Skew: -0.393ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.676ns Source Clock Delay (SCD): -2.283ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.545 -2.283 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y113 FDCE (Prop_fdce_C_Q) 0.337 -1.946 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.637 -1.309 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.171ns (logic 0.385ns (32.864%) route 0.786ns (67.136%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.675ns Source Clock Delay (SCD): -2.281ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.385 -1.896 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.786 -1.109 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[2] SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D >>>>>>> Stashed changes (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.240ns (logic 1.078ns (86.936%) route 0.162ns (13.064%)) Logic Levels: 0 <<<<<<< Updated upstream Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.395ns Source Clock Delay (SCD): -2.007ns ======= Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.684ns Source Clock Delay (SCD): -2.290ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X18Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y56 RAMD32 (Prop_ramd32_CLK_O) 1.078 -0.929 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC/O net (fo=1, routed) 0.162 -0.767 u_Axi_CDC/awFifo/_zz_ram_port10[34] SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[34]/D ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.234 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 0.159 -1.075 u_Axi_CDC/awFifo/_zz_ram_port10[7] SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/awFifo/sys_clk SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[34]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.359ns (logic 1.078ns (79.297%) route 0.281ns (20.703%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.495ns Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.030 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/O net (fo=1, routed) 0.281 -0.749 u_Axi_CDC/arFifo/_zz_ram_port10__1[10] SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.363ns (logic 1.084ns (79.504%) route 0.279ns (20.496%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.495ns Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) 1.084 -1.024 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/O net (fo=1, routed) 0.279 -0.745 u_Axi_CDC/arFifo/_zz_ram_port10__1[6] SLICE_X44Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk SLICE_X44Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.106ns (logic 0.367ns (33.193%) route 0.739ns (66.807%)) Logic Levels: 0 Clock Path Skew: -0.379ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.210ns Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/arFifo/cpu_clk SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y47 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.739 -0.725 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[0] SLICE_X16Y47 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk SLICE_X16Y47 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.301ns (logic 1.056ns (81.139%) route 0.245ns (18.861%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.396ns Source Clock Delay (SCD): -2.008ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X20Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y54 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.952 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/O net (fo=1, routed) 0.245 -0.707 u_Axi_CDC/arFifo/_zz_ram_port10__1[37] SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/arFifo/sys_clk SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.301ns (logic 1.056ns (81.139%) route 0.245ns (18.861%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.395ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X18Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y56 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.951 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/O net (fo=1, routed) 0.245 -0.706 u_Axi_CDC/awFifo/_zz_ram_port10[31] SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/awFifo/sys_clk SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.328ns (logic 1.056ns (79.500%) route 0.272ns (20.500%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.412ns Source Clock Delay (SCD): -2.025ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.803 -2.025 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X40Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y57 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.969 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/O net (fo=1, routed) 0.272 -0.697 u_Axi_CDC/awFifo/_zz_ram_port10[13] SLICE_X38Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.930 -2.412 u_Axi_CDC/awFifo/sys_clk SLICE_X38Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.331ns (logic 1.083ns (81.357%) route 0.248ns (18.643%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.395ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X18Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y56 RAMD32 (Prop_ramd32_CLK_O) 1.083 -0.924 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/O net (fo=1, routed) 0.248 -0.676 u_Axi_CDC/awFifo/_zz_ram_port10[32] SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/awFifo/sys_clk SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.157ns (logic 0.367ns (31.718%) route 0.790ns (68.282%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.210ns Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 -1.832 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y42 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.790 -0.675 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[0] SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.333ns (logic 1.062ns (79.680%) route 0.271ns (20.320%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.395ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) 1.062 -0.945 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/O net (fo=1, routed) 0.271 -0.674 u_Axi_CDC/arFifo/_zz_ram_port10__1[33] SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.338ns (logic 1.062ns (79.382%) route 0.276ns (20.618%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.396ns Source Clock Delay (SCD): -2.008ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X20Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y54 RAMD32 (Prop_ramd32_CLK_O) 1.062 -0.946 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/O net (fo=1, routed) 0.276 -0.670 u_Axi_CDC/arFifo/_zz_ram_port10__1[39] SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/arFifo/sys_clk SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.344ns (logic 1.056ns (78.598%) route 0.288ns (21.402%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.395ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.951 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/O net (fo=1, routed) 0.288 -0.664 u_Axi_CDC/arFifo/_zz_ram_port10__1[31] SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.348ns (logic 1.062ns (78.762%) route 0.286ns (21.238%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.394ns Source Clock Delay (SCD): -2.006ns ======= net (fo=9971, routed) 1.658 -2.684 u_Axi_CDC/awFifo/sys_clk SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.221ns (logic 1.062ns (86.996%) route 0.159ns (13.004%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.669ns Source Clock Delay (SCD): -2.275ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.822 -2.006 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X16Y50 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y50 RAMD32 (Prop_ramd32_CLK_O) 1.062 -0.944 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/O net (fo=1, routed) 0.286 -0.658 u_Axi_CDC/arFifo/_zz_ram_port10__1[45] SLICE_X15Y50 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/D ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.553 -2.275 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X60Y100 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y100 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.213 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/O net (fo=1, routed) 0.159 -1.054 u_Axi_CDC/awFifo/_zz_ram_port10[33] SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.948 -2.394 u_Axi_CDC/arFifo/sys_clk SLICE_X15Y50 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.451ns (logic 1.056ns (72.768%) route 0.395ns (27.232%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.495ns Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= net (fo=9971, routed) 1.673 -2.669 u_Axi_CDC/awFifo/sys_clk SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.312ns (logic 1.062ns (80.930%) route 0.250ns (19.070%)) Logic Levels: 0 Clock Path Skew: -0.393ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.699ns Source Clock Delay (SCD): -2.306ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll <<<<<<< Updated upstream BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.052 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 0.395 -0.657 u_Axi_CDC/arFifo/_zz_ram_port10__1[7] SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D ======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.522 -2.306 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X84Y117 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y117 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.244 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/O net (fo=1, routed) 0.250 -0.994 u_Axi_CDC/arFifo/_zz_ram_port10__1[15] SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) ======= net (fo=9971, routed) 1.643 -2.699 u_Axi_CDC/arFifo/sys_clk SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.335ns (logic 1.084ns (81.206%) route 0.251ns (18.794%)) Logic Levels: 0 Clock Path Skew: -0.393ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.699ns Source Clock Delay (SCD): -2.306ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.522 -2.306 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X84Y117 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y117 RAMD32 (Prop_ramd32_CLK_O) 1.084 -1.222 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/O net (fo=1, routed) 0.251 -0.971 u_Axi_CDC/arFifo/_zz_ram_port10__1[12] SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.643 -2.699 u_Axi_CDC/arFifo/sys_clk SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[47]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.335ns (logic 1.059ns (79.339%) route 0.276ns (20.661%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.681ns Source Clock Delay (SCD): -2.287ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X72Y104 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X72Y104 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.228 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/O net (fo=1, routed) 0.276 -0.952 u_Axi_CDC/arFifo/_zz_ram_port10__1[47] SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[47]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.661 -2.681 u_Axi_CDC/arFifo/sys_clk SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[47]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.345ns (logic 1.059ns (78.719%) route 0.286ns (21.281%)) Logic Levels: 0 Clock Path Skew: -0.391ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.678ns Source Clock Delay (SCD): -2.287ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X70Y103 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y103 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.228 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/O net (fo=1, routed) 0.286 -0.942 u_Axi_CDC/arFifo/_zz_ram_port10__1[35] SLICE_X68Y103 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.664 -2.678 u_Axi_CDC/arFifo/sys_clk SLICE_X68Y103 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.354ns (logic 1.056ns (77.964%) route 0.298ns (22.036%)) Logic Levels: 0 Clock Path Skew: -0.400ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.692ns Source Clock Delay (SCD): -2.292ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X90Y130 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y130 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.236 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.298 -0.937 u_Axi_CDC/wFifo/_zz_ram_port10__0[25] SLICE_X88Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.650 -2.692 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.345ns (logic 1.059ns (78.719%) route 0.286ns (21.281%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.675ns Source Clock Delay (SCD): -2.281ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK SLICE_X64Y106 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y106 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.222 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/O net (fo=1, routed) 0.286 -0.936 u_Axi_CDC/awFifo/_zz_ram_port10[47] SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/awFifo/sys_clk SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.375ns (logic 1.083ns (78.791%) route 0.292ns (21.209%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.675ns Source Clock Delay (SCD): -2.281ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK SLICE_X64Y106 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y106 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.198 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/O net (fo=1, routed) 0.292 -0.906 u_Axi_CDC/awFifo/_zz_ram_port10[44] SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/awFifo/sys_clk SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.428ns (logic 1.056ns (73.931%) route 0.372ns (26.069%)) Logic Levels: 0 Clock Path Skew: -0.393ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.699ns Source Clock Delay (SCD): -2.306ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.522 -2.306 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X84Y117 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y117 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.250 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/O net (fo=1, routed) 0.372 -0.878 u_Axi_CDC/arFifo/_zz_ram_port10__1[13] SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.643 -2.699 u_Axi_CDC/arFifo/sys_clk SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.462ns (logic 1.059ns (72.441%) route 0.403ns (27.559%)) Logic Levels: 0 Clock Path Skew: -0.391ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.699ns Source Clock Delay (SCD): -2.308ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.520 -2.308 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X84Y118 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y118 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.249 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/O net (fo=1, routed) 0.403 -0.846 u_Axi_CDC/arFifo/_zz_ram_port10__1[5] SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.643 -2.699 u_Axi_CDC/arFifo/sys_clk SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.457ns (logic 1.078ns (73.968%) route 0.379ns (26.032%)) Logic Levels: 0 Clock Path Skew: -0.410ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.712ns Source Clock Delay (SCD): -2.302ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X88Y125 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y125 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.224 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/O net (fo=1, routed) 0.379 -0.844 u_Axi_CDC/wFifo/_zz_ram_port10__0[34] SLICE_X86Y125 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.630 -2.712 u_Axi_CDC/wFifo/sys_clk SLICE_X86Y125 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.457ns (logic 1.083ns (74.327%) route 0.374ns (25.673%)) Logic Levels: 0 Clock Path Skew: -0.408ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.703ns Source Clock Delay (SCD): -2.295ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.533 -2.295 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X88Y131 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y131 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.212 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 0.374 -0.838 u_Axi_CDC/wFifo/_zz_ram_port10__0[8] SLICE_X87Y131 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.639 -2.703 u_Axi_CDC/wFifo/sys_clk SLICE_X87Y131 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.454ns (logic 1.056ns (72.605%) route 0.398ns (27.395%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.681ns Source Clock Delay (SCD): -2.287ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X70Y105 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y105 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.231 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/O net (fo=1, routed) 0.398 -0.832 u_Axi_CDC/arFifo/_zz_ram_port10__1[19] SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.661 -2.681 u_Axi_CDC/arFifo/sys_clk SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.456ns (logic 1.062ns (72.954%) route 0.394ns (27.046%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.681ns Source Clock Delay (SCD): -2.287ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X72Y104 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X72Y104 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.225 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/O net (fo=1, routed) 0.394 -0.831 u_Axi_CDC/arFifo/_zz_ram_port10__1[45] SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.661 -2.681 u_Axi_CDC/arFifo/sys_clk SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.481ns (logic 1.078ns (72.808%) route 0.403ns (27.192%)) Logic Levels: 0 Clock Path Skew: -0.391ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.699ns Source Clock Delay (SCD): -2.308ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.520 -2.308 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X84Y118 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y118 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.230 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/O net (fo=1, routed) 0.403 -0.827 u_Axi_CDC/arFifo/_zz_ram_port10__1[4] SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.643 -2.699 u_Axi_CDC/arFifo/sys_clk SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.465ns (logic 1.062ns (72.476%) route 0.403ns (27.524%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.675ns Source Clock Delay (SCD): -2.281ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK SLICE_X64Y106 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y106 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.219 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/O net (fo=1, routed) 0.403 -0.816 u_Axi_CDC/awFifo/_zz_ram_port10[45] SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/awFifo/sys_clk SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.476ns (logic 1.078ns (73.019%) route 0.398ns (26.981%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.681ns Source Clock Delay (SCD): -2.287ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X72Y104 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X72Y104 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.209 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/O net (fo=1, routed) 0.398 -0.811 u_Axi_CDC/arFifo/_zz_ram_port10__1[46] SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.661 -2.681 u_Axi_CDC/arFifo/sys_clk SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.483ns (logic 1.059ns (71.419%) route 0.424ns (28.581%)) Logic Levels: 0 Clock Path Skew: -0.397ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.684ns Source Clock Delay (SCD): -2.287ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X90Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y115 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.228 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/O net (fo=1, routed) 0.424 -0.804 u_Axi_CDC/awFifo/_zz_ram_port10[5] SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.658 -2.684 u_Axi_CDC/awFifo/sys_clk SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.490ns (logic 1.059ns (71.080%) route 0.431ns (28.920%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.676ns Source Clock Delay (SCD): -2.287ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X70Y105 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y105 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.228 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/O net (fo=1, routed) 0.431 -0.797 u_Axi_CDC/arFifo/_zz_ram_port10__1[23] SLICE_X64Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/arFifo/sys_clk SLICE_X64Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.511ns (logic 1.056ns (69.870%) route 0.455ns (30.130%)) Logic Levels: 0 Clock Path Skew: -0.410ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.712ns Source Clock Delay (SCD): -2.302ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X88Y125 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y125 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.246 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.455 -0.791 u_Axi_CDC/wFifo/_zz_ram_port10__0[31] SLICE_X86Y125 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.630 -2.712 u_Axi_CDC/wFifo/sys_clk SLICE_X86Y125 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.486ns (logic 1.083ns (72.891%) route 0.403ns (27.109%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.669ns Source Clock Delay (SCD): -2.275ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.553 -2.275 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X60Y100 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y100 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.192 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/O net (fo=1, routed) 0.403 -0.789 u_Axi_CDC/awFifo/_zz_ram_port10[32] SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.673 -2.669 u_Axi_CDC/awFifo/sys_clk SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.498ns (logic 1.083ns (72.295%) route 0.415ns (27.705%)) Logic Levels: 0 Clock Path Skew: -0.391ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.678ns Source Clock Delay (SCD): -2.287ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X72Y104 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X72Y104 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.204 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/O net (fo=1, routed) 0.415 -0.789 u_Axi_CDC/arFifo/_zz_ram_port10__1[44] SLICE_X68Y103 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.664 -2.678 u_Axi_CDC/arFifo/sys_clk SLICE_X68Y103 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.492ns (logic 1.056ns (70.798%) route 0.436ns (29.202%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.675ns Source Clock Delay (SCD): -2.280ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.548 -2.280 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK SLICE_X62Y103 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y103 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.224 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/O net (fo=1, routed) 0.436 -0.788 u_Axi_CDC/awFifo/_zz_ram_port10[37] SLICE_X63Y103 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/awFifo/sys_clk SLICE_X63Y103 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.499ns (logic 1.078ns (71.932%) route 0.421ns (28.068%)) Logic Levels: 0 Clock Path Skew: -0.397ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.684ns Source Clock Delay (SCD): -2.287ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X90Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y115 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.209 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC/O net (fo=1, routed) 0.421 -0.788 u_Axi_CDC/awFifo/_zz_ram_port10[4] SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.658 -2.684 u_Axi_CDC/awFifo/sys_clk SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) >>>>>>> Stashed changes Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) <<<<<<< Updated upstream Data Path Delay: 1.359ns (logic 1.078ns (79.297%) route 0.281ns (20.703%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.396ns Source Clock Delay (SCD): -2.008ns ======= Data Path Delay: 1.497ns (logic 1.078ns (72.028%) route 0.419ns (27.972%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.675ns Source Clock Delay (SCD): -2.281ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK SLICE_X64Y106 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y106 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.203 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/O net (fo=1, routed) 0.419 -0.784 u_Axi_CDC/awFifo/_zz_ram_port10[46] SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/awFifo/sys_clk SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.503ns (logic 1.056ns (70.245%) route 0.447ns (29.755%)) Logic Levels: 0 Clock Path Skew: -0.391ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.677ns Source Clock Delay (SCD): -2.286ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.542 -2.286 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y100 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y100 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.230 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/O net (fo=1, routed) 0.447 -0.783 u_Axi_CDC/arFifo/_zz_ram_port10__1[37] SLICE_X67Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.665 -2.677 u_Axi_CDC/arFifo/sys_clk SLICE_X67Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.504ns (logic 1.059ns (70.399%) route 0.445ns (29.601%)) Logic Levels: 0 Clock Path Skew: -0.391ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.677ns Source Clock Delay (SCD): -2.286ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.542 -2.286 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y100 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y100 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.227 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/O net (fo=1, routed) 0.445 -0.782 u_Axi_CDC/arFifo/_zz_ram_port10__1[41] SLICE_X67Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.665 -2.677 u_Axi_CDC/arFifo/sys_clk SLICE_X67Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.516ns (logic 1.056ns (69.676%) route 0.460ns (30.324%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.679ns Source Clock Delay (SCD): -2.285ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.543 -2.285 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK SLICE_X90Y112 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y112 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.229 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/O net (fo=1, routed) 0.460 -0.769 u_Axi_CDC/awFifo/_zz_ram_port10[25] SLICE_X89Y105 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.663 -2.679 u_Axi_CDC/awFifo/sys_clk SLICE_X89Y105 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.534ns (logic 1.056ns (68.850%) route 0.478ns (31.150%)) Logic Levels: 0 Clock Path Skew: -0.397ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.697ns Source Clock Delay (SCD): -2.300ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.528 -2.300 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X84Y109 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y109 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.244 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/O net (fo=1, routed) 0.478 -0.766 u_Axi_CDC/arFifo/_zz_ram_port10__1[25] SLICE_X81Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/arFifo/sys_clk SLICE_X81Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.531ns (logic 1.078ns (70.406%) route 0.453ns (29.594%)) Logic Levels: 0 Clock Path Skew: -0.408ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.703ns Source Clock Delay (SCD): -2.295ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.533 -2.295 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X88Y131 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y131 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.217 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 0.453 -0.764 u_Axi_CDC/wFifo/_zz_ram_port10__0[10] SLICE_X87Y131 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.639 -2.703 u_Axi_CDC/wFifo/sys_clk SLICE_X87Y131 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.542ns (logic 1.056ns (68.461%) route 0.486ns (31.539%)) Logic Levels: 0 Clock Path Skew: -0.393ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.697ns Source Clock Delay (SCD): -2.304ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.524 -2.304 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X84Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y115 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.248 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/O net (fo=1, routed) 0.486 -0.761 u_Axi_CDC/awFifo/_zz_ram_port10[13] SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/awFifo/sys_clk SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.544ns (logic 1.059ns (68.591%) route 0.485ns (31.409%)) Logic Levels: 0 Clock Path Skew: -0.393ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.697ns Source Clock Delay (SCD): -2.304ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.524 -2.304 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X84Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y115 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.245 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/O net (fo=1, routed) 0.485 -0.760 u_Axi_CDC/awFifo/_zz_ram_port10[17] SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/awFifo/sys_clk SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: mlkem_clk To Clock: sys_clk Max Delay 0 Endpoints Min Delay 61 Endpoints -------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.636ns (logic 0.367ns (57.746%) route 0.269ns (42.254%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.367 -1.755 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.269 -1.487 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[0] SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.633ns (logic 0.367ns (57.963%) route 0.266ns (42.037%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.499ns Source Clock Delay (SCD): -2.113ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.715 -2.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X54Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.266 -1.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[1] SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.637ns (logic 0.367ns (57.593%) route 0.270ns (42.407%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.115ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK SLICE_X20Y55 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y55 RAMD32 (Prop_ramd32_CLK_O) 1.078 -0.930 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/O net (fo=1, routed) 0.281 -0.649 u_Axi_CDC/awFifo/_zz_ram_port10[46] SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/D ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X50Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y85 FDCE (Prop_fdce_C_Q) 0.367 -1.748 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.270 -1.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[0] SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.359ns (logic 1.083ns (79.691%) route 0.276ns (20.309%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.395ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) 1.083 -0.924 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/O net (fo=1, routed) 0.276 -0.648 u_Axi_CDC/arFifo/_zz_ram_port10__1[32] SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.364ns (logic 1.083ns (79.398%) route 0.281ns (20.602%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.396ns Source Clock Delay (SCD): -2.008ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK SLICE_X20Y55 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y55 RAMD32 (Prop_ramd32_CLK_O) 1.083 -0.925 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/O net (fo=1, routed) 0.281 -0.644 u_Axi_CDC/awFifo/_zz_ram_port10[44] SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.364ns (logic 1.084ns (79.446%) route 0.280ns (20.554%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.395ns Source Clock Delay (SCD): -2.008ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK SLICE_X18Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y57 RAMD32 (Prop_ramd32_CLK_O) 1.084 -0.924 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/O net (fo=1, routed) 0.280 -0.644 u_Axi_CDC/awFifo/_zz_ram_port10[48] SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/awFifo/sys_clk SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.475ns (logic 1.059ns (71.806%) route 0.416ns (28.194%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.495ns Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.049 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/O net (fo=1, routed) 0.416 -0.633 u_Axi_CDC/arFifo/_zz_ram_port10__1[11] SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.375ns (logic 1.084ns (78.853%) route 0.291ns (21.147%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.395ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) 1.084 -0.923 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/O net (fo=1, routed) 0.291 -0.633 u_Axi_CDC/arFifo/_zz_ram_port10__1[30] SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/C ======= net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C >>>>>>> Stashed changes Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) <<<<<<< Updated upstream Data Path Delay: 1.484ns (logic 1.083ns (72.970%) route 0.401ns (27.030%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.495ns Source Clock Delay (SCD): -2.108ns ======= Data Path Delay: 0.682ns (logic 0.418ns (61.266%) route 0.264ns (38.734%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.514ns Source Clock Delay (SCD): -2.127ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y51 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.025 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/O net (fo=1, routed) 0.401 -0.624 u_Axi_CDC/arFifo/_zz_ram_port10__1[2] SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/D ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.701 -2.127 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y97 FDCE (Prop_fdce_C_Q) 0.418 -1.709 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.264 -1.445 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[2] SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.484ns (logic 1.083ns (72.970%) route 0.401ns (27.030%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.495ns Source Clock Delay (SCD): -2.108ns ======= net (fo=9971, routed) 1.828 -2.514 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.684ns (logic 0.418ns (61.086%) route 0.266ns (38.914%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.514ns Source Clock Delay (SCD): -2.127ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.701 -2.127 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y97 FDCE (Prop_fdce_C_Q) 0.418 -1.709 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.266 -1.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[1] SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.828 -2.514 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.730ns (logic 0.337ns (46.159%) route 0.393ns (53.841%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.499ns Source Clock Delay (SCD): -2.113ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.715 -2.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X54Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y90 FDCE (Prop_fdce_C_Q) 0.337 -1.776 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.393 -1.383 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.750ns (logic 0.367ns (48.935%) route 0.383ns (51.065%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.367 -1.755 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=3, routed) 0.383 -1.372 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[2] SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.770ns (logic 0.367ns (47.632%) route 0.403ns (52.368%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns >>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.025 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/O net (fo=1, routed) 0.401 -0.624 u_Axi_CDC/arFifo/_zz_ram_port10__1[8] SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.367 -1.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.403 -1.350 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[1] SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.389ns (logic 1.084ns (78.063%) route 0.305ns (21.937%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.394ns Source Clock Delay (SCD): -2.006ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.776ns (logic 0.337ns (43.419%) route 0.439ns (56.581%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.337 -1.785 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=5, routed) 0.439 -1.346 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[3] SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.792ns (logic 0.367ns (46.358%) route 0.425ns (53.642%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream (clock cpu_clk rise edge) 0.000 0.000 r ======= (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.822 -2.006 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X16Y50 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y50 RAMD32 (Prop_ramd32_CLK_O) 1.084 -0.922 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/O net (fo=1, routed) 0.305 -0.618 u_Axi_CDC/arFifo/_zz_ram_port10__1[42] SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X50Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y85 FDCE (Prop_fdce_C_Q) 0.367 -1.748 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.425 -1.324 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[2] SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.948 -2.394 u_Axi_CDC/arFifo/sys_clk SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.463ns (logic 1.084ns (74.106%) route 0.379ns (25.894%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.396ns Source Clock Delay (SCD): -2.008ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.837ns (logic 0.418ns (49.937%) route 0.419ns (50.063%)) Logic Levels: 0 Clock Path Skew: -0.391ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.514ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y96 FDCE (Prop_fdce_C_Q) 0.418 -1.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.419 -1.285 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.828 -2.514 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.844ns (logic 0.367ns (43.474%) route 0.477ns (56.526%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.367 -1.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.477 -1.276 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[0] SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.848ns (logic 0.337ns (39.750%) route 0.511ns (60.250%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.337 -1.783 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.511 -1.272 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.044ns (logic 0.367ns (35.163%) route 0.677ns (64.837%)) Logic Levels: 0 Clock Path Skew: -0.393ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.670ns Source Clock Delay (SCD): -2.277ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.551 -2.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X93Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y102 FDCE (Prop_fdce_C_Q) 0.367 -1.910 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q net (fo=2, routed) 0.677 -1.233 u_fft_mlkem_axi_slave/mlkem_intr_m SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.672 -2.670 u_fft_mlkem_axi_slave/sys_clk SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.902ns (logic 0.367ns (40.694%) route 0.535ns (59.306%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.367 -1.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.535 -1.218 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[3] SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.908ns (logic 0.367ns (40.413%) route 0.541ns (59.587%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream (clock cpu_clk rise edge) 0.000 0.000 r ======= (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK SLICE_X20Y55 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y55 RAMD32 (Prop_ramd32_CLK_O) 1.084 -0.924 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/O net (fo=1, routed) 0.379 -0.546 u_Axi_CDC/awFifo/_zz_ram_port10[42] SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X50Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y85 FDCE (Prop_fdce_C_Q) 0.367 -1.748 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.541 -1.207 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[1] SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.480ns (logic 1.078ns (72.829%) route 0.402ns (27.171%)) Logic Levels: 0 Clock Path Skew: -0.382ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.405ns Source Clock Delay (SCD): -2.022ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.925ns (logic 0.367ns (39.693%) route 0.558ns (60.307%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.499ns Source Clock Delay (SCD): -2.113ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.715 -2.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X54Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.558 -1.189 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.985ns (logic 0.367ns (37.277%) route 0.618ns (62.723%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.367 -1.755 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.618 -1.138 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1] SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.240ns (logic 1.078ns (86.936%) route 0.162ns (13.064%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.112ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream (clock cpu_clk rise edge) 0.000 0.000 r ======= (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.806 -2.022 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK SLICE_X36Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y56 RAMD32 (Prop_ramd32_CLK_O) 1.078 -0.944 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/O net (fo=1, routed) 0.402 -0.542 u_Axi_CDC/awFifo/_zz_ram_port10[40] SLICE_X35Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/D ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y90 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.034 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O net (fo=1, routed) 0.162 -0.872 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] SLICE_X53Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.937 -2.405 u_Axi_CDC/awFifo/sys_clk SLICE_X35Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.571ns (logic 1.059ns (67.419%) route 0.512ns (32.581%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.495ns Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk SLICE_X53Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.467ns (logic 1.062ns (72.369%) route 0.405ns (27.631%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.502ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream (clock cpu_clk rise edge) 0.000 0.000 r ======= (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y51 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.049 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/O net (fo=1, routed) 0.512 -0.537 u_Axi_CDC/arFifo/_zz_ram_port10__1[5] SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/D ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.055 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O net (fo=1, routed) 0.405 -0.650 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.576ns (logic 1.062ns (67.383%) route 0.514ns (32.617%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.495ns Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y51 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.046 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/O net (fo=1, routed) 0.514 -0.532 u_Axi_CDC/arFifo/_zz_ram_port10__1[3] SLICE_X45Y56 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk SLICE_X45Y56 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.482ns (logic 1.078ns (72.759%) route 0.404ns (27.241%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.394ns Source Clock Delay (SCD): -2.006ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.822 -2.006 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X16Y50 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y50 RAMD32 (Prop_ramd32_CLK_O) 1.078 -0.928 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/O net (fo=1, routed) 0.404 -0.525 u_Axi_CDC/arFifo/_zz_ram_port10__1[46] SLICE_X15Y50 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.948 -2.394 u_Axi_CDC/arFifo/sys_clk SLICE_X15Y50 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.488ns (logic 1.059ns (71.167%) route 0.429ns (28.833%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.395ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) 1.059 -0.948 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/O net (fo=1, routed) 0.429 -0.519 u_Axi_CDC/arFifo/_zz_ram_port10__1[35] SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.493ns (logic 1.062ns (71.119%) route 0.431ns (28.881%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.396ns Source Clock Delay (SCD): -2.008ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK SLICE_X20Y55 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y55 RAMD32 (Prop_ramd32_CLK_O) 1.062 -0.946 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/O net (fo=1, routed) 0.431 -0.515 u_Axi_CDC/awFifo/_zz_ram_port10[45] SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D ======= net (fo=9971, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D >>>>>>> Stashed changes (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.492ns (logic 1.083ns (72.568%) route 0.409ns (27.432%)) Logic Levels: 0 <<<<<<< Updated upstream Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.394ns Source Clock Delay (SCD): -2.006ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.502ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream (clock cpu_clk rise edge) 0.000 0.000 r ======= (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.822 -2.006 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X16Y50 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y50 RAMD32 (Prop_ramd32_CLK_O) 1.083 -0.923 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/O net (fo=1, routed) 0.409 -0.514 u_Axi_CDC/arFifo/_zz_ram_port10__1[44] SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.034 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 0.409 -0.625 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[32] SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.948 -2.394 u_Axi_CDC/arFifo/sys_clk SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.597ns (logic 1.062ns (66.517%) route 0.535ns (33.483%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.495ns Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= net (fo=9971, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.506ns (logic 1.083ns (71.903%) route 0.423ns (28.097%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.118ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream (clock cpu_clk rise edge) 0.000 0.000 r ======= (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.046 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/O net (fo=1, routed) 0.535 -0.512 u_Axi_CDC/arFifo/_zz_ram_port10__1[9] SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.710 -2.118 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.035 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O net (fo=1, routed) 0.423 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.601ns (logic 1.056ns (65.965%) route 0.545ns (34.035%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.496ns Source Clock Delay (SCD): -2.109ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.593ns (logic 1.056ns (66.281%) route 0.537ns (33.719%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.118ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream (clock cpu_clk rise edge) 0.000 0.000 r ======= (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.719 -2.109 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X44Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y54 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.053 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/O net (fo=1, routed) 0.545 -0.508 u_Axi_CDC/arFifo/_zz_ram_port10__1[13] SLICE_X43Y55 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.710 -2.118 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O net (fo=1, routed) 0.537 -0.525 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.846 -2.496 u_Axi_CDC/arFifo/sys_clk SLICE_X43Y55 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.601ns (logic 1.084ns (67.687%) route 0.517ns (32.313%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.495ns Source Clock Delay (SCD): -2.109ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.612ns (logic 1.084ns (67.246%) route 0.528ns (32.754%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.118ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream (clock cpu_clk rise edge) 0.000 0.000 r ======= (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.719 -2.109 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X44Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y54 RAMD32 (Prop_ramd32_CLK_O) 1.084 -1.025 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/O net (fo=1, routed) 0.517 -0.508 u_Axi_CDC/arFifo/_zz_ram_port10__1[12] SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.710 -2.118 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) 1.084 -1.034 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O net (fo=1, routed) 0.528 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36] SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.601ns (logic 1.084ns (67.690%) route 0.517ns (32.310%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.495ns Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns ======= net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.616ns (logic 1.078ns (66.728%) route 0.538ns (33.272%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.502ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns >>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream (clock cpu_clk rise edge) 0.000 0.000 r ======= (clock mlkem_clk rise edge) 0.000 0.000 r >>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll <<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y51 RAMD32 (Prop_ramd32_CLK_O) 1.084 -1.024 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 0.517 -0.507 u_Axi_CDC/arFifo/_zz_ram_port10__1[0] SLICE_X44Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D ======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.039 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O net (fo=1, routed) 0.538 -0.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk SLICE_X44Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/C ======= net (fo=9971, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.651ns (logic 1.062ns (64.315%) route 0.589ns (35.685%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.118ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.710 -2.118 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.056 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O net (fo=1, routed) 0.589 -0.467 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] SLICE_X65Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X65Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.709ns (logic 1.059ns (61.956%) route 0.650ns (38.044%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.502ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.058 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O net (fo=1, routed) 0.650 -0.408 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.843ns (logic 1.059ns (57.448%) route 0.784ns (42.552%)) Logic Levels: 0 Clock Path Skew: -0.375ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.063 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 0.784 -0.279 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.871ns (logic 1.056ns (56.445%) route 0.815ns (43.555%)) Logic Levels: 0 Clock Path Skew: -0.375ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.497ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.065 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.815 -0.250 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.874ns (logic 1.062ns (56.680%) route 0.812ns (43.320%)) Logic Levels: 0 Clock Path Skew: -0.375ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.060 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 0.812 -0.249 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.875ns (logic 1.056ns (56.314%) route 0.819ns (43.686%)) Logic Levels: 0 Clock Path Skew: -0.376ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.065 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.819 -0.246 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25] SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.901ns (logic 1.059ns (55.705%) route 0.842ns (44.295%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.501ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.063 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/O net (fo=1, routed) 0.842 -0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[17] SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.841 -2.501 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.902ns (logic 1.083ns (56.944%) route 0.819ns (43.056%)) Logic Levels: 0 Clock Path Skew: -0.375ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.497ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.038 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 0.819 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.920ns (logic 1.083ns (56.420%) route 0.837ns (43.580%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.501ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.039 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 0.837 -0.203 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[14] SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.841 -2.501 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.937ns (logic 1.083ns (55.902%) route 0.854ns (44.098%)) Logic Levels: 0 Clock Path Skew: -0.378ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.501ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.039 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 0.854 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[20] SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.841 -2.501 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.959ns (logic 1.059ns (54.058%) route 0.900ns (45.942%)) Logic Levels: 0 Clock Path Skew: -0.376ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 0.900 -0.162 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[29] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.974ns (logic 1.059ns (53.657%) route 0.915ns (46.343%)) Logic Levels: 0 Clock Path Skew: -0.376ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) 1.059 -1.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 0.915 -0.148 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5] SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.976ns (logic 1.078ns (54.551%) route 0.898ns (45.449%)) Logic Levels: 0 Clock Path Skew: -0.375ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.044 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.898 -0.146 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.981ns (logic 1.083ns (54.682%) route 0.898ns (45.318%)) Logic Levels: 0 Clock Path Skew: -0.375ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.497ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.038 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 0.898 -0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.984ns (logic 1.056ns (53.233%) route 0.928ns (46.767%)) Logic Levels: 0 Clock Path Skew: -0.375ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.066 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.928 -0.139 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.988ns (logic 1.062ns (53.409%) route 0.926ns (46.591%)) Logic Levels: 0 Clock Path Skew: -0.376ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.059 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 0.926 -0.133 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[9] SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.996ns (logic 1.056ns (52.902%) route 0.940ns (47.098%)) Logic Levels: 0 Clock Path Skew: -0.375ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.066 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.940 -0.126 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.999ns (logic 1.062ns (53.120%) route 0.937ns (46.880%)) Logic Levels: 0 Clock Path Skew: -0.375ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.497ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.059 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 0.937 -0.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[27] SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.000ns (logic 1.062ns (53.096%) route 0.938ns (46.904%)) Logic Levels: 0 Clock Path Skew: -0.376ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.059 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O net (fo=1, routed) 0.938 -0.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.001ns (logic 1.078ns (53.864%) route 0.923ns (46.136%)) Logic Levels: 0 Clock Path Skew: -0.375ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.044 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.923 -0.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.011ns (logic 1.084ns (53.891%) route 0.927ns (46.109%)) Logic Levels: 0 Clock Path Skew: -0.376ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) 1.084 -1.037 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.927 -0.110 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.019ns (logic 1.084ns (53.691%) route 0.935ns (46.309%)) Logic Levels: 0 Clock Path Skew: -0.375ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) 1.084 -1.038 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.935 -0.103 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.020ns (logic 1.083ns (53.627%) route 0.937ns (46.373%)) Logic Levels: 0 Clock Path Skew: -0.376ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) 1.083 -1.038 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 0.937 -0.102 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[2] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.031ns (logic 1.084ns (53.380%) route 0.947ns (46.620%)) Logic Levels: 0 Clock Path Skew: -0.376ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) 1.084 -1.037 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 0.947 -0.091 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.081ns (logic 1.056ns (50.757%) route 1.025ns (49.243%)) Logic Levels: 0 Clock Path Skew: -0.376ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.065 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 1.025 -0.041 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7] SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/C >>>>>>> Stashed changes -------------------------------------------------------------------------------------- Path Group: (none) From Clock: clkfbout_clk_pll To Clock: Max Delay 0 Endpoints Min Delay 1 Endpoint -------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT (clock source 'clkfbout_clk_pll' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Path Group: (none) Path Type: Min at Slow Process Corner Data Path Delay: 3.498ns (logic 0.091ns (2.602%) route 3.407ns (97.398%)) Logic Levels: 1 (BUFG=1) Clock Uncertainty: 0.225ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.110ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clkfbout_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/clkfbout_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkf_buf/O net (fo=1, routed) 1.652 -2.177 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: Max Delay 0 Endpoints Min Delay 41 Endpoints -------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 (clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_clk (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.614ns (logic 1.260ns (48.196%) route 1.354ns (51.804%)) Logic Levels: 2 (BUFG=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.794 -0.468 video_clk_OBUF ======= net (fo=9971, routed) 0.794 -0.468 video_clk_OBUF >>>>>>> Stashed changes H22 OBUF (Prop_obuf_I_O) 1.234 0.766 r video_clk_OBUF_inst/O net (fo=0) 0.000 0.766 video_clk H22 r video_clk (OUT) ------------------------------------------------------------------- ------------------- Slack: inf <<<<<<< Updated upstream Source: u_confreg/led_data_reg[15]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[15] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.765ns (logic 1.404ns (50.799%) route 1.360ns (49.201%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.721 -0.541 u_confreg/sys_clk SLICE_X0Y84 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[15]_lopt_replica/Q net (fo=1, routed) 1.360 0.960 lopt_6 B20 OBUF (Prop_obuf_I_O) 1.263 2.223 r leds_OBUF[15]_inst/O net (fo=0) 0.000 2.223 leds[15] B20 r leds[15] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[12]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[12] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.814ns (logic 1.384ns (49.180%) route 1.430ns (50.820%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.721 -0.541 u_confreg/sys_clk SLICE_X0Y85 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[12]_lopt_replica/Q net (fo=1, routed) 1.430 1.030 lopt_3 D20 OBUF (Prop_obuf_I_O) 1.243 2.273 r leds_OBUF[12]_inst/O net (fo=0) 0.000 2.273 leds[12] D20 r leds[12] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[7]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[7] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.837ns (logic 1.414ns (49.822%) route 1.424ns (50.178%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.718 -0.544 u_confreg/sys_clk SLICE_X0Y81 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y81 FDRE (Prop_fdre_C_Q) 0.141 -0.403 r u_confreg/led_data_reg[7]_lopt_replica/Q net (fo=1, routed) 1.424 1.020 lopt_13 B22 OBUF (Prop_obuf_I_O) 1.273 2.293 r leds_OBUF[7]_inst/O net (fo=0) 0.000 2.293 leds[7] B22 r leds[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[10]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[10] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.845ns (logic 1.389ns (48.821%) route 1.456ns (51.179%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.718 -0.544 u_confreg/sys_clk SLICE_X1Y81 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X1Y81 FDRE (Prop_fdre_C_Q) 0.141 -0.403 r u_confreg/led_data_reg[10]_lopt_replica/Q net (fo=1, routed) 1.456 1.052 lopt_1 D21 OBUF (Prop_obuf_I_O) 1.248 2.300 r leds_OBUF[10]_inst/O net (fo=0) 0.000 2.300 leds[10] D21 r leds[10] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.867ns (logic 1.416ns (49.395%) route 1.451ns (50.605%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[0]_lopt_replica/Q net (fo=1, routed) 1.451 1.053 lopt B24 OBUF (Prop_obuf_I_O) 1.275 2.328 r leds_OBUF[0]_inst/O net (fo=0) 0.000 2.328 leds[0] B24 r leds[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[4]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[4] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.934ns (logic 1.404ns (47.847%) route 1.530ns (52.153%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.715 -0.547 u_confreg/sys_clk SLICE_X0Y78 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y78 FDRE (Prop_fdre_C_Q) 0.141 -0.406 r u_confreg/led_data_reg[4]_lopt_replica/Q net (fo=1, routed) 1.530 1.124 lopt_10 C22 OBUF (Prop_obuf_I_O) 1.263 2.386 r leds_OBUF[4]_inst/O net (fo=0) 0.000 2.386 leds[4] C22 r leds[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[6]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[6] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.974ns (logic 1.383ns (46.512%) route 1.591ns (53.488%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.715 -0.547 u_confreg/sys_clk SLICE_X0Y78 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y78 FDRE (Prop_fdre_C_Q) 0.141 -0.406 r u_confreg/led_data_reg[6]_lopt_replica/Q net (fo=1, routed) 1.591 1.185 lopt_12 E20 OBUF (Prop_obuf_I_O) 1.242 2.427 r leds_OBUF[6]_inst/O net (fo=0) 0.000 2.427 leds[6] E20 r leds[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[11]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[11] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.976ns (logic 1.408ns (47.324%) route 1.568ns (52.676%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[11]_lopt_replica/Q net (fo=1, routed) 1.568 1.169 lopt_2 A18 OBUF (Prop_obuf_I_O) 1.267 2.436 r leds_OBUF[11]_inst/O net (fo=0) 0.000 2.436 leds[11] A18 r leds[11] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[5] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.051ns (logic 1.388ns (45.475%) route 1.664ns (54.525%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q net (fo=1, routed) 1.664 1.267 dpy0_OBUF[5] C19 OBUF (Prop_obuf_I_O) 1.247 2.514 r dpy0_OBUF[5]_inst/O net (fo=0) 0.000 2.514 dpy0[5] C19 r dpy0[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_RX (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.985ns (logic 0.965ns (32.328%) route 2.020ns (67.672%)) Logic Levels: 1 (OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.795 -0.468 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X3Y39 FDSE r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y39 FDSE (Prop_fdse_C_Q) 0.141 -0.327 r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/Q net (fo=28, routed) 2.020 1.693 UART_RX_IOBUF_inst/T J20 OBUFT (TriStatD_obuft_T_O) 0.824 2.517 r UART_RX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 2.517 UART_RX J20 r UART_RX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[5]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[5] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.109ns (logic 1.435ns (46.158%) route 1.674ns (53.842%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r u_confreg/led_data_reg[5]_lopt_replica/Q net (fo=1, routed) 1.674 1.263 lopt_11 C21 OBUF (Prop_obuf_I_O) 1.307 2.570 r leds_OBUF[5]_inst/O net (fo=0) 0.000 2.570 leds[5] C21 r leds[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/transmitter/stx_o_tmp_reg/C (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_TX (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.056ns (logic 1.416ns (46.332%) route 1.640ns (53.668%)) Logic Levels: 2 (LUT4=1 OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.796 -0.467 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X0Y41 FDSE r u_axi_uart_controller/uart0/regs/transmitter/stx_o_tmp_reg/C ------------------------------------------------------------------- ------------------- SLICE_X0Y41 FDSE (Prop_fdse_C_Q) 0.141 -0.326 r u_axi_uart_controller/uart0/regs/transmitter/stx_o_tmp_reg/Q net (fo=5, routed) 0.136 -0.189 u_axi_uart_controller/uart0/regs/transmitter/stx_o_tmp_reg_0 SLICE_X0Y40 LUT4 (Prop_lut4_I1_O) 0.045 -0.144 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_1/O net (fo=1, routed) 1.504 1.360 UART_TX_IOBUF_inst/I H18 OBUFT (Prop_obuft_I_O) 1.230 2.590 r UART_TX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 2.590 UART_TX H18 r UART_TX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.150ns (logic 1.400ns (44.449%) route 1.750ns (55.551%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q net (fo=1, routed) 1.750 1.353 dpy0_OBUF[2] B21 OBUF (Prop_obuf_I_O) 1.259 2.612 r dpy0_OBUF[2]_inst/O net (fo=0) 0.000 2.612 dpy0[2] B21 r dpy0[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.168ns (logic 1.402ns (44.239%) route 1.767ns (55.761%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q net (fo=1, routed) 1.767 1.370 dpy0_OBUF[0] B19 OBUF (Prop_obuf_I_O) 1.261 2.631 r dpy0_OBUF[0]_inst/O net (fo=0) 0.000 2.631 dpy0[0] B19 r dpy0[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[3] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.170ns (logic 1.415ns (44.629%) route 1.755ns (55.371%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q net (fo=1, routed) 1.755 1.359 dpy0_OBUF[3] A19 OBUF (Prop_obuf_I_O) 1.274 2.632 r dpy0_OBUF[3]_inst/O net (fo=0) 0.000 2.632 dpy0[3] A19 r dpy0[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[6] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.175ns (logic 1.379ns (43.433%) route 1.796ns (56.567%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q net (fo=1, routed) 1.796 1.398 dpy1_OBUF[6] F15 OBUF (Prop_obuf_I_O) 1.238 2.636 r dpy1_OBUF[6]_inst/O net (fo=0) 0.000 2.636 dpy1[6] F15 r dpy1[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[3]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[3] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.180ns (logic 1.444ns (45.406%) route 1.736ns (54.594%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r u_confreg/led_data_reg[3]_lopt_replica/Q net (fo=1, routed) 1.736 1.324 lopt_9 D23 OBUF (Prop_obuf_I_O) 1.316 2.640 r leds_OBUF[3]_inst/O net (fo=0) 0.000 2.640 leds[3] D23 r leds[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.210ns (logic 1.391ns (43.329%) route 1.819ns (56.671%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q net (fo=1, routed) 1.819 1.422 dpy1_OBUF[1] D16 OBUF (Prop_obuf_I_O) 1.250 2.671 r dpy1_OBUF[1]_inst/O net (fo=0) 0.000 2.671 dpy1[1] D16 r dpy1[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[4] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.257ns (logic 1.383ns (42.471%) route 1.874ns (57.529%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q net (fo=1, routed) 1.874 1.476 dpy1_OBUF[4] E16 OBUF (Prop_obuf_I_O) 1.242 2.719 r dpy1_OBUF[4]_inst/O net (fo=0) 0.000 2.719 dpy1[4] E16 r dpy1[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[3] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.258ns (logic 1.356ns (41.632%) route 1.902ns (58.368%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q net (fo=1, routed) 1.902 1.504 dpy1_OBUF[3] F17 OBUF (Prop_obuf_I_O) 1.215 2.719 r dpy1_OBUF[3]_inst/O net (fo=0) 0.000 2.719 dpy1[3] F17 r dpy1[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.344ns (logic 1.387ns (41.472%) route 1.957ns (58.528%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q net (fo=1, routed) 1.957 1.561 dpy0_OBUF[1] D19 OBUF (Prop_obuf_I_O) 1.246 2.807 r dpy0_OBUF[1]_inst/O net (fo=0) 0.000 2.807 dpy0[1] D19 r dpy0[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[14]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[14] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.393ns (logic 1.404ns (41.392%) route 1.989ns (58.608%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[14]_lopt_replica/Q net (fo=1, routed) 1.989 1.590 lopt_5 A20 OBUF (Prop_obuf_I_O) 1.263 2.854 r leds_OBUF[14]_inst/O net (fo=0) 0.000 2.854 leds[14] A20 r leds[14] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[6] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.619ns (logic 1.398ns (38.631%) route 2.221ns (61.369%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q net (fo=1, routed) 2.221 1.825 dpy0_OBUF[6] B17 OBUF (Prop_obuf_I_O) 1.257 3.082 r dpy0_OBUF[6]_inst/O net (fo=0) 0.000 3.082 dpy0[6] B17 r dpy0[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.636ns (logic 1.407ns (38.697%) route 2.229ns (61.303%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q net (fo=1, routed) 2.229 1.831 dpy1_OBUF[0] A17 OBUF (Prop_obuf_I_O) 1.266 3.097 r dpy1_OBUF[0]_inst/O net (fo=0) 0.000 3.097 dpy1[0] A17 r dpy1[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_vsync (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.669ns (logic 1.482ns (40.396%) route 2.187ns (59.604%)) Logic Levels: 3 (LUT4=1 LUT6=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.716 -0.546 u_axi_dvi/sys_clk SLICE_X1Y79 FDRE r u_axi_dvi/vdata_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y79 FDRE (Prop_fdre_C_Q) 0.141 -0.405 r u_axi_dvi/vdata_reg[0]/Q net (fo=13, routed) 0.170 -0.236 u_axi_dvi/vdata_reg_n_0_[0] SLICE_X1Y79 LUT6 (Prop_lut6_I3_O) 0.045 -0.191 r u_axi_dvi/video_vsync_OBUF_inst_i_2/O net (fo=1, routed) 0.189 -0.001 u_axi_dvi/video_vsync_OBUF_inst_i_2_n_0 SLICE_X1Y80 LUT4 (Prop_lut4_I0_O) 0.045 0.044 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O net (fo=1, routed) 1.828 1.872 video_vsync_OBUF H24 OBUF (Prop_obuf_I_O) 1.251 3.123 r video_vsync_OBUF_inst/O net (fo=0) 0.000 3.123 video_vsync H24 r video_vsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[7] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.661ns (logic 1.386ns (37.869%) route 2.275ns (62.131%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q net (fo=1, routed) 2.275 1.878 dpy0_OBUF[7] C17 OBUF (Prop_obuf_I_O) 1.245 3.124 r dpy0_OBUF[7]_inst/O net (fo=0) 0.000 3.124 dpy0[7] C17 r dpy0[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[4] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.691ns (logic 1.381ns (37.421%) route 2.309ns (62.579%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q net (fo=1, routed) 2.309 1.913 dpy0_OBUF[4] E18 OBUF (Prop_obuf_I_O) 1.240 3.153 r dpy0_OBUF[4]_inst/O net (fo=0) 0.000 3.153 dpy0[4] E18 r dpy0[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[11]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_de (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.778ns (logic 1.447ns (38.313%) route 2.330ns (61.687%)) Logic Levels: 2 (LUT6=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.713 -0.549 u_axi_dvi/sys_clk SLICE_X0Y76 FDRE r u_axi_dvi/vdata_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y76 FDRE (Prop_fdre_C_Q) 0.141 -0.408 f u_axi_dvi/vdata_reg[11]/Q net (fo=11, routed) 0.358 -0.050 u_axi_dvi/vdata_reg_n_0_[11] SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.045 -0.005 r u_axi_dvi/video_de_OBUF_inst_i_1/O net (fo=1, routed) 1.972 1.967 video_de_OBUF G24 OBUF (Prop_obuf_I_O) 1.261 3.228 r video_de_OBUF_inst/O net (fo=0) 0.000 3.228 video_de G24 r video_de (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.808ns (logic 1.383ns (36.327%) route 2.425ns (63.673%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q net (fo=1, routed) 2.425 2.027 dpy1_OBUF[2] E17 OBUF (Prop_obuf_I_O) 1.242 3.270 r dpy1_OBUF[2]_inst/O net (fo=0) 0.000 3.270 dpy1[2] E17 r dpy1[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.856ns (logic 1.671ns (43.330%) route 2.185ns (56.670%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.712 -0.550 u_axi_dvi/sys_clk SLICE_X0Y74 FDRE r u_axi_dvi/vdata_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y74 FDRE (Prop_fdre_C_Q) 0.141 -0.409 r u_axi_dvi/vdata_reg[2]/Q net (fo=12, routed) 0.241 -0.169 u_axi_dvi/vdata_reg_n_0_[2] SLICE_X2Y73 LUT4 (Prop_lut4_I2_O) 0.047 -0.122 r u_axi_dvi/video_red_OBUF[2]_inst_i_53/O net (fo=1, routed) 0.000 -0.122 u_axi_dvi/video_red_OBUF[2]_inst_i_53_n_0 SLICE_X2Y73 CARRY4 (Prop_carry4_DI[1]_CO[3]) 0.111 -0.011 r u_axi_dvi/video_red_OBUF[2]_inst_i_19/CO[3] net (fo=1, routed) 0.000 -0.011 u_axi_dvi/video_red_OBUF[2]_inst_i_19_n_0 SLICE_X2Y74 CARRY4 (Prop_carry4_CI_CO[3]) 0.040 0.029 r u_axi_dvi/video_red_OBUF[2]_inst_i_4/CO[3] net (fo=1, routed) 0.222 0.252 u_axi_dvi/vdata1_in_range07_in SLICE_X6Y74 LUT5 (Prop_lut5_I2_O) 0.045 0.297 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 1.722 2.019 video_red_OBUF[0] E26 OBUF (Prop_obuf_I_O) 1.287 3.306 r video_red_OBUF[2]_inst/O net (fo=0) 0.000 3.306 video_red[2] E26 r video_red[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.955ns (logic 1.645ns (41.586%) route 2.310ns (58.414%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.712 -0.550 u_axi_dvi/sys_clk SLICE_X0Y74 FDRE r u_axi_dvi/vdata_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y74 FDRE (Prop_fdre_C_Q) 0.141 -0.409 r u_axi_dvi/vdata_reg[2]/Q net (fo=12, routed) 0.241 -0.169 u_axi_dvi/vdata_reg_n_0_[2] SLICE_X2Y73 LUT4 (Prop_lut4_I2_O) 0.047 -0.122 r u_axi_dvi/video_red_OBUF[2]_inst_i_53/O net (fo=1, routed) 0.000 -0.122 u_axi_dvi/video_red_OBUF[2]_inst_i_53_n_0 SLICE_X2Y73 CARRY4 (Prop_carry4_DI[1]_CO[3]) 0.111 -0.011 r u_axi_dvi/video_red_OBUF[2]_inst_i_19/CO[3] net (fo=1, routed) 0.000 -0.011 u_axi_dvi/video_red_OBUF[2]_inst_i_19_n_0 SLICE_X2Y74 CARRY4 (Prop_carry4_CI_CO[3]) 0.040 0.029 r u_axi_dvi/video_red_OBUF[2]_inst_i_4/CO[3] net (fo=1, routed) 0.222 0.252 u_axi_dvi/vdata1_in_range07_in SLICE_X6Y74 LUT5 (Prop_lut5_I2_O) 0.045 0.297 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 1.847 2.144 video_red_OBUF[0] F24 OBUF (Prop_obuf_I_O) 1.261 3.405 r video_red_OBUF[1]_inst/O net (fo=0) 0.000 3.405 video_red[1] F24 r video_red[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.987ns (logic 1.617ns (40.568%) route 2.370ns (59.432%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.712 -0.550 u_axi_dvi/sys_clk SLICE_X0Y74 FDRE r u_axi_dvi/vdata_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y74 FDRE (Prop_fdre_C_Q) 0.141 -0.409 r u_axi_dvi/vdata_reg[2]/Q net (fo=12, routed) 0.241 -0.169 u_axi_dvi/vdata_reg_n_0_[2] SLICE_X2Y73 LUT4 (Prop_lut4_I2_O) 0.047 -0.122 r u_axi_dvi/video_red_OBUF[2]_inst_i_53/O net (fo=1, routed) 0.000 -0.122 u_axi_dvi/video_red_OBUF[2]_inst_i_53_n_0 SLICE_X2Y73 CARRY4 (Prop_carry4_DI[1]_CO[3]) 0.111 -0.011 r u_axi_dvi/video_red_OBUF[2]_inst_i_19/CO[3] net (fo=1, routed) 0.000 -0.011 u_axi_dvi/video_red_OBUF[2]_inst_i_19_n_0 SLICE_X2Y74 CARRY4 (Prop_carry4_CI_CO[3]) 0.040 0.029 r u_axi_dvi/video_red_OBUF[2]_inst_i_4/CO[3] net (fo=1, routed) 0.222 0.252 u_axi_dvi/vdata1_in_range07_in SLICE_X6Y74 LUT5 (Prop_lut5_I2_O) 0.045 0.297 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 1.907 2.203 video_red_OBUF[0] K23 OBUF (Prop_obuf_I_O) 1.233 3.437 r video_red_OBUF[0]_inst/O net (fo=0) 0.000 3.437 video_red[0] K23 r video_red[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[11]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_hsync (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.159ns (logic 1.455ns (34.973%) route 2.705ns (65.027%)) Logic Levels: 2 (LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.712 -0.550 u_axi_dvi/sys_clk SLICE_X6Y72 FDRE r u_axi_dvi/hdata_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y72 FDRE (Prop_fdre_C_Q) 0.164 -0.386 f u_axi_dvi/hdata_reg[11]/Q net (fo=12, routed) 0.410 0.023 u_axi_dvi/hdata_reg_n_0_[11] SLICE_X0Y72 LUT5 (Prop_lut5_I1_O) 0.045 0.068 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O net (fo=1, routed) 2.295 2.363 video_hsync_OBUF J24 OBUF (Prop_obuf_I_O) 1.246 3.609 r video_hsync_OBUF_inst/O net (fo=0) 0.000 3.609 video_hsync J24 r video_hsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[7] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.208ns (logic 1.362ns (32.369%) route 2.846ns (67.631%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q net (fo=1, routed) 2.846 2.449 dpy1_OBUF[7] G17 OBUF (Prop_obuf_I_O) 1.221 3.670 r dpy1_OBUF[7]_inst/O net (fo=0) 0.000 3.670 dpy1[7] G17 r dpy1[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[8]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[8] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.363ns (logic 1.443ns (33.063%) route 2.921ns (66.937%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r u_confreg/led_data_reg[8]_lopt_replica/Q net (fo=1, routed) 2.921 2.509 lopt_14 C23 OBUF (Prop_obuf_I_O) 1.315 3.824 r leds_OBUF[8]_inst/O net (fo=0) 0.000 3.824 leds[8] C23 r leds[8] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[2]_lopt_replica/C ======= Source: u_confreg/led_data_reg[9]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[9] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.581ns (logic 1.447ns (56.055%) route 1.134ns (43.945%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X14Y141 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X14Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[9]_lopt_replica/Q net (fo=1, routed) 1.134 0.663 lopt_15 A23 OBUF (Prop_obuf_I_O) 1.283 1.946 r leds_OBUF[9]_inst/O net (fo=0) 0.000 1.946 leds[9] A23 r leds[9] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[15]_lopt_replica/C >>>>>>> Stashed changes (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner <<<<<<< Updated upstream Data Path Delay: 4.375ns (logic 1.428ns (32.639%) route 2.947ns (67.361%)) ======= Data Path Delay: 2.597ns (logic 1.427ns (54.964%) route 1.170ns (45.036%)) >>>>>>> Stashed changes Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.721 -0.541 u_confreg/sys_clk SLICE_X0Y84 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[2]_lopt_replica/Q net (fo=1, routed) 2.947 2.547 lopt_8 A24 OBUF (Prop_obuf_I_O) 1.287 3.834 r leds_OBUF[2]_inst/O net (fo=0) 0.000 3.834 leds[2] A24 r leds[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[9]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[9] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.395ns (logic 1.424ns (32.390%) route 2.972ns (67.610%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.721 -0.541 u_confreg/sys_clk SLICE_X0Y84 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[9]_lopt_replica/Q net (fo=1, routed) 2.972 2.571 lopt_15 A23 OBUF (Prop_obuf_I_O) 1.283 3.854 r leds_OBUF[9]_inst/O net (fo=0) 0.000 3.854 leds[9] A23 r leds[9] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[1]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.695ns (logic 1.424ns (30.329%) route 3.271ns (69.671%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r u_confreg/led_data_reg[1]_lopt_replica/Q net (fo=1, routed) 3.271 2.860 lopt_7 E21 OBUF (Prop_obuf_I_O) 1.296 4.155 r leds_OBUF[1]_inst/O net (fo=0) 0.000 4.155 leds[1] E21 r leds[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[13]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[13] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.756ns (logic 1.412ns (29.687%) route 3.344ns (70.313%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[13]_lopt_replica/Q net (fo=1, routed) 3.344 2.946 lopt_4 A22 OBUF (Prop_obuf_I_O) 1.271 4.217 r leds_OBUF[13]_inst/O net (fo=0) 0.000 4.217 leds[13] A22 r leds[13] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[5] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 5.792ns (logic 1.376ns (23.753%) route 4.416ns (76.247%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q net (fo=1, routed) 4.416 4.019 dpy1_OBUF[5] G16 OBUF (Prop_obuf_I_O) 1.235 5.254 r dpy1_OBUF[5]_inst/O net (fo=0) 0.000 5.254 dpy1[5] G16 r dpy1[5] (OUT) ======= net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X12Y142 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[15]_lopt_replica/Q net (fo=1, routed) 1.170 0.699 lopt_6 B20 OBUF (Prop_obuf_I_O) 1.263 1.962 r leds_OBUF[15]_inst/O net (fo=0) 0.000 1.962 leds[15] B20 r leds[15] (OUT) >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[10]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[10] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.666ns (logic 1.412ns (52.947%) route 1.255ns (47.053%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk SLICE_X20Y141 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X20Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[10]_lopt_replica/Q net (fo=1, routed) 1.255 0.781 lopt_1 D21 OBUF (Prop_obuf_I_O) 1.248 2.028 r leds_OBUF[10]_inst/O net (fo=0) 0.000 2.028 leds[10] D21 r leds[10] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[12]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[12] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.709ns (logic 1.384ns (51.091%) route 1.325ns (48.909%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X13Y142 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X13Y142 FDRE (Prop_fdre_C_Q) 0.141 -0.494 r u_confreg/led_data_reg[12]_lopt_replica/Q net (fo=1, routed) 1.325 0.831 lopt_3 D20 OBUF (Prop_obuf_I_O) 1.243 2.074 r leds_OBUF[12]_inst/O net (fo=0) 0.000 2.074 leds[12] D20 r leds[12] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.736ns (logic 1.439ns (52.603%) route 1.297ns (47.397%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk SLICE_X22Y141 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[0]_lopt_replica/Q net (fo=1, routed) 1.297 0.823 lopt B24 OBUF (Prop_obuf_I_O) 1.275 2.098 r leds_OBUF[0]_inst/O net (fo=0) 0.000 2.098 leds[0] B24 r leds[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[11]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[11] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.765ns (logic 1.431ns (51.772%) route 1.333ns (48.228%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X12Y141 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[11]_lopt_replica/Q net (fo=1, routed) 1.333 0.862 lopt_2 A18 OBUF (Prop_obuf_I_O) 1.267 2.130 r leds_OBUF[11]_inst/O net (fo=0) 0.000 2.130 leds[11] A18 r leds[11] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[1]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.956ns (logic 1.406ns (47.555%) route 1.550ns (52.445%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X12Y142 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[1]_lopt_replica/Q net (fo=1, routed) 1.550 1.079 lopt_7 E21 OBUF (Prop_obuf_I_O) 1.242 2.321 r leds_OBUF[1]_inst/O net (fo=0) 0.000 2.321 leds[1] E21 r leds[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[13]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[13] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.031ns (logic 1.412ns (46.583%) route 1.619ns (53.417%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X13Y142 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X13Y142 FDRE (Prop_fdre_C_Q) 0.141 -0.494 r u_confreg/led_data_reg[13]_lopt_replica/Q net (fo=1, routed) 1.619 1.125 lopt_4 A22 OBUF (Prop_obuf_I_O) 1.271 2.396 r leds_OBUF[13]_inst/O net (fo=0) 0.000 2.396 leds[13] A22 r leds[13] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[5]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[5] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.069ns (logic 1.418ns (46.208%) route 1.651ns (53.792%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk SLICE_X20Y141 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X20Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[5]_lopt_replica/Q net (fo=1, routed) 1.651 1.177 lopt_11 C21 OBUF (Prop_obuf_I_O) 1.254 2.431 r leds_OBUF[5]_inst/O net (fo=0) 0.000 2.431 leds[5] C21 r leds[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[3]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[3] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.092ns (logic 1.427ns (46.147%) route 1.665ns (53.853%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.617 -0.646 u_confreg/sys_clk SLICE_X36Y141 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X36Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.482 r u_confreg/led_data_reg[3]_lopt_replica/Q net (fo=1, routed) 1.665 1.183 lopt_9 D23 OBUF (Prop_obuf_I_O) 1.263 2.446 r leds_OBUF[3]_inst/O net (fo=0) 0.000 2.446 leds[3] D23 r leds[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[8]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[8] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.086ns (logic 1.426ns (46.198%) route 1.660ns (53.802%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk SLICE_X22Y141 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[8]_lopt_replica/Q net (fo=1, routed) 1.660 1.186 lopt_14 C23 OBUF (Prop_obuf_I_O) 1.262 2.448 r leds_OBUF[8]_inst/O net (fo=0) 0.000 2.448 leds[8] C23 r leds[8] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[4]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[4] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.088ns (logic 1.427ns (46.209%) route 1.661ns (53.791%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk SLICE_X22Y141 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[4]_lopt_replica/Q net (fo=1, routed) 1.661 1.187 lopt_10 C22 OBUF (Prop_obuf_I_O) 1.263 2.450 r leds_OBUF[4]_inst/O net (fo=0) 0.000 2.450 leds[4] C22 r leds[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[7]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[7] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.095ns (logic 1.437ns (46.407%) route 1.659ns (53.593%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X12Y142 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[7]_lopt_replica/Q net (fo=1, routed) 1.659 1.188 lopt_13 B22 OBUF (Prop_obuf_I_O) 1.273 2.461 r leds_OBUF[7]_inst/O net (fo=0) 0.000 2.461 leds[7] B22 r leds[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[6]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[6] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.132ns (logic 1.406ns (44.897%) route 1.726ns (55.103%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X12Y142 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[6]_lopt_replica/Q net (fo=1, routed) 1.726 1.255 lopt_12 E20 OBUF (Prop_obuf_I_O) 1.242 2.497 r leds_OBUF[6]_inst/O net (fo=0) 0.000 2.497 leds[6] E20 r leds[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[14]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[14] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.179ns (logic 1.427ns (44.902%) route 1.752ns (55.098%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk SLICE_X22Y141 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[14]_lopt_replica/Q net (fo=1, routed) 1.752 1.278 lopt_5 A20 OBUF (Prop_obuf_I_O) 1.263 2.541 r leds_OBUF[14]_inst/O net (fo=0) 0.000 2.541 leds[14] A20 r leds[14] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[2]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.213ns (logic 1.451ns (45.157%) route 1.762ns (54.843%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.617 -0.646 u_confreg/sys_clk SLICE_X36Y140 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X36Y140 FDRE (Prop_fdre_C_Q) 0.164 -0.482 r u_confreg/led_data_reg[2]_lopt_replica/Q net (fo=1, routed) 1.762 1.280 lopt_8 A24 OBUF (Prop_obuf_I_O) 1.287 2.567 r leds_OBUF[2]_inst/O net (fo=0) 0.000 2.567 leds[2] A24 r leds[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_TX (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.463ns (logic 1.033ns (29.825%) route 2.430ns (70.175%)) Logic Levels: 2 (LUT3=1 OBUFT=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.572 -0.691 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X76Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C ------------------------------------------------------------------- ------------------- SLICE_X76Y137 FDRE (Prop_fdre_C_Q) 0.164 -0.527 r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/Q net (fo=2, routed) 0.147 -0.380 u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en SLICE_X77Y137 LUT3 (Prop_lut3_I0_O) 0.045 -0.335 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O net (fo=1, routed) 2.283 1.949 UART_TX_IOBUF_inst/T H18 OBUFT (TriStatD_obuft_T_O) 0.824 2.773 r UART_TX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 2.773 UART_TX H18 r UART_TX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.498ns (logic 1.406ns (40.207%) route 2.091ns (59.793%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q net (fo=1, routed) 2.091 1.566 dpy1_OBUF[2] E17 OBUF (Prop_obuf_I_O) 1.242 2.808 r dpy1_OBUF[2]_inst/O net (fo=0) 0.000 2.808 dpy1[2] E17 r dpy1[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.553ns (logic 1.387ns (39.035%) route 2.166ns (60.965%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q net (fo=1, routed) 2.166 1.625 dpy0_OBUF[1] D19 OBUF (Prop_obuf_I_O) 1.246 2.871 r dpy0_OBUF[1]_inst/O net (fo=0) 0.000 2.871 dpy0[1] D19 r dpy0[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.658ns (logic 1.400ns (38.270%) route 2.258ns (61.730%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q net (fo=1, routed) 2.258 1.717 dpy0_OBUF[2] B21 OBUF (Prop_obuf_I_O) 1.259 2.976 r dpy0_OBUF[2]_inst/O net (fo=0) 0.000 2.976 dpy0[2] B21 r dpy0[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.681ns (logic 1.430ns (38.848%) route 2.251ns (61.152%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q net (fo=1, routed) 2.251 1.725 dpy1_OBUF[0] A17 OBUF (Prop_obuf_I_O) 1.266 2.991 r dpy1_OBUF[0]_inst/O net (fo=0) 0.000 2.991 dpy1[0] A17 r dpy1[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.690ns (logic 1.414ns (38.316%) route 2.276ns (61.684%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q net (fo=1, routed) 2.276 1.750 dpy1_OBUF[1] D16 OBUF (Prop_obuf_I_O) 1.250 3.000 r dpy1_OBUF[1]_inst/O net (fo=0) 0.000 3.000 dpy1[1] D16 r dpy1[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[3] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.708ns (logic 1.438ns (38.776%) route 2.270ns (61.224%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.164 -0.518 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q net (fo=1, routed) 2.270 1.752 dpy0_OBUF[3] A19 OBUF (Prop_obuf_I_O) 1.274 3.026 r dpy0_OBUF[3]_inst/O net (fo=0) 0.000 3.026 dpy0[3] A19 r dpy0[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[5] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.719ns (logic 1.399ns (37.614%) route 2.320ns (62.386%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q net (fo=1, routed) 2.320 1.794 dpy1_OBUF[5] G16 OBUF (Prop_obuf_I_O) 1.235 3.029 r dpy1_OBUF[5]_inst/O net (fo=0) 0.000 3.029 dpy1[5] G16 r dpy1[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[4] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.719ns (logic 1.406ns (37.816%) route 2.313ns (62.184%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q net (fo=1, routed) 2.313 1.787 dpy1_OBUF[4] E16 OBUF (Prop_obuf_I_O) 1.242 3.029 r dpy1_OBUF[4]_inst/O net (fo=0) 0.000 3.029 dpy1[4] E16 r dpy1[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_RX (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.734ns (logic 0.988ns (26.459%) route 2.746ns (73.541%)) Logic Levels: 1 (OBUFT=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.563 -0.700 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X80Y133 FDSE r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y133 FDSE (Prop_fdse_C_Q) 0.164 -0.536 r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/Q net (fo=28, routed) 2.746 2.210 UART_RX_IOBUF_inst/T J20 OBUFT (TriStatD_obuft_T_O) 0.824 3.034 r UART_RX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 3.034 UART_RX J20 r UART_RX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[6] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.726ns (logic 1.402ns (37.617%) route 2.325ns (62.383%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q net (fo=1, routed) 2.325 1.799 dpy1_OBUF[6] F15 OBUF (Prop_obuf_I_O) 1.238 3.037 r dpy1_OBUF[6]_inst/O net (fo=0) 0.000 3.037 dpy1[6] F15 r dpy1[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[3] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.738ns (logic 1.379ns (36.896%) route 2.359ns (63.104%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q net (fo=1, routed) 2.359 1.833 dpy1_OBUF[3] F17 OBUF (Prop_obuf_I_O) 1.215 3.049 r dpy1_OBUF[3]_inst/O net (fo=0) 0.000 3.049 dpy1[3] F17 r dpy1[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[5] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.812ns (logic 1.388ns (36.398%) route 2.425ns (63.602%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q net (fo=1, routed) 2.425 1.884 dpy0_OBUF[5] C19 OBUF (Prop_obuf_I_O) 1.247 3.130 r dpy0_OBUF[5]_inst/O net (fo=0) 0.000 3.130 dpy0[5] C19 r dpy0[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[7] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.845ns (logic 1.385ns (36.025%) route 2.460ns (63.975%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q net (fo=1, routed) 2.460 1.934 dpy1_OBUF[7] G17 OBUF (Prop_obuf_I_O) 1.221 3.155 r dpy1_OBUF[7]_inst/O net (fo=0) 0.000 3.155 dpy1[7] G17 r dpy1[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.860ns (logic 1.402ns (36.317%) route 2.458ns (63.683%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.582 -0.681 u_confreg/u_digitaltube_controller/sys_clk SLICE_X63Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y141 FDCE (Prop_fdce_C_Q) 0.141 -0.540 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q net (fo=1, routed) 2.458 1.918 dpy0_OBUF[0] B19 OBUF (Prop_obuf_I_O) 1.261 3.179 r dpy0_OBUF[0]_inst/O net (fo=0) 0.000 3.179 dpy0[0] B19 r dpy0[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[4] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.015ns (logic 1.404ns (34.969%) route 2.611ns (65.031%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.164 -0.518 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q net (fo=1, routed) 2.611 2.093 dpy0_OBUF[4] E18 OBUF (Prop_obuf_I_O) 1.240 3.333 r dpy0_OBUF[4]_inst/O net (fo=0) 0.000 3.333 dpy0[4] E18 r dpy0[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[7] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.060ns (logic 1.409ns (34.714%) route 2.651ns (65.286%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.164 -0.518 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q net (fo=1, routed) 2.651 2.133 dpy0_OBUF[7] C17 OBUF (Prop_obuf_I_O) 1.245 3.378 r dpy0_OBUF[7]_inst/O net (fo=0) 0.000 3.378 dpy0[7] C17 r dpy0[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[10]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_hsync (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.023ns (logic 1.455ns (36.157%) route 2.569ns (63.843%)) Logic Levels: 2 (LUT5=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.650 -0.612 u_axi_dvi/sys_clk SLICE_X46Y86 FDRE r u_axi_dvi/hdata_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y86 FDRE (Prop_fdre_C_Q) 0.164 -0.448 f u_axi_dvi/hdata_reg[10]/Q net (fo=12, routed) 0.384 -0.065 u_axi_dvi/hdata_reg_n_0_[10] SLICE_X41Y86 LUT5 (Prop_lut5_I0_O) 0.045 -0.020 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O net (fo=1, routed) 2.185 2.165 video_hsync_OBUF J24 OBUF (Prop_obuf_I_O) 1.246 3.411 r video_hsync_OBUF_inst/O net (fo=0) 0.000 3.411 video_hsync J24 r video_hsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[6] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.163ns (logic 1.421ns (34.137%) route 2.742ns (65.863%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.164 -0.518 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q net (fo=1, routed) 2.742 2.224 dpy0_OBUF[6] B17 OBUF (Prop_obuf_I_O) 1.257 3.481 r dpy0_OBUF[6]_inst/O net (fo=0) 0.000 3.481 dpy0[6] B17 r dpy0[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[10]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_vsync (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.146ns (logic 1.482ns (35.753%) route 2.664ns (64.247%)) Logic Levels: 3 (LUT4=2 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.649 -0.613 u_axi_dvi/sys_clk SLICE_X47Y83 FDRE r u_axi_dvi/vdata_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y83 FDRE (Prop_fdre_C_Q) 0.141 -0.472 f u_axi_dvi/vdata_reg[10]/Q net (fo=11, routed) 0.120 -0.353 u_axi_dvi/vdata_reg_n_0_[10] SLICE_X49Y82 LUT4 (Prop_lut4_I1_O) 0.045 -0.308 f u_axi_dvi/video_vsync_OBUF_inst_i_4/O net (fo=2, routed) 0.145 -0.163 u_axi_dvi/video_vsync_OBUF_inst_i_4_n_0 SLICE_X49Y81 LUT4 (Prop_lut4_I3_O) 0.045 -0.118 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O net (fo=1, routed) 2.399 2.281 video_vsync_OBUF H24 OBUF (Prop_obuf_I_O) 1.251 3.532 r video_vsync_OBUF_inst/O net (fo=0) 0.000 3.532 video_vsync H24 r video_vsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[11]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_de (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.171ns (logic 1.470ns (35.251%) route 2.701ns (64.749%)) Logic Levels: 2 (LUT6=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.650 -0.612 u_axi_dvi/sys_clk SLICE_X46Y86 FDRE r u_axi_dvi/hdata_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y86 FDRE (Prop_fdre_C_Q) 0.164 -0.448 f u_axi_dvi/hdata_reg[11]/Q net (fo=12, routed) 0.239 -0.210 u_axi_dvi/hdata_reg_n_0_[11] SLICE_X46Y83 LUT6 (Prop_lut6_I3_O) 0.045 -0.165 r u_axi_dvi/video_de_OBUF_inst_i_1/O net (fo=1, routed) 2.462 2.297 video_de_OBUF G24 OBUF (Prop_obuf_I_O) 1.261 3.559 r video_de_OBUF_inst/O net (fo=0) 0.000 3.559 video_de G24 r video_de (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/DVI_SQU_DIR_reg[31]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.241ns (logic 1.808ns (42.631%) route 2.433ns (57.369%)) Logic Levels: 6 (CARRY4=2 LUT2=2 LUT5=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.680 -0.582 u_axi_dvi/sys_clk SLICE_X39Y85 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[31]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.441 r u_axi_dvi/DVI_SQU_DIR_reg[31]/Q net (fo=3, routed) 0.121 -0.320 u_axi_dvi/p_1_in[15] SLICE_X40Y85 LUT2 (Prop_lut2_I0_O) 0.045 -0.275 r u_axi_dvi/video_red_OBUF[2]_inst_i_107/O net (fo=1, routed) 0.000 -0.275 u_axi_dvi/video_red_OBUF[2]_inst_i_107_n_0 SLICE_X40Y85 CARRY4 (Prop_carry4_S[3]_O[3]) 0.064 -0.211 f u_axi_dvi/video_red_OBUF[2]_inst_i_50/O[3] net (fo=1, routed) 0.110 -0.101 hdata1_in_range11_out[15] SLICE_X41Y84 LUT2 (Prop_lut2_I0_O) 0.111 0.010 r video_red_OBUF[2]_inst_i_15/O net (fo=1, routed) 0.000 0.010 u_axi_dvi/video_red_OBUF[2]_inst_i_1_2[1] SLICE_X41Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.115 0.125 r u_axi_dvi/video_red_OBUF[2]_inst_i_3/CO[3] net (fo=1, routed) 0.214 0.338 u_axi_dvi/hdata1_in_range08_in SLICE_X41Y85 LUT5 (Prop_lut5_I1_O) 0.045 0.383 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 1.988 2.372 video_red_OBUF[0] E26 OBUF (Prop_obuf_I_O) 1.287 3.658 r video_red_OBUF[2]_inst/O net (fo=0) 0.000 3.658 video_red[2] E26 r video_red[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/DVI_SQU_DIR_reg[31]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.340ns (logic 1.782ns (41.058%) route 2.558ns (58.942%)) Logic Levels: 6 (CARRY4=2 LUT2=2 LUT5=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.680 -0.582 u_axi_dvi/sys_clk SLICE_X39Y85 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[31]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.441 r u_axi_dvi/DVI_SQU_DIR_reg[31]/Q net (fo=3, routed) 0.121 -0.320 u_axi_dvi/p_1_in[15] SLICE_X40Y85 LUT2 (Prop_lut2_I0_O) 0.045 -0.275 r u_axi_dvi/video_red_OBUF[2]_inst_i_107/O net (fo=1, routed) 0.000 -0.275 u_axi_dvi/video_red_OBUF[2]_inst_i_107_n_0 SLICE_X40Y85 CARRY4 (Prop_carry4_S[3]_O[3]) 0.064 -0.211 f u_axi_dvi/video_red_OBUF[2]_inst_i_50/O[3] net (fo=1, routed) 0.110 -0.101 hdata1_in_range11_out[15] SLICE_X41Y84 LUT2 (Prop_lut2_I0_O) 0.111 0.010 r video_red_OBUF[2]_inst_i_15/O net (fo=1, routed) 0.000 0.010 u_axi_dvi/video_red_OBUF[2]_inst_i_1_2[1] SLICE_X41Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.115 0.125 r u_axi_dvi/video_red_OBUF[2]_inst_i_3/CO[3] net (fo=1, routed) 0.214 0.338 u_axi_dvi/hdata1_in_range08_in SLICE_X41Y85 LUT5 (Prop_lut5_I1_O) 0.045 0.383 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 2.113 2.497 video_red_OBUF[0] F24 OBUF (Prop_obuf_I_O) 1.261 3.757 r video_red_OBUF[1]_inst/O net (fo=0) 0.000 3.757 video_red[1] F24 r video_red[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/DVI_SQU_DIR_reg[31]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.372ns (logic 1.754ns (40.132%) route 2.617ns (59.868%)) Logic Levels: 6 (CARRY4=2 LUT2=2 LUT5=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.680 -0.582 u_axi_dvi/sys_clk SLICE_X39Y85 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[31]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.441 r u_axi_dvi/DVI_SQU_DIR_reg[31]/Q net (fo=3, routed) 0.121 -0.320 u_axi_dvi/p_1_in[15] SLICE_X40Y85 LUT2 (Prop_lut2_I0_O) 0.045 -0.275 r u_axi_dvi/video_red_OBUF[2]_inst_i_107/O net (fo=1, routed) 0.000 -0.275 u_axi_dvi/video_red_OBUF[2]_inst_i_107_n_0 SLICE_X40Y85 CARRY4 (Prop_carry4_S[3]_O[3]) 0.064 -0.211 f u_axi_dvi/video_red_OBUF[2]_inst_i_50/O[3] net (fo=1, routed) 0.110 -0.101 hdata1_in_range11_out[15] SLICE_X41Y84 LUT2 (Prop_lut2_I0_O) 0.111 0.010 r video_red_OBUF[2]_inst_i_15/O net (fo=1, routed) 0.000 0.010 u_axi_dvi/video_red_OBUF[2]_inst_i_1_2[1] SLICE_X41Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.115 0.125 r u_axi_dvi/video_red_OBUF[2]_inst_i_3/CO[3] net (fo=1, routed) 0.214 0.338 u_axi_dvi/hdata1_in_range08_in SLICE_X41Y85 LUT5 (Prop_lut5_I1_O) 0.045 0.383 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 2.172 2.556 video_red_OBUF[0] K23 OBUF (Prop_obuf_I_O) 1.233 3.789 r video_red_OBUF[0]_inst/O net (fo=0) 0.000 3.789 video_red[0] K23 r video_red[0] (OUT) ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: To Clock: sys_clk Max Delay 0 Endpoints Min Delay 43 Endpoints -------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf <<<<<<< Updated upstream Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.872ns (logic 0.287ns (15.346%) route 1.585ns (84.654%)) Logic Levels: 2 (IBUF=1 LUT4=1) Clock Path Skew: -0.231ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.231ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 1.585 1.827 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_TX_IBUF SLICE_X0Y42 LUT4 (Prop_lut4_I2_O) 0.045 1.872 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O net (fo=1, routed) 0.000 1.872 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i SLICE_X0Y42 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.077 -0.231 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk SLICE_X0Y42 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.957ns (logic 0.287ns (14.676%) route 1.670ns (85.324%)) Logic Levels: 2 (IBUF=1 LUT5=1) Clock Path Skew: -0.232ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.232ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 1.670 1.912 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X1Y38 LUT5 (Prop_lut5_I0_O) 0.045 1.957 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O net (fo=1, routed) 0.000 1.957 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 SLICE_X1Y38 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.076 -0.232 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X1Y38 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.987ns (logic 0.287ns (14.457%) route 1.700ns (85.543%)) Logic Levels: 2 (IBUF=1 LUT5=1) Clock Path Skew: -0.232ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.232ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 1.700 1.942 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF SLICE_X1Y39 LUT5 (Prop_lut5_I2_O) 0.045 1.987 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O net (fo=1, routed) 0.000 1.987 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.076 -0.232 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.184ns (logic 0.395ns (18.098%) route 1.789ns (81.902%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1) Clock Path Skew: -0.232ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.232ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 1.670 1.912 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X1Y38 LUT2 (Prop_lut2_I1_O) 0.046 1.958 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O net (fo=2, routed) 0.119 2.077 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 SLICE_X1Y39 LUT6 (Prop_lut6_I2_O) 0.107 2.184 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O net (fo=1, routed) 0.000 2.184 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.076 -0.232 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.412ns (logic 0.394ns (16.343%) route 2.018ns (83.657%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) Clock Path Skew: -0.232ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.232ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 1.670 1.912 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X1Y38 LUT2 (Prop_lut2_I1_O) 0.046 1.958 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O net (fo=2, routed) 0.348 2.306 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 SLICE_X1Y39 LUT5 (Prop_lut5_I1_O) 0.106 2.412 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O net (fo=1, routed) 0.000 2.412 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.076 -0.232 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C Slack: inf Source: dip_sw[29] (input port) Destination: u_confreg/s_rdata_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.665ns (logic 0.336ns (12.609%) route 2.329ns (87.391%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.309ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T5 0.000 0.000 r dip_sw[29] (IN) net (fo=0) 0.000 0.000 dip_sw[29] T5 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[29]_inst/O net (fo=1, routed) 2.278 2.524 u_confreg/dip_sw_IBUF[29] SLICE_X5Y59 LUT5 (Prop_lut5_I4_O) 0.045 2.569 r u_confreg/s_rdata[29]_i_4/O net (fo=1, routed) 0.050 2.620 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 SLICE_X5Y59 LUT6 (Prop_lut6_I4_O) 0.045 2.665 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O net (fo=1, routed) 0.000 2.665 u_confreg/u_int_ctrl_n_2 SLICE_X5Y59 FDRE r u_confreg/s_rdata_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.999 -0.309 u_confreg/sys_clk SLICE_X5Y59 FDRE r u_confreg/s_rdata_reg[29]/C Slack: inf Source: dip_sw[16] (input port) Destination: u_confreg/s_rdata_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.200ns (logic 0.358ns (11.179%) route 2.842ns (88.821%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.306ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K2 0.000 0.000 r dip_sw[16] (IN) net (fo=0) 0.000 0.000 dip_sw[16] K2 IBUF (Prop_ibuf_I_O) 0.268 0.268 r dip_sw_IBUF[16]_inst/O net (fo=1, routed) 2.701 2.969 u_confreg/dip_sw_IBUF[16] SLICE_X1Y56 LUT5 (Prop_lut5_I4_O) 0.045 3.014 r u_confreg/s_rdata[16]_i_4/O net (fo=1, routed) 0.142 3.155 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 SLICE_X1Y54 LUT6 (Prop_lut6_I4_O) 0.045 3.200 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O net (fo=1, routed) 0.000 3.200 u_confreg/u_int_ctrl_n_15 SLICE_X1Y54 FDRE r u_confreg/s_rdata_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk SLICE_X1Y54 FDRE r u_confreg/s_rdata_reg[16]/C Slack: inf Source: dip_sw[11] (input port) Destination: u_confreg/s_rdata_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.265ns (logic 0.329ns (10.081%) route 2.936ns (89.919%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.335ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L7 0.000 0.000 r dip_sw[11] (IN) net (fo=0) 0.000 0.000 dip_sw[11] L7 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[11]_inst/O net (fo=1, routed) 2.885 3.124 u_confreg/dip_sw_IBUF[11] SLICE_X9Y51 LUT5 (Prop_lut5_I4_O) 0.045 3.169 r u_confreg/s_rdata[11]_i_4/O net (fo=1, routed) 0.051 3.220 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 SLICE_X9Y51 LUT6 (Prop_lut6_I4_O) 0.045 3.265 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O net (fo=1, routed) 0.000 3.265 u_confreg/u_int_ctrl_n_20 SLICE_X9Y51 FDRE r u_confreg/s_rdata_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.973 -0.335 u_confreg/sys_clk SLICE_X9Y51 FDRE r u_confreg/s_rdata_reg[11]/C Slack: inf Source: dip_sw[13] (input port) Destination: u_confreg/s_rdata_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.266ns (logic 0.344ns (10.521%) route 2.922ns (89.479%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.335ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K3 0.000 0.000 r dip_sw[13] (IN) net (fo=0) 0.000 0.000 dip_sw[13] K3 IBUF (Prop_ibuf_I_O) 0.254 0.254 r dip_sw_IBUF[13]_inst/O net (fo=1, routed) 2.784 3.038 u_confreg/dip_sw_IBUF[13] SLICE_X10Y52 LUT5 (Prop_lut5_I4_O) 0.045 3.083 r u_confreg/s_rdata[13]_i_4/O net (fo=1, routed) 0.138 3.221 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 SLICE_X11Y52 LUT6 (Prop_lut6_I4_O) 0.045 3.266 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O net (fo=1, routed) 0.000 3.266 u_confreg/u_int_ctrl_n_18 SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.973 -0.335 u_confreg/sys_clk SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[13]/C Slack: inf Source: dip_sw[0] (input port) Destination: u_confreg/s_rdata_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.268ns (logic 0.353ns (10.796%) route 2.915ns (89.204%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.336ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T3 0.000 0.000 r dip_sw[0] (IN) net (fo=0) 0.000 0.000 dip_sw[0] T3 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[0]_inst/O net (fo=1, routed) 2.694 2.957 u_confreg/dip_sw_IBUF[0] SLICE_X8Y54 LUT5 (Prop_lut5_I4_O) 0.045 3.002 r u_confreg/s_rdata[0]_i_4/O net (fo=1, routed) 0.220 3.223 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 SLICE_X8Y54 LUT6 (Prop_lut6_I4_O) 0.045 3.268 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O net (fo=1, routed) 0.000 3.268 u_confreg/u_int_ctrl_n_31 SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.972 -0.336 u_confreg/sys_clk SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[0]/C Slack: inf Source: dip_sw[6] (input port) Destination: u_confreg/s_rdata_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.390ns (logic 0.346ns (10.197%) route 3.045ns (89.803%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.336ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L3 0.000 0.000 r dip_sw[6] (IN) net (fo=0) 0.000 0.000 dip_sw[6] L3 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[6]_inst/O net (fo=1, routed) 2.741 2.996 u_confreg/dip_sw_IBUF[6] SLICE_X8Y59 LUT5 (Prop_lut5_I4_O) 0.045 3.041 r u_confreg/s_rdata[6]_i_4/O net (fo=1, routed) 0.304 3.345 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 SLICE_X8Y54 LUT6 (Prop_lut6_I4_O) 0.045 3.390 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O net (fo=1, routed) 0.000 3.390 u_confreg/u_int_ctrl_n_25 SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.972 -0.336 u_confreg/sys_clk SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[6]/C Slack: inf Source: dip_sw[19] (input port) Destination: u_confreg/s_rdata_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.414ns (logic 0.336ns (9.845%) route 3.078ns (90.155%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.338ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L4 0.000 0.000 r dip_sw[19] (IN) net (fo=0) 0.000 0.000 dip_sw[19] L4 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[19]_inst/O net (fo=1, routed) 3.026 3.272 u_confreg/dip_sw_IBUF[19] SLICE_X15Y58 LUT5 (Prop_lut5_I4_O) 0.045 3.317 r u_confreg/s_rdata[19]_i_4/O net (fo=1, routed) 0.051 3.369 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 SLICE_X15Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.414 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O net (fo=1, routed) 0.000 3.414 u_confreg/u_int_ctrl_n_12 SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.970 -0.338 u_confreg/sys_clk SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[19]/C Slack: inf Source: dip_sw[14] (input port) Destination: u_confreg/s_rdata_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.434ns (logic 0.373ns (10.848%) route 3.061ns (89.152%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.306ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J1 0.000 0.000 r dip_sw[14] (IN) net (fo=0) 0.000 0.000 dip_sw[14] J1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r dip_sw_IBUF[14]_inst/O net (fo=1, routed) 3.010 3.293 u_confreg/dip_sw_IBUF[14] SLICE_X1Y53 LUT5 (Prop_lut5_I4_O) 0.045 3.338 r u_confreg/s_rdata[14]_i_4/O net (fo=1, routed) 0.051 3.389 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 SLICE_X1Y53 LUT6 (Prop_lut6_I4_O) 0.045 3.434 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O net (fo=1, routed) 0.000 3.434 u_confreg/u_int_ctrl_n_17 SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[14]/C Slack: inf Source: dip_sw[10] (input port) Destination: u_confreg/s_rdata_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.439ns (logic 0.330ns (9.600%) route 3.109ns (90.400%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.260ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.260ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M7 0.000 0.000 r dip_sw[10] (IN) net (fo=0) 0.000 0.000 dip_sw[10] M7 IBUF (Prop_ibuf_I_O) 0.240 0.240 r dip_sw_IBUF[10]_inst/O net (fo=1, routed) 3.053 3.293 u_confreg/dip_sw_IBUF[10] SLICE_X10Y49 LUT5 (Prop_lut5_I4_O) 0.045 3.338 r u_confreg/s_rdata[10]_i_4/O net (fo=1, routed) 0.056 3.394 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 SLICE_X10Y49 LUT6 (Prop_lut6_I4_O) 0.045 3.439 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O net (fo=1, routed) 0.000 3.439 u_confreg/u_int_ctrl_n_21 SLICE_X10Y49 FDRE r u_confreg/s_rdata_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.048 -0.260 u_confreg/sys_clk SLICE_X10Y49 FDRE r u_confreg/s_rdata_reg[10]/C Slack: inf Source: dip_sw[8] (input port) Destination: u_confreg/s_rdata_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.468ns (logic 0.334ns (9.621%) route 3.134ns (90.379%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.335ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M6 0.000 0.000 r dip_sw[8] (IN) net (fo=0) 0.000 0.000 dip_sw[8] M6 IBUF (Prop_ibuf_I_O) 0.244 0.244 r dip_sw_IBUF[8]_inst/O net (fo=1, routed) 2.855 3.099 u_confreg/dip_sw_IBUF[8] SLICE_X11Y54 LUT5 (Prop_lut5_I4_O) 0.045 3.144 r u_confreg/s_rdata[8]_i_4/O net (fo=1, routed) 0.279 3.423 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 SLICE_X11Y52 LUT6 (Prop_lut6_I4_O) 0.045 3.468 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O net (fo=1, routed) 0.000 3.468 u_confreg/u_int_ctrl_n_23 SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.973 -0.335 u_confreg/sys_clk SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[8]/C Slack: inf Source: dip_sw[5] (input port) Destination: u_confreg/s_rdata_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.503ns (logic 0.328ns (9.375%) route 3.174ns (90.625%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.305ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.305ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L5 0.000 0.000 r dip_sw[5] (IN) net (fo=0) 0.000 0.000 dip_sw[5] L5 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[5]_inst/O net (fo=1, routed) 3.123 3.361 u_confreg/dip_sw_IBUF[5] SLICE_X3Y52 LUT5 (Prop_lut5_I4_O) 0.045 3.406 r u_confreg/s_rdata[5]_i_4/O net (fo=1, routed) 0.051 3.458 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 SLICE_X3Y52 LUT6 (Prop_lut6_I4_O) 0.045 3.503 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O net (fo=1, routed) 0.000 3.503 u_confreg/u_int_ctrl_n_26 SLICE_X3Y52 FDRE r u_confreg/s_rdata_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.003 -0.305 u_confreg/sys_clk SLICE_X3Y52 FDRE r u_confreg/s_rdata_reg[5]/C Slack: inf Source: dip_sw[15] (input port) Destination: u_confreg/s_rdata_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.507ns (logic 0.352ns (10.034%) route 3.155ns (89.966%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.306ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L2 0.000 0.000 r dip_sw[15] (IN) net (fo=0) 0.000 0.000 dip_sw[15] L2 IBUF (Prop_ibuf_I_O) 0.262 0.262 r dip_sw_IBUF[15]_inst/O net (fo=1, routed) 2.926 3.188 u_confreg/dip_sw_IBUF[15] SLICE_X2Y53 LUT5 (Prop_lut5_I4_O) 0.045 3.233 r u_confreg/s_rdata[15]_i_4/O net (fo=1, routed) 0.229 3.462 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 SLICE_X2Y53 LUT6 (Prop_lut6_I4_O) 0.045 3.507 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O net (fo=1, routed) 0.000 3.507 u_confreg/u_int_ctrl_n_16 SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[15]/C Slack: inf Source: touch_btn[2] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.530ns (logic 0.255ns (7.212%) route 3.276ns (92.788%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -0.340ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.340ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P3 0.000 0.000 r touch_btn[2] (IN) net (fo=0) 0.000 0.000 touch_btn[2] P3 IBUF (Prop_ibuf_I_O) 0.255 0.255 r touch_btn_IBUF[2]_inst/O net (fo=1, routed) 3.276 3.530 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] SLICE_X9Y62 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.968 -0.340 u_confreg/u_int_ctrl/sys_clk SLICE_X9Y62 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C Slack: inf Source: dip_sw[9] (input port) Destination: u_confreg/s_rdata_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.537ns (logic 0.328ns (9.266%) route 3.209ns (90.734%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.337ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N7 0.000 0.000 r dip_sw[9] (IN) net (fo=0) 0.000 0.000 dip_sw[9] N7 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[9]_inst/O net (fo=1, routed) 3.010 3.247 u_confreg/dip_sw_IBUF[9] SLICE_X13Y57 LUT5 (Prop_lut5_I4_O) 0.045 3.292 r u_confreg/s_rdata[9]_i_4/O net (fo=1, routed) 0.199 3.492 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 SLICE_X13Y55 LUT6 (Prop_lut6_I4_O) 0.045 3.537 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O net (fo=1, routed) 0.000 3.537 u_confreg/u_int_ctrl_n_22 SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[9]/C Slack: inf Source: dip_sw[23] (input port) Destination: u_confreg/s_rdata_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.560ns (logic 0.376ns (10.559%) route 3.184ns (89.441%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.337ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N1 0.000 0.000 r dip_sw[23] (IN) net (fo=0) 0.000 0.000 dip_sw[23] N1 IBUF (Prop_ibuf_I_O) 0.286 0.286 r dip_sw_IBUF[23]_inst/O net (fo=1, routed) 2.820 3.106 u_confreg/dip_sw_IBUF[23] SLICE_X15Y60 LUT5 (Prop_lut5_I4_O) 0.045 3.151 r u_confreg/s_rdata[23]_i_4/O net (fo=1, routed) 0.365 3.515 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.045 3.560 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O net (fo=1, routed) 0.000 3.560 u_confreg/u_int_ctrl_n_8 SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[23]/C Slack: inf Source: dip_sw[2] (input port) Destination: u_confreg/s_rdata_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.591ns (logic 0.353ns (9.826%) route 3.238ns (90.174%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.306ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M2 0.000 0.000 r dip_sw[2] (IN) net (fo=0) 0.000 0.000 dip_sw[2] M2 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[2]_inst/O net (fo=1, routed) 2.898 3.161 u_confreg/dip_sw_IBUF[2] SLICE_X2Y56 LUT5 (Prop_lut5_I4_O) 0.045 3.206 r u_confreg/s_rdata[2]_i_4/O net (fo=1, routed) 0.340 3.546 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 SLICE_X2Y53 LUT6 (Prop_lut6_I4_O) 0.045 3.591 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O net (fo=1, routed) 0.000 3.591 u_confreg/u_int_ctrl_n_29 SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[2]/C Slack: inf Source: dip_sw[17] (input port) Destination: u_confreg/s_rdata_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.592ns (logic 0.362ns (10.072%) route 3.230ns (89.928%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.307ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.307ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K1 0.000 0.000 r dip_sw[17] (IN) net (fo=0) 0.000 0.000 dip_sw[17] K1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[17]_inst/O net (fo=1, routed) 3.009 3.281 u_confreg/dip_sw_IBUF[17] SLICE_X3Y58 LUT5 (Prop_lut5_I4_O) 0.045 3.326 r u_confreg/s_rdata[17]_i_4/O net (fo=1, routed) 0.221 3.547 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 SLICE_X3Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.592 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O net (fo=1, routed) 0.000 3.592 u_confreg/u_int_ctrl_n_14 SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[17]/C Slack: inf Source: dip_sw[24] (input port) Destination: u_confreg/s_rdata_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.594ns (logic 0.324ns (9.027%) route 3.270ns (90.973%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.338ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P5 0.000 0.000 r dip_sw[24] (IN) net (fo=0) 0.000 0.000 dip_sw[24] P5 IBUF (Prop_ibuf_I_O) 0.234 0.234 r dip_sw_IBUF[24]_inst/O net (fo=1, routed) 3.131 3.365 u_confreg/dip_sw_IBUF[24] SLICE_X15Y58 LUT5 (Prop_lut5_I4_O) 0.045 3.410 r u_confreg/s_rdata[24]_i_4/O net (fo=1, routed) 0.139 3.549 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 SLICE_X15Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.594 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O net (fo=1, routed) 0.000 3.594 u_confreg/u_int_ctrl_n_7 SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.970 -0.338 u_confreg/sys_clk SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[24]/C Slack: inf Source: dip_sw[12] (input port) Destination: u_confreg/s_rdata_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.598ns (logic 0.327ns (9.090%) route 3.271ns (90.910%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.337ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M5 0.000 0.000 r dip_sw[12] (IN) net (fo=0) 0.000 0.000 dip_sw[12] M5 IBUF (Prop_ibuf_I_O) 0.237 0.237 r dip_sw_IBUF[12]_inst/O net (fo=1, routed) 3.009 3.246 u_confreg/dip_sw_IBUF[12] SLICE_X14Y57 LUT5 (Prop_lut5_I4_O) 0.045 3.291 r u_confreg/s_rdata[12]_i_4/O net (fo=1, routed) 0.262 3.553 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 SLICE_X13Y56 LUT6 (Prop_lut6_I4_O) 0.045 3.598 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O net (fo=1, routed) 0.000 3.598 u_confreg/u_int_ctrl_n_19 SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[12]/C Slack: inf Source: dip_sw[1] (input port) Destination: u_confreg/s_rdata_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.716ns (logic 0.355ns (9.565%) route 3.361ns (90.435%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.307ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.307ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J3 0.000 0.000 r dip_sw[1] (IN) net (fo=0) 0.000 0.000 dip_sw[1] J3 IBUF (Prop_ibuf_I_O) 0.265 0.265 r dip_sw_IBUF[1]_inst/O net (fo=1, routed) 3.093 3.358 u_confreg/dip_sw_IBUF[1] SLICE_X5Y51 LUT5 (Prop_lut5_I4_O) 0.045 3.403 r u_confreg/s_rdata[1]_i_4/O net (fo=1, routed) 0.268 3.671 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 SLICE_X5Y50 LUT6 (Prop_lut6_I4_O) 0.045 3.716 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O net (fo=1, routed) 0.000 3.716 u_confreg/u_int_ctrl_n_30 SLICE_X5Y50 FDRE r u_confreg/s_rdata_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk SLICE_X5Y50 FDRE r u_confreg/s_rdata_reg[1]/C Slack: inf Source: dip_sw[20] (input port) Destination: u_confreg/s_rdata_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.770ns (logic 0.333ns (8.832%) route 3.437ns (91.168%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.307ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.307ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M4 0.000 0.000 r dip_sw[20] (IN) net (fo=0) 0.000 0.000 dip_sw[20] M4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r dip_sw_IBUF[20]_inst/O net (fo=1, routed) 3.269 3.512 u_confreg/dip_sw_IBUF[20] SLICE_X1Y61 LUT5 (Prop_lut5_I4_O) 0.045 3.557 r u_confreg/s_rdata[20]_i_4/O net (fo=1, routed) 0.168 3.725 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 SLICE_X1Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.770 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O net (fo=1, routed) 0.000 3.770 u_confreg/u_int_ctrl_n_11 SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[20]/C Slack: inf Source: dip_sw[26] (input port) Destination: u_confreg/s_rdata_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.868ns (logic 0.367ns (9.485%) route 3.501ns (90.515%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.307ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.307ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T4 0.000 0.000 r dip_sw[26] (IN) net (fo=0) 0.000 0.000 dip_sw[26] T4 IBUF (Prop_ibuf_I_O) 0.277 0.277 r dip_sw_IBUF[26]_inst/O net (fo=1, routed) 3.288 3.565 u_confreg/dip_sw_IBUF[26] SLICE_X1Y58 LUT5 (Prop_lut5_I4_O) 0.045 3.610 r u_confreg/s_rdata[26]_i_4/O net (fo=1, routed) 0.213 3.823 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 SLICE_X1Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.868 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O net (fo=1, routed) 0.000 3.868 u_confreg/u_int_ctrl_n_5 SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[26]/C Slack: inf Source: dip_sw[3] (input port) Destination: u_confreg/s_rdata_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.879ns (logic 0.362ns (9.330%) route 3.517ns (90.670%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.307ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.307ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P1 0.000 0.000 r dip_sw[3] (IN) net (fo=0) 0.000 0.000 dip_sw[3] P1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[3]_inst/O net (fo=1, routed) 3.459 3.731 u_confreg/dip_sw_IBUF[3] SLICE_X4Y51 LUT5 (Prop_lut5_I4_O) 0.045 3.776 r u_confreg/s_rdata[3]_i_4/O net (fo=1, routed) 0.059 3.834 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 SLICE_X4Y51 LUT6 (Prop_lut6_I4_O) 0.045 3.879 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O net (fo=1, routed) 0.000 3.879 u_confreg/u_int_ctrl_n_28 SLICE_X4Y51 FDRE r u_confreg/s_rdata_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk SLICE_X4Y51 FDRE r u_confreg/s_rdata_reg[3]/C Slack: inf Source: touch_btn[1] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.995ns (logic 0.283ns (7.072%) route 3.713ns (92.928%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M1 0.000 0.000 r touch_btn[1] (IN) net (fo=0) 0.000 0.000 touch_btn[1] M1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r touch_btn_IBUF[1]_inst/O net (fo=1, routed) 3.713 3.995 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] SLICE_X15Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.969 -0.339 u_confreg/u_int_ctrl/sys_clk SLICE_X15Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C Slack: inf Source: touch_btn[3] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 4.065ns (logic 0.280ns (6.894%) route 3.785ns (93.106%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -0.338ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- U2 0.000 0.000 r touch_btn[3] (IN) net (fo=0) 0.000 0.000 touch_btn[3] U2 IBUF (Prop_ibuf_I_O) 0.280 0.280 r touch_btn_IBUF[3]_inst/O net (fo=1, routed) 3.785 4.065 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] SLICE_X10Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.970 -0.338 u_confreg/u_int_ctrl/sys_clk SLICE_X10Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C Slack: inf Source: touch_btn[0] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 4.085ns (logic 0.267ns (6.527%) route 3.818ns (93.473%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -0.337ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T2 0.000 0.000 r touch_btn[0] (IN) net (fo=0) 0.000 0.000 touch_btn[0] T2 IBUF (Prop_ibuf_I_O) 0.267 0.267 r touch_btn_IBUF[0]_inst/O net (fo=1, routed) 3.818 4.085 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] SLICE_X8Y57 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_confreg/u_int_ctrl/sys_clk SLICE_X8Y57 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C Slack: inf ======= >>>>>>> Stashed changes Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED (internal pin) Destination: pll_clk.u_rst_sys/delay_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Removal (Min at Fast Process Corner) <<<<<<< Updated upstream Data Path Delay: 4.205ns (logic 0.045ns (1.070%) route 4.160ns (98.930%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns ======= Data Path Delay: 1.811ns (logic 0.045ns (2.485%) route 1.766ns (97.515%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED <<<<<<< Updated upstream net (fo=1, routed) 3.932 3.932 pll_clk.u_rst_sys/locked SLICE_X106Y69 LUT1 (Prop_lut1_I0_O) 0.045 3.977 f pll_clk.u_rst_sys/delay[1]_i_1/O net (fo=2, routed) 0.228 4.205 pll_clk.u_rst_sys/delay[1]_i_1_n_0 SLICE_X106Y69 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR ======= net (fo=1, routed) 1.592 1.592 pll_clk.u_rst_sys/locked SLICE_X22Y139 LUT1 (Prop_lut1_I0_O) 0.045 1.637 f pll_clk.u_rst_sys/delay[1]_i_1/O net (fo=2, routed) 0.174 1.811 pll_clk.u_rst_sys/delay[1]_i_1_n_0 SLICE_X22Y139 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.922 -0.386 pll_clk.u_rst_sys/sys_clk SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C ======= net (fo=9971, routed) 0.896 -0.412 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C >>>>>>> Stashed changes Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED (internal pin) Destination: pll_clk.u_rst_sys/delay_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Removal (Min at Fast Process Corner) <<<<<<< Updated upstream Data Path Delay: 4.205ns (logic 0.045ns (1.070%) route 4.160ns (98.930%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns ======= Data Path Delay: 1.811ns (logic 0.045ns (2.485%) route 1.766ns (97.515%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns >>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED <<<<<<< Updated upstream net (fo=1, routed) 3.932 3.932 pll_clk.u_rst_sys/locked SLICE_X106Y69 LUT1 (Prop_lut1_I0_O) 0.045 3.977 f pll_clk.u_rst_sys/delay[1]_i_1/O net (fo=2, routed) 0.228 4.205 pll_clk.u_rst_sys/delay[1]_i_1_n_0 SLICE_X106Y69 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR ======= net (fo=1, routed) 1.592 1.592 pll_clk.u_rst_sys/locked SLICE_X22Y139 LUT1 (Prop_lut1_I0_O) 0.045 1.637 f pll_clk.u_rst_sys/delay[1]_i_1/O net (fo=2, routed) 0.174 1.811 pll_clk.u_rst_sys/delay[1]_i_1_n_0 SLICE_X22Y139 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.922 -0.386 pll_clk.u_rst_sys/sys_clk SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C Slack: inf Source: dip_sw[21] (input port) Destination: u_confreg/s_rdata_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 4.217ns (logic 0.346ns (8.203%) route 3.871ns (91.797%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.337ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N2 0.000 0.000 r dip_sw[21] (IN) net (fo=0) 0.000 0.000 dip_sw[21] N2 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[21]_inst/O net (fo=1, routed) 3.762 4.018 u_confreg/dip_sw_IBUF[21] SLICE_X12Y56 LUT5 (Prop_lut5_I4_O) 0.045 4.063 r u_confreg/s_rdata[21]_i_4/O net (fo=1, routed) 0.110 4.172 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 SLICE_X13Y56 LUT6 (Prop_lut6_I4_O) 0.045 4.217 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O net (fo=1, routed) 0.000 4.217 u_confreg/u_int_ctrl_n_10 SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[21]/C ======= net (fo=9971, routed) 0.896 -0.412 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C >>>>>>> Stashed changes Slack: inf Source: dip_sw[31] (input port) Destination: u_confreg/s_rdata_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) <<<<<<< Updated upstream Data Path Delay: 4.251ns (logic 0.351ns (8.267%) route 3.899ns (91.733%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.337ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns ======= Data Path Delay: 2.161ns (logic 0.351ns (16.258%) route 1.810ns (83.742%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.454ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.454ns >>>>>>> Stashed changes Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R2 0.000 0.000 r dip_sw[31] (IN) net (fo=0) 0.000 0.000 dip_sw[31] R2 IBUF (Prop_ibuf_I_O) 0.261 0.261 r dip_sw_IBUF[31]_inst/O <<<<<<< Updated upstream net (fo=1, routed) 3.787 4.048 u_confreg/dip_sw_IBUF[31] SLICE_X9Y61 LUT5 (Prop_lut5_I4_O) 0.045 4.093 r u_confreg/s_rdata[31]_i_6/O net (fo=1, routed) 0.112 4.206 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.045 4.251 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O net (fo=1, routed) 0.000 4.251 u_confreg/u_int_ctrl_n_0 SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[31]/D ======= net (fo=1, routed) 1.699 1.960 u_confreg/dip_sw_IBUF[31] SLICE_X59Y137 LUT5 (Prop_lut5_I4_O) 0.045 2.005 r u_confreg/s_rdata[31]_i_6/O net (fo=1, routed) 0.111 2.116 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 SLICE_X57Y137 LUT6 (Prop_lut6_I4_O) 0.045 2.161 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O net (fo=1, routed) 0.000 2.161 u_confreg/u_int_ctrl_n_0 SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[31]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[31]/C Slack: inf Source: dip_sw[18] (input port) Destination: u_confreg/s_rdata_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 4.259ns (logic 0.347ns (8.145%) route 3.912ns (91.855%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.337ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns ======= net (fo=9971, routed) 0.854 -0.454 u_confreg/sys_clk SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[31]/C Slack: inf Source: dip_sw[23] (input port) Destination: u_confreg/s_rdata_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.220ns (logic 0.376ns (16.930%) route 1.845ns (83.070%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.452ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns >>>>>>> Stashed changes Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream N3 0.000 0.000 r dip_sw[18] (IN) net (fo=0) 0.000 0.000 dip_sw[18] N3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[18]_inst/O net (fo=1, routed) 3.633 3.889 u_confreg/dip_sw_IBUF[18] SLICE_X13Y57 LUT5 (Prop_lut5_I4_O) 0.045 3.934 r u_confreg/s_rdata[18]_i_4/O net (fo=1, routed) 0.279 4.214 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 SLICE_X13Y55 LUT6 (Prop_lut6_I4_O) 0.045 4.259 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O net (fo=1, routed) 0.000 4.259 u_confreg/u_int_ctrl_n_13 SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[18]/D ======= N1 0.000 0.000 r dip_sw[23] (IN) net (fo=0) 0.000 0.000 dip_sw[23] N1 IBUF (Prop_ibuf_I_O) 0.286 0.286 r dip_sw_IBUF[23]_inst/O net (fo=1, routed) 1.603 1.889 u_confreg/dip_sw_IBUF[23] SLICE_X51Y139 LUT5 (Prop_lut5_I4_O) 0.045 1.934 r u_confreg/s_rdata[23]_i_4/O net (fo=1, routed) 0.241 2.175 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 SLICE_X50Y139 LUT6 (Prop_lut6_I4_O) 0.045 2.220 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O net (fo=1, routed) 0.000 2.220 u_confreg/u_int_ctrl_n_8 SLICE_X50Y139 FDRE r u_confreg/s_rdata_reg[23]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[18]/C Slack: inf Source: dip_sw[30] (input port) Destination: u_confreg/s_rdata_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 4.355ns (logic 0.317ns (7.282%) route 4.038ns (92.718%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.337ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R6 0.000 0.000 r dip_sw[30] (IN) net (fo=0) 0.000 0.000 dip_sw[30] R6 IBUF (Prop_ibuf_I_O) 0.227 0.227 r dip_sw_IBUF[30]_inst/O net (fo=1, routed) 3.935 4.162 u_confreg/dip_sw_IBUF[30] SLICE_X9Y60 LUT5 (Prop_lut5_I4_O) 0.045 4.207 r u_confreg/s_rdata[30]_i_4/O net (fo=1, routed) 0.103 4.310 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.045 4.355 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O net (fo=1, routed) 0.000 4.355 u_confreg/u_int_ctrl_n_1 SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[30]/C Slack: inf Source: dip_sw[22] (input port) Destination: u_confreg/s_rdata_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 4.425ns (logic 0.320ns (7.240%) route 4.104ns (92.760%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.337ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P6 0.000 0.000 r dip_sw[22] (IN) net (fo=0) 0.000 0.000 dip_sw[22] P6 IBUF (Prop_ibuf_I_O) 0.230 0.230 r dip_sw_IBUF[22]_inst/O net (fo=1, routed) 3.963 4.193 u_confreg/dip_sw_IBUF[22] SLICE_X9Y61 LUT5 (Prop_lut5_I4_O) 0.045 4.238 r u_confreg/s_rdata[22]_i_4/O net (fo=1, routed) 0.142 4.380 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.045 4.425 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O net (fo=1, routed) 0.000 4.425 u_confreg/u_int_ctrl_n_9 SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[22]/C Slack: inf Source: dip_sw[7] (input port) Destination: u_confreg/s_rdata_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 4.560ns (logic 0.329ns (7.220%) route 4.231ns (92.780%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.306ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N6 0.000 0.000 r dip_sw[7] (IN) net (fo=0) 0.000 0.000 dip_sw[7] N6 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[7]_inst/O net (fo=1, routed) 4.018 4.257 u_confreg/dip_sw_IBUF[7] SLICE_X3Y56 LUT5 (Prop_lut5_I4_O) 0.045 4.302 r u_confreg/s_rdata[7]_i_4/O net (fo=1, routed) 0.213 4.515 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 SLICE_X3Y56 LUT6 (Prop_lut6_I4_O) 0.045 4.560 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O net (fo=1, routed) 0.000 4.560 u_confreg/u_int_ctrl_n_24 SLICE_X3Y56 FDRE r u_confreg/s_rdata_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk SLICE_X3Y56 FDRE r u_confreg/s_rdata_reg[7]/C ======= net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk SLICE_X50Y139 FDRE r u_confreg/s_rdata_reg[23]/C >>>>>>> Stashed changes Slack: inf Source: touch_btn[1] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) <<<<<<< Updated upstream Data Path Delay: 4.587ns (logic 0.346ns (7.542%) route 4.241ns (92.458%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.306ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.306ns ======= Data Path Delay: 2.242ns (logic 0.283ns (12.603%) route 1.959ns (87.397%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -0.465ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.465ns >>>>>>> Stashed changes Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream P4 0.000 0.000 r dip_sw[4] (IN) net (fo=0) 0.000 0.000 dip_sw[4] P4 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[4]_inst/O net (fo=1, routed) 3.727 3.983 u_confreg/dip_sw_IBUF[4] SLICE_X0Y59 LUT5 (Prop_lut5_I4_O) 0.045 4.028 r u_confreg/s_rdata[4]_i_4/O net (fo=1, routed) 0.514 4.542 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 SLICE_X1Y53 LUT6 (Prop_lut6_I4_O) 0.045 4.587 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O net (fo=1, routed) 0.000 4.587 u_confreg/u_int_ctrl_n_27 SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[4]/D ======= M1 0.000 0.000 r touch_btn[1] (IN) net (fo=0) 0.000 0.000 touch_btn[1] M1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r touch_btn_IBUF[1]_inst/O net (fo=1, routed) 1.959 2.242 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[4]/C Slack: inf Source: dip_sw[27] (input port) Destination: u_confreg/s_rdata_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 4.738ns (logic 0.362ns (7.650%) route 4.375ns (92.350%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.309ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns ======= net (fo=9971, routed) 0.843 -0.465 u_confreg/u_int_ctrl/sys_clk SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.295ns (logic 0.287ns (12.514%) route 2.008ns (87.486%)) Logic Levels: 2 (IBUF=1 LUT5=1) Clock Path Skew: -0.466ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.466ns >>>>>>> Stashed changes Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream R1 0.000 0.000 r dip_sw[27] (IN) net (fo=0) 0.000 0.000 dip_sw[27] R1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[27]_inst/O net (fo=1, routed) 4.155 4.428 u_confreg/dip_sw_IBUF[27] SLICE_X5Y58 LUT5 (Prop_lut5_I4_O) 0.045 4.473 r u_confreg/s_rdata[27]_i_4/O net (fo=1, routed) 0.220 4.693 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 SLICE_X5Y58 LUT6 (Prop_lut6_I4_O) 0.045 4.738 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O net (fo=1, routed) 0.000 4.738 u_confreg/u_int_ctrl_n_4 SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[27]/D ======= H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 2.008 2.250 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF SLICE_X77Y137 LUT5 (Prop_lut5_I2_O) 0.045 2.295 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O net (fo=1, routed) 0.000 2.295 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 SLICE_X77Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.999 -0.309 u_confreg/sys_clk SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[27]/C ======= net (fo=9971, routed) 0.842 -0.466 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X77Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C Slack: inf Source: dip_sw[28] (input port) Destination: u_confreg/s_rdata_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.315ns (logic 0.326ns (14.065%) route 1.989ns (85.935%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.452ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R5 0.000 0.000 r dip_sw[28] (IN) net (fo=0) 0.000 0.000 dip_sw[28] R5 IBUF (Prop_ibuf_I_O) 0.236 0.236 r dip_sw_IBUF[28]_inst/O net (fo=1, routed) 1.643 1.878 u_confreg/dip_sw_IBUF[28] SLICE_X59Y139 LUT5 (Prop_lut5_I4_O) 0.045 1.923 r u_confreg/s_rdata[28]_i_4/O net (fo=1, routed) 0.346 2.270 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 SLICE_X52Y139 LUT6 (Prop_lut6_I4_O) 0.045 2.315 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O net (fo=1, routed) 0.000 2.315 u_confreg/u_int_ctrl_n_3 SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[28]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.347ns (logic 0.287ns (12.237%) route 2.060ns (87.763%)) Logic Levels: 2 (IBUF=1 LUT4=1) Clock Path Skew: -0.466ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.466ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 2.060 2.302 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_TX_IBUF SLICE_X77Y137 LUT4 (Prop_lut4_I2_O) 0.045 2.347 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O net (fo=1, routed) 0.000 2.347 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i SLICE_X77Y137 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.842 -0.466 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk SLICE_X77Y137 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C Slack: inf Source: dip_sw[17] (input port) Destination: u_confreg/s_rdata_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.367ns (logic 0.362ns (15.281%) route 2.005ns (84.719%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.455ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.455ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K1 0.000 0.000 r dip_sw[17] (IN) net (fo=0) 0.000 0.000 dip_sw[17] K1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[17]_inst/O net (fo=1, routed) 1.744 2.015 u_confreg/dip_sw_IBUF[17] SLICE_X56Y136 LUT5 (Prop_lut5_I4_O) 0.045 2.060 r u_confreg/s_rdata[17]_i_4/O net (fo=1, routed) 0.262 2.322 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 SLICE_X49Y136 LUT6 (Prop_lut6_I4_O) 0.045 2.367 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O net (fo=1, routed) 0.000 2.367 u_confreg/u_int_ctrl_n_14 SLICE_X49Y136 FDRE r u_confreg/s_rdata_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk SLICE_X49Y136 FDRE r u_confreg/s_rdata_reg[17]/C >>>>>>> Stashed changes Slack: inf Source: dip_sw[28] (input port) <<<<<<< Updated upstream Destination: u_confreg/s_rdata_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 4.824ns (logic 0.326ns (6.749%) route 4.499ns (93.251%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.307ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.307ns ======= Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.371ns (logic 0.255ns (10.737%) route 2.117ns (89.263%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -0.462ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.462ns >>>>>>> Stashed changes Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- <<<<<<< Updated upstream R5 0.000 0.000 r dip_sw[28] (IN) net (fo=0) 0.000 0.000 dip_sw[28] R5 IBUF (Prop_ibuf_I_O) 0.236 0.236 r dip_sw_IBUF[28]_inst/O net (fo=1, routed) 3.990 4.226 u_confreg/dip_sw_IBUF[28] SLICE_X12Y58 LUT5 (Prop_lut5_I4_O) 0.045 4.271 r u_confreg/s_rdata[28]_i_4/O net (fo=1, routed) 0.508 4.779 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 SLICE_X3Y58 LUT6 (Prop_lut6_I4_O) 0.045 4.824 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O net (fo=1, routed) 0.000 4.824 u_confreg/u_int_ctrl_n_3 SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[28]/D ======= P3 0.000 0.000 r touch_btn[2] (IN) net (fo=0) 0.000 0.000 touch_btn[2] P3 IBUF (Prop_ibuf_I_O) 0.255 0.255 r touch_btn_IBUF[2]_inst/O net (fo=1, routed) 2.117 2.371 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[28]/C ======= net (fo=9971, routed) 0.846 -0.462 u_confreg/u_int_ctrl/sys_clk SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C Slack: inf Source: dip_sw[11] (input port) Destination: u_confreg/s_rdata_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.379ns (logic 0.329ns (13.836%) route 2.050ns (86.164%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.457ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L7 0.000 0.000 r dip_sw[11] (IN) net (fo=0) 0.000 0.000 dip_sw[11] L7 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[11]_inst/O net (fo=1, routed) 1.819 2.059 u_confreg/dip_sw_IBUF[11] SLICE_X60Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.104 r u_confreg/s_rdata[11]_i_4/O net (fo=1, routed) 0.230 2.334 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.045 2.379 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O net (fo=1, routed) 0.000 2.379 u_confreg/u_int_ctrl_n_20 SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.851 -0.457 u_confreg/sys_clk SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[11]/C Slack: inf Source: dip_sw[9] (input port) Destination: u_confreg/s_rdata_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.511ns (logic 0.328ns (13.048%) route 2.184ns (86.952%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.458ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N7 0.000 0.000 r dip_sw[9] (IN) net (fo=0) 0.000 0.000 dip_sw[9] N7 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[9]_inst/O net (fo=1, routed) 1.929 2.167 u_confreg/dip_sw_IBUF[9] SLICE_X58Y135 LUT5 (Prop_lut5_I4_O) 0.045 2.212 r u_confreg/s_rdata[9]_i_4/O net (fo=1, routed) 0.254 2.466 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 SLICE_X57Y132 LUT6 (Prop_lut6_I4_O) 0.045 2.511 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O net (fo=1, routed) 0.000 2.511 u_confreg/u_int_ctrl_n_22 SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.850 -0.458 u_confreg/sys_clk SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[9]/C Slack: inf Source: dip_sw[30] (input port) Destination: u_confreg/s_rdata_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.573ns (logic 0.317ns (12.327%) route 2.256ns (87.673%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.451ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R6 0.000 0.000 r dip_sw[30] (IN) net (fo=0) 0.000 0.000 dip_sw[30] R6 IBUF (Prop_ibuf_I_O) 0.227 0.227 r dip_sw_IBUF[30]_inst/O net (fo=1, routed) 2.205 2.432 u_confreg/dip_sw_IBUF[30] SLICE_X57Y140 LUT5 (Prop_lut5_I4_O) 0.045 2.477 r u_confreg/s_rdata[30]_i_4/O net (fo=1, routed) 0.050 2.528 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 SLICE_X57Y140 LUT6 (Prop_lut6_I4_O) 0.045 2.573 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O net (fo=1, routed) 0.000 2.573 u_confreg/u_int_ctrl_n_1 SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.857 -0.451 u_confreg/sys_clk SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[30]/C Slack: inf Source: dip_sw[26] (input port) Destination: u_confreg/s_rdata_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.588ns (logic 0.367ns (14.175%) route 2.221ns (85.825%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.454ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.454ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T4 0.000 0.000 r dip_sw[26] (IN) net (fo=0) 0.000 0.000 dip_sw[26] T4 IBUF (Prop_ibuf_I_O) 0.277 0.277 r dip_sw_IBUF[26]_inst/O net (fo=1, routed) 1.957 2.234 u_confreg/dip_sw_IBUF[26] SLICE_X52Y137 LUT5 (Prop_lut5_I4_O) 0.045 2.279 r u_confreg/s_rdata[26]_i_4/O net (fo=1, routed) 0.264 2.543 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 SLICE_X50Y137 LUT6 (Prop_lut6_I4_O) 0.045 2.588 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O net (fo=1, routed) 0.000 2.588 u_confreg/u_int_ctrl_n_5 SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.854 -0.454 u_confreg/sys_clk SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[26]/C Slack: inf Source: touch_btn[0] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.605ns (logic 0.267ns (10.235%) route 2.338ns (89.765%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -0.460ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T2 0.000 0.000 r touch_btn[0] (IN) net (fo=0) 0.000 0.000 touch_btn[0] T2 IBUF (Prop_ibuf_I_O) 0.267 0.267 r touch_btn_IBUF[0]_inst/O net (fo=1, routed) 2.338 2.605 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] SLICE_X60Y132 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.848 -0.460 u_confreg/u_int_ctrl/sys_clk SLICE_X60Y132 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C Slack: inf Source: dip_sw[10] (input port) Destination: u_confreg/s_rdata_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.611ns (logic 0.330ns (12.645%) route 2.281ns (87.355%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.455ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.455ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M7 0.000 0.000 r dip_sw[10] (IN) net (fo=0) 0.000 0.000 dip_sw[10] M7 IBUF (Prop_ibuf_I_O) 0.240 0.240 r dip_sw_IBUF[10]_inst/O net (fo=1, routed) 1.737 1.977 u_confreg/dip_sw_IBUF[10] SLICE_X62Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.022 r u_confreg/s_rdata[10]_i_4/O net (fo=1, routed) 0.543 2.566 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 SLICE_X55Y135 LUT6 (Prop_lut6_I4_O) 0.045 2.611 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O net (fo=1, routed) 0.000 2.611 u_confreg/u_int_ctrl_n_21 SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[10]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.615ns (logic 0.287ns (10.986%) route 2.328ns (89.014%)) Logic Levels: 2 (IBUF=1 LUT5=1) Clock Path Skew: -0.474ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.474ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 2.328 2.570 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X79Y136 LUT5 (Prop_lut5_I0_O) 0.045 2.615 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O net (fo=1, routed) 0.000 2.615 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.834 -0.474 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C Slack: inf Source: touch_btn[3] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.660ns (logic 0.280ns (10.536%) route 2.380ns (89.464%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -0.461ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- U2 0.000 0.000 r touch_btn[3] (IN) net (fo=0) 0.000 0.000 touch_btn[3] U2 IBUF (Prop_ibuf_I_O) 0.280 0.280 r touch_btn_IBUF[3]_inst/O net (fo=1, routed) 2.380 2.660 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] SLICE_X60Y131 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.847 -0.461 u_confreg/u_int_ctrl/sys_clk SLICE_X60Y131 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C Slack: inf Source: dip_sw[1] (input port) Destination: u_confreg/s_rdata_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.718ns (logic 0.355ns (13.080%) route 2.362ns (86.920%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.457ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J3 0.000 0.000 r dip_sw[1] (IN) net (fo=0) 0.000 0.000 dip_sw[1] J3 IBUF (Prop_ibuf_I_O) 0.265 0.265 r dip_sw_IBUF[1]_inst/O net (fo=1, routed) 1.935 2.201 u_confreg/dip_sw_IBUF[1] SLICE_X66Y141 LUT5 (Prop_lut5_I4_O) 0.045 2.246 r u_confreg/s_rdata[1]_i_4/O net (fo=1, routed) 0.427 2.673 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.045 2.718 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O net (fo=1, routed) 0.000 2.718 u_confreg/u_int_ctrl_n_30 SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.851 -0.457 u_confreg/sys_clk SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[1]/C Slack: inf Source: dip_sw[5] (input port) Destination: u_confreg/s_rdata_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.769ns (logic 0.328ns (11.858%) route 2.441ns (88.142%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.454ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.454ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L5 0.000 0.000 r dip_sw[5] (IN) net (fo=0) 0.000 0.000 dip_sw[5] L5 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[5]_inst/O net (fo=1, routed) 2.069 2.307 u_confreg/dip_sw_IBUF[5] SLICE_X66Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.352 r u_confreg/s_rdata[5]_i_4/O net (fo=1, routed) 0.372 2.724 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 SLICE_X57Y137 LUT6 (Prop_lut6_I4_O) 0.045 2.769 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O net (fo=1, routed) 0.000 2.769 u_confreg/u_int_ctrl_n_26 SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.854 -0.454 u_confreg/sys_clk SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[5]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.788ns (logic 0.393ns (14.104%) route 2.395ns (85.896%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1) Clock Path Skew: -0.474ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.474ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 2.328 2.570 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X79Y136 LUT2 (Prop_lut2_I1_O) 0.044 2.614 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O net (fo=2, routed) 0.068 2.681 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 SLICE_X79Y136 LUT6 (Prop_lut6_I2_O) 0.107 2.788 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O net (fo=1, routed) 0.000 2.788 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.834 -0.474 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C Slack: inf Source: dip_sw[18] (input port) Destination: u_confreg/s_rdata_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.792ns (logic 0.347ns (12.424%) route 2.445ns (87.576%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.461ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N3 0.000 0.000 r dip_sw[18] (IN) net (fo=0) 0.000 0.000 dip_sw[18] N3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[18]_inst/O net (fo=1, routed) 2.224 2.481 u_confreg/dip_sw_IBUF[18] SLICE_X61Y129 LUT5 (Prop_lut5_I4_O) 0.045 2.526 r u_confreg/s_rdata[18]_i_4/O net (fo=1, routed) 0.221 2.747 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 SLICE_X48Y129 LUT6 (Prop_lut6_I4_O) 0.045 2.792 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O net (fo=1, routed) 0.000 2.792 u_confreg/u_int_ctrl_n_13 SLICE_X48Y129 FDRE r u_confreg/s_rdata_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.847 -0.461 u_confreg/sys_clk SLICE_X48Y129 FDRE r u_confreg/s_rdata_reg[18]/C Slack: inf Source: dip_sw[24] (input port) Destination: u_confreg/s_rdata_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.796ns (logic 0.324ns (11.603%) route 2.472ns (88.397%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.452ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P5 0.000 0.000 r dip_sw[24] (IN) net (fo=0) 0.000 0.000 dip_sw[24] P5 IBUF (Prop_ibuf_I_O) 0.234 0.234 r dip_sw_IBUF[24]_inst/O net (fo=1, routed) 2.272 2.506 u_confreg/dip_sw_IBUF[24] SLICE_X55Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.551 r u_confreg/s_rdata[24]_i_4/O net (fo=1, routed) 0.200 2.751 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 SLICE_X52Y139 LUT6 (Prop_lut6_I4_O) 0.045 2.796 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O net (fo=1, routed) 0.000 2.796 u_confreg/u_int_ctrl_n_7 SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[24]/C Slack: inf Source: dip_sw[3] (input port) Destination: u_confreg/s_rdata_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.803ns (logic 0.362ns (12.912%) route 2.441ns (87.088%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.461ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P1 0.000 0.000 r dip_sw[3] (IN) net (fo=0) 0.000 0.000 dip_sw[3] P1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[3]_inst/O net (fo=1, routed) 2.117 2.389 u_confreg/dip_sw_IBUF[3] SLICE_X63Y131 LUT5 (Prop_lut5_I4_O) 0.045 2.434 r u_confreg/s_rdata[3]_i_4/O net (fo=1, routed) 0.324 2.758 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 SLICE_X59Y131 LUT6 (Prop_lut6_I4_O) 0.045 2.803 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O net (fo=1, routed) 0.000 2.803 u_confreg/u_int_ctrl_n_28 SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.847 -0.461 u_confreg/sys_clk SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[3]/C Slack: inf Source: dip_sw[2] (input port) Destination: u_confreg/s_rdata_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.824ns (logic 0.353ns (12.494%) route 2.472ns (87.506%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.459ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.459ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M2 0.000 0.000 r dip_sw[2] (IN) net (fo=0) 0.000 0.000 dip_sw[2] M2 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[2]_inst/O net (fo=1, routed) 2.041 2.304 u_confreg/dip_sw_IBUF[2] SLICE_X66Y131 LUT5 (Prop_lut5_I4_O) 0.045 2.349 r u_confreg/s_rdata[2]_i_4/O net (fo=1, routed) 0.430 2.779 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 SLICE_X56Y131 LUT6 (Prop_lut6_I4_O) 0.045 2.824 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O net (fo=1, routed) 0.000 2.824 u_confreg/u_int_ctrl_n_29 SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.849 -0.459 u_confreg/sys_clk SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[2]/C Slack: inf Source: dip_sw[6] (input port) Destination: u_confreg/s_rdata_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.873ns (logic 0.346ns (12.035%) route 2.527ns (87.965%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.458ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L3 0.000 0.000 r dip_sw[6] (IN) net (fo=0) 0.000 0.000 dip_sw[6] L3 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[6]_inst/O net (fo=1, routed) 2.127 2.383 u_confreg/dip_sw_IBUF[6] SLICE_X65Y134 LUT5 (Prop_lut5_I4_O) 0.045 2.428 r u_confreg/s_rdata[6]_i_4/O net (fo=1, routed) 0.400 2.828 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 SLICE_X57Y132 LUT6 (Prop_lut6_I4_O) 0.045 2.873 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O net (fo=1, routed) 0.000 2.873 u_confreg/u_int_ctrl_n_25 SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.850 -0.458 u_confreg/sys_clk SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[6]/C Slack: inf Source: dip_sw[21] (input port) Destination: u_confreg/s_rdata_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.877ns (logic 0.346ns (12.026%) route 2.531ns (87.974%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.452ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N2 0.000 0.000 r dip_sw[21] (IN) net (fo=0) 0.000 0.000 dip_sw[21] N2 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[21]_inst/O net (fo=1, routed) 2.343 2.599 u_confreg/dip_sw_IBUF[21] SLICE_X57Y138 LUT5 (Prop_lut5_I4_O) 0.045 2.644 r u_confreg/s_rdata[21]_i_4/O net (fo=1, routed) 0.187 2.832 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 SLICE_X51Y138 LUT6 (Prop_lut6_I4_O) 0.045 2.877 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O net (fo=1, routed) 0.000 2.877 u_confreg/u_int_ctrl_n_10 SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[21]/C Slack: inf Source: dip_sw[0] (input port) Destination: u_confreg/s_rdata_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.880ns (logic 0.353ns (12.249%) route 2.527ns (87.751%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.459ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.459ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T3 0.000 0.000 r dip_sw[0] (IN) net (fo=0) 0.000 0.000 dip_sw[0] T3 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[0]_inst/O net (fo=1, routed) 2.218 2.481 u_confreg/dip_sw_IBUF[0] SLICE_X62Y133 LUT5 (Prop_lut5_I4_O) 0.045 2.526 r u_confreg/s_rdata[0]_i_4/O net (fo=1, routed) 0.309 2.835 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 SLICE_X60Y133 LUT6 (Prop_lut6_I4_O) 0.045 2.880 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O net (fo=1, routed) 0.000 2.880 u_confreg/u_int_ctrl_n_31 SLICE_X60Y133 FDRE r u_confreg/s_rdata_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.849 -0.459 u_confreg/sys_clk SLICE_X60Y133 FDRE r u_confreg/s_rdata_reg[0]/C Slack: inf Source: dip_sw[13] (input port) Destination: u_confreg/s_rdata_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.890ns (logic 0.344ns (11.888%) route 2.547ns (88.112%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.457ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K3 0.000 0.000 r dip_sw[13] (IN) net (fo=0) 0.000 0.000 dip_sw[13] K3 IBUF (Prop_ibuf_I_O) 0.254 0.254 r dip_sw_IBUF[13]_inst/O net (fo=1, routed) 2.319 2.572 u_confreg/dip_sw_IBUF[13] SLICE_X58Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.617 r u_confreg/s_rdata[13]_i_4/O net (fo=1, routed) 0.228 2.845 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.045 2.890 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O net (fo=1, routed) 0.000 2.890 u_confreg/u_int_ctrl_n_18 SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.851 -0.457 u_confreg/sys_clk SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[13]/C Slack: inf Source: dip_sw[12] (input port) Destination: u_confreg/s_rdata_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.899ns (logic 0.327ns (11.281%) route 2.572ns (88.719%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.455ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.455ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M5 0.000 0.000 r dip_sw[12] (IN) net (fo=0) 0.000 0.000 dip_sw[12] M5 IBUF (Prop_ibuf_I_O) 0.237 0.237 r dip_sw_IBUF[12]_inst/O net (fo=1, routed) 2.212 2.449 u_confreg/dip_sw_IBUF[12] SLICE_X59Y137 LUT5 (Prop_lut5_I4_O) 0.045 2.494 r u_confreg/s_rdata[12]_i_4/O net (fo=1, routed) 0.360 2.854 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.045 2.899 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O net (fo=1, routed) 0.000 2.899 u_confreg/u_int_ctrl_n_19 SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[12]/C Slack: inf Source: dip_sw[8] (input port) Destination: u_confreg/s_rdata_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.908ns (logic 0.334ns (11.472%) route 2.575ns (88.528%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.461ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M6 0.000 0.000 r dip_sw[8] (IN) net (fo=0) 0.000 0.000 dip_sw[8] M6 IBUF (Prop_ibuf_I_O) 0.244 0.244 r dip_sw_IBUF[8]_inst/O net (fo=1, routed) 2.293 2.537 u_confreg/dip_sw_IBUF[8] SLICE_X61Y135 LUT5 (Prop_lut5_I4_O) 0.045 2.582 r u_confreg/s_rdata[8]_i_4/O net (fo=1, routed) 0.282 2.863 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 SLICE_X59Y131 LUT6 (Prop_lut6_I4_O) 0.045 2.908 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O net (fo=1, routed) 0.000 2.908 u_confreg/u_int_ctrl_n_23 SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.847 -0.461 u_confreg/sys_clk SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[8]/C Slack: inf Source: dip_sw[20] (input port) Destination: u_confreg/s_rdata_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.916ns (logic 0.333ns (11.420%) route 2.583ns (88.580%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.452ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M4 0.000 0.000 r dip_sw[20] (IN) net (fo=0) 0.000 0.000 dip_sw[20] M4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r dip_sw_IBUF[20]_inst/O net (fo=1, routed) 2.250 2.493 u_confreg/dip_sw_IBUF[20] SLICE_X54Y140 LUT5 (Prop_lut5_I4_O) 0.045 2.538 r u_confreg/s_rdata[20]_i_4/O net (fo=1, routed) 0.332 2.871 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 SLICE_X50Y138 LUT6 (Prop_lut6_I4_O) 0.045 2.916 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O net (fo=1, routed) 0.000 2.916 u_confreg/u_int_ctrl_n_11 SLICE_X50Y138 FDRE r u_confreg/s_rdata_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk SLICE_X50Y138 FDRE r u_confreg/s_rdata_reg[20]/C Slack: inf Source: dip_sw[4] (input port) Destination: u_confreg/s_rdata_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.923ns (logic 0.346ns (11.834%) route 2.577ns (88.166%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.455ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.455ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P4 0.000 0.000 r dip_sw[4] (IN) net (fo=0) 0.000 0.000 dip_sw[4] P4 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[4]_inst/O net (fo=1, routed) 2.226 2.482 u_confreg/dip_sw_IBUF[4] SLICE_X63Y134 LUT5 (Prop_lut5_I4_O) 0.045 2.527 r u_confreg/s_rdata[4]_i_4/O net (fo=1, routed) 0.351 2.878 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 SLICE_X55Y135 LUT6 (Prop_lut6_I4_O) 0.045 2.923 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O net (fo=1, routed) 0.000 2.923 u_confreg/u_int_ctrl_n_27 SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[4]/C Slack: inf Source: dip_sw[16] (input port) Destination: u_confreg/s_rdata_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.946ns (logic 0.358ns (12.144%) route 2.588ns (87.856%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.455ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.455ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K2 0.000 0.000 r dip_sw[16] (IN) net (fo=0) 0.000 0.000 dip_sw[16] K2 IBUF (Prop_ibuf_I_O) 0.268 0.268 r dip_sw_IBUF[16]_inst/O net (fo=1, routed) 2.202 2.469 u_confreg/dip_sw_IBUF[16] SLICE_X62Y135 LUT5 (Prop_lut5_I4_O) 0.045 2.514 r u_confreg/s_rdata[16]_i_4/O net (fo=1, routed) 0.386 2.901 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.045 2.946 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O net (fo=1, routed) 0.000 2.946 u_confreg/u_int_ctrl_n_15 SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[16]/C Slack: inf Source: dip_sw[7] (input port) Destination: u_confreg/s_rdata_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.963ns (logic 0.329ns (11.112%) route 2.634ns (88.888%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.459ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.459ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N6 0.000 0.000 r dip_sw[7] (IN) net (fo=0) 0.000 0.000 dip_sw[7] N6 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[7]_inst/O net (fo=1, routed) 2.091 2.331 u_confreg/dip_sw_IBUF[7] SLICE_X66Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.376 r u_confreg/s_rdata[7]_i_4/O net (fo=1, routed) 0.542 2.918 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 SLICE_X56Y131 LUT6 (Prop_lut6_I4_O) 0.045 2.963 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O net (fo=1, routed) 0.000 2.963 u_confreg/u_int_ctrl_n_24 SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.849 -0.459 u_confreg/sys_clk SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[7]/C >>>>>>> Stashed changes Slack: inf Source: dip_sw[25] (input port) Destination: u_confreg/s_rdata_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) <<<<<<< Updated upstream Data Path Delay: 5.158ns (logic 0.347ns (6.729%) route 4.811ns (93.271%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.309ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns ======= Data Path Delay: 2.966ns (logic 0.347ns (11.701%) route 2.619ns (88.299%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.452ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns >>>>>>> Stashed changes Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R3 0.000 0.000 r dip_sw[25] (IN) net (fo=0) 0.000 0.000 dip_sw[25] R3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[25]_inst/O <<<<<<< Updated upstream net (fo=1, routed) 4.470 4.727 u_confreg/dip_sw_IBUF[25] SLICE_X1Y60 LUT5 (Prop_lut5_I4_O) 0.045 4.772 r u_confreg/s_rdata[25]_i_4/O net (fo=1, routed) 0.341 5.113 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 SLICE_X5Y58 LUT6 (Prop_lut6_I4_O) 0.045 5.158 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O net (fo=1, routed) 0.000 5.158 u_confreg/u_int_ctrl_n_6 SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[25]/D ======= net (fo=1, routed) 2.366 2.623 u_confreg/dip_sw_IBUF[25] SLICE_X55Y138 LUT5 (Prop_lut5_I4_O) 0.045 2.668 r u_confreg/s_rdata[25]_i_4/O net (fo=1, routed) 0.253 2.921 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 SLICE_X51Y138 LUT6 (Prop_lut6_I4_O) 0.045 2.966 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O net (fo=1, routed) 0.000 2.966 u_confreg/u_int_ctrl_n_6 SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[25]/D >>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O <<<<<<< Updated upstream net (fo=35652, routed) 0.999 -0.309 u_confreg/sys_clk SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[25]/C ======= net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[25]/C Slack: inf Source: dip_sw[15] (input port) Destination: u_confreg/s_rdata_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.012ns (logic 0.352ns (11.684%) route 2.660ns (88.316%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.455ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.455ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L2 0.000 0.000 r dip_sw[15] (IN) net (fo=0) 0.000 0.000 dip_sw[15] L2 IBUF (Prop_ibuf_I_O) 0.262 0.262 r dip_sw_IBUF[15]_inst/O net (fo=1, routed) 2.317 2.579 u_confreg/dip_sw_IBUF[15] SLICE_X58Y135 LUT5 (Prop_lut5_I4_O) 0.045 2.624 r u_confreg/s_rdata[15]_i_4/O net (fo=1, routed) 0.343 2.967 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 SLICE_X49Y135 LUT6 (Prop_lut6_I4_O) 0.045 3.012 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O net (fo=1, routed) 0.000 3.012 u_confreg/u_int_ctrl_n_16 SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[15]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.028ns (logic 0.392ns (12.954%) route 2.636ns (87.046%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) Clock Path Skew: -0.474ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.474ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 2.328 2.570 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X79Y136 LUT2 (Prop_lut2_I1_O) 0.044 2.614 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O net (fo=2, routed) 0.308 2.922 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 SLICE_X78Y136 LUT5 (Prop_lut5_I1_O) 0.106 3.028 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O net (fo=1, routed) 0.000 3.028 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 SLICE_X78Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.834 -0.474 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X78Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C Slack: inf Source: dip_sw[14] (input port) Destination: u_confreg/s_rdata_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.067ns (logic 0.373ns (12.147%) route 2.694ns (87.853%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.455ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.455ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J1 0.000 0.000 r dip_sw[14] (IN) net (fo=0) 0.000 0.000 dip_sw[14] J1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r dip_sw_IBUF[14]_inst/O net (fo=1, routed) 2.150 2.432 u_confreg/dip_sw_IBUF[14] SLICE_X62Y135 LUT5 (Prop_lut5_I4_O) 0.045 2.477 r u_confreg/s_rdata[14]_i_4/O net (fo=1, routed) 0.545 3.022 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 SLICE_X49Y135 LUT6 (Prop_lut6_I4_O) 0.045 3.067 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O net (fo=1, routed) 0.000 3.067 u_confreg/u_int_ctrl_n_17 SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[14]/C Slack: inf Source: dip_sw[27] (input port) Destination: u_confreg/s_rdata_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.109ns (logic 0.362ns (11.659%) route 2.746ns (88.341%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.454ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.454ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R1 0.000 0.000 r dip_sw[27] (IN) net (fo=0) 0.000 0.000 dip_sw[27] R1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[27]_inst/O net (fo=1, routed) 2.348 2.621 u_confreg/dip_sw_IBUF[27] SLICE_X61Y135 LUT5 (Prop_lut5_I4_O) 0.045 2.666 r u_confreg/s_rdata[27]_i_4/O net (fo=1, routed) 0.398 3.064 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 SLICE_X50Y137 LUT6 (Prop_lut6_I4_O) 0.045 3.109 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O net (fo=1, routed) 0.000 3.109 u_confreg/u_int_ctrl_n_4 SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.854 -0.454 u_confreg/sys_clk SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[27]/C Slack: inf Source: dip_sw[19] (input port) Destination: u_confreg/s_rdata_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.148ns (logic 0.336ns (10.676%) route 2.812ns (89.324%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.455ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.455ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L4 0.000 0.000 r dip_sw[19] (IN) net (fo=0) 0.000 0.000 dip_sw[19] L4 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[19]_inst/O net (fo=1, routed) 2.485 2.731 u_confreg/dip_sw_IBUF[19] SLICE_X54Y136 LUT5 (Prop_lut5_I4_O) 0.045 2.776 r u_confreg/s_rdata[19]_i_4/O net (fo=1, routed) 0.327 3.103 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.045 3.148 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O net (fo=1, routed) 0.000 3.148 u_confreg/u_int_ctrl_n_12 SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[19]/C Slack: inf Source: dip_sw[29] (input port) Destination: u_confreg/s_rdata_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.199ns (logic 0.336ns (10.503%) route 2.863ns (89.497%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.451ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T5 0.000 0.000 r dip_sw[29] (IN) net (fo=0) 0.000 0.000 dip_sw[29] T5 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[29]_inst/O net (fo=1, routed) 2.536 2.782 u_confreg/dip_sw_IBUF[29] SLICE_X60Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.827 r u_confreg/s_rdata[29]_i_4/O net (fo=1, routed) 0.326 3.154 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 SLICE_X57Y140 LUT6 (Prop_lut6_I4_O) 0.045 3.199 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O net (fo=1, routed) 0.000 3.199 u_confreg/u_int_ctrl_n_2 SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.857 -0.451 u_confreg/sys_clk SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[29]/C Slack: inf Source: dip_sw[22] (input port) Destination: u_confreg/s_rdata_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 3.279ns (logic 0.320ns (9.768%) route 2.959ns (90.232%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.451ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P6 0.000 0.000 r dip_sw[22] (IN) net (fo=0) 0.000 0.000 dip_sw[22] P6 IBUF (Prop_ibuf_I_O) 0.230 0.230 r dip_sw_IBUF[22]_inst/O net (fo=1, routed) 2.615 2.845 u_confreg/dip_sw_IBUF[22] SLICE_X58Y140 LUT5 (Prop_lut5_I4_O) 0.045 2.890 r u_confreg/s_rdata[22]_i_4/O net (fo=1, routed) 0.345 3.234 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 SLICE_X52Y140 LUT6 (Prop_lut6_I4_O) 0.045 3.279 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O net (fo=1, routed) 0.000 3.279 u_confreg/u_int_ctrl_n_9 SLICE_X52Y140 FDRE r u_confreg/s_rdata_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.857 -0.451 u_confreg/sys_clk SLICE_X52Y140 FDRE r u_confreg/s_rdata_reg[22]/C >>>>>>> Stashed changes