Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 | Date : Wed Jul 8 02:57:58 2026 | Host : fedora running 64-bit unknown | Command : report_timing -from [get_clocks mlkem_clk_clk_pll] -to [get_clocks mlkem_clk_clk_pll] -delay_type max -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_withdsp/mlkem_clk_timing.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Timing Report Slack (MET) : 12.906ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.488ns (logic 1.164ns (4.394%) route 25.324ns (95.606%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400] ------------------------------------------------------------------- required time 36.872 arrival time -23.966 ------------------------------------------------------------------- slack 12.906 Slack (MET) : 12.906ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.488ns (logic 1.164ns (4.394%) route 25.324ns (95.606%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400] ------------------------------------------------------------------- required time 36.872 arrival time -23.966 ------------------------------------------------------------------- slack 12.906 Slack (MET) : 12.906ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.488ns (logic 1.164ns (4.394%) route 25.324ns (95.606%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592] ------------------------------------------------------------------- required time 36.872 arrival time -23.966 ------------------------------------------------------------------- slack 12.906 Slack (MET) : 12.906ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.488ns (logic 1.164ns (4.394%) route 25.324ns (95.606%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592] ------------------------------------------------------------------- required time 36.872 arrival time -23.966 ------------------------------------------------------------------- slack 12.906 Slack (MET) : 12.985ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.751ns (logic 1.556ns (5.817%) route 25.195ns (94.183%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.245 21.384 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X123Y140 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[602]_i_3/I3 SLICE_X123Y140 LUT4 (Prop_lut4_I3_O) 0.118 21.502 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[602]_i_3/O net (fo=1, routed) 1.525 23.027 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[602] SLICE_X132Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[602]_i_2/I0 SLICE_X132Y158 LUT6 (Prop_lut6_I0_O) 0.326 23.353 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[602]_i_2/O net (fo=1, routed) 0.757 24.111 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[341] SLICE_X134Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[602]_i_1/I1 SLICE_X134Y155 LUT3 (Prop_lut3_I1_O) 0.118 24.229 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[602]_i_1/O net (fo=1, routed) 0.000 24.229 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[602] SLICE_X134Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X134Y155 FDCE (Setup_fdce_C_D) 0.075 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602] ------------------------------------------------------------------- required time 37.213 arrival time -24.229 ------------------------------------------------------------------- slack 12.985 Slack (MET) : 12.985ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.751ns (logic 1.556ns (5.817%) route 25.195ns (94.183%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.245 21.384 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X123Y140 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[602]_i_3/I3 SLICE_X123Y140 LUT4 (Prop_lut4_I3_O) 0.118 21.502 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[602]_i_3/O net (fo=1, routed) 1.525 23.027 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[602] SLICE_X132Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[602]_i_2/I0 SLICE_X132Y158 LUT6 (Prop_lut6_I0_O) 0.326 23.353 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[602]_i_2/O net (fo=1, routed) 0.757 24.111 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[341] SLICE_X134Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[602]_i_1/I1 SLICE_X134Y155 LUT3 (Prop_lut3_I1_O) 0.118 24.229 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[602]_i_1/O net (fo=1, routed) 0.000 24.229 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[602] SLICE_X134Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X134Y155 FDCE (Setup_fdce_C_D) 0.075 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602] ------------------------------------------------------------------- required time 37.213 arrival time -24.229 ------------------------------------------------------------------- slack 12.985 Slack (MET) : 12.994ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.404ns (logic 1.164ns (4.408%) route 25.240ns (95.592%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.279 23.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X153Y128 FDCE (Setup_fdce_C_CE) -0.413 36.875 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527] ------------------------------------------------------------------- required time 36.875 arrival time -23.881 ------------------------------------------------------------------- slack 12.994 Slack (MET) : 12.994ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.404ns (logic 1.164ns (4.408%) route 25.240ns (95.592%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.279 23.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X153Y128 FDCE (Setup_fdce_C_CE) -0.413 36.875 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527] ------------------------------------------------------------------- required time 36.875 arrival time -23.881 ------------------------------------------------------------------- slack 12.994 Slack (MET) : 13.047ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.784ns (logic 1.624ns (6.063%) route 25.160ns (93.937%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.167ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.255ns = ( 37.745 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.176 20.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X119Y148 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[795]_i_3/I3 SLICE_X119Y148 LUT4 (Prop_lut4_I3_O) 0.152 20.467 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[795]_i_3/O net (fo=1, routed) 1.499 21.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[795] SLICE_X120Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[795]_i_2/I0 SLICE_X120Y158 LUT6 (Prop_lut6_I0_O) 0.326 22.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[795]_i_2/O net (fo=1, routed) 1.818 24.110 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[534] SLICE_X131Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[795]_i_1/I1 SLICE_X131Y145 LUT3 (Prop_lut3_I1_O) 0.152 24.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[795]_i_1/O net (fo=1, routed) 0.000 24.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[795] SLICE_X131Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.420 37.745 clock pessimism -0.435 37.310 clock uncertainty -0.077 37.234 SLICE_X131Y145 FDCE (Setup_fdce_C_D) 0.075 37.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795] ------------------------------------------------------------------- required time 37.309 arrival time -24.262 ------------------------------------------------------------------- slack 13.047 Slack (MET) : 13.047ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.784ns (logic 1.624ns (6.063%) route 25.160ns (93.937%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.167ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.255ns = ( 37.745 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.176 20.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X119Y148 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[795]_i_3/I3 SLICE_X119Y148 LUT4 (Prop_lut4_I3_O) 0.152 20.467 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[795]_i_3/O net (fo=1, routed) 1.499 21.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[795] SLICE_X120Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[795]_i_2/I0 SLICE_X120Y158 LUT6 (Prop_lut6_I0_O) 0.326 22.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[795]_i_2/O net (fo=1, routed) 1.818 24.110 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[534] SLICE_X131Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[795]_i_1/I1 SLICE_X131Y145 LUT3 (Prop_lut3_I1_O) 0.152 24.262 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[795]_i_1/O net (fo=1, routed) 0.000 24.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[795] SLICE_X131Y145 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.420 37.745 clock pessimism -0.435 37.310 clock uncertainty -0.077 37.234 SLICE_X131Y145 FDCE (Setup_fdce_C_D) 0.075 37.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795] ------------------------------------------------------------------- required time 37.309 arrival time -24.262 ------------------------------------------------------------------- slack 13.047 Slack (MET) : 13.154ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.538ns (logic 1.562ns (5.886%) route 24.976ns (94.114%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.901 21.041 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X130Y146 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[629]_i_3/I3 SLICE_X130Y146 LUT4 (Prop_lut4_I3_O) 0.118 21.159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[629]_i_3/O net (fo=1, routed) 1.198 22.357 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[629] SLICE_X134Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[629]_i_2/I0 SLICE_X134Y157 LUT6 (Prop_lut6_I0_O) 0.326 22.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[629]_i_2/O net (fo=1, routed) 1.209 23.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[368] SLICE_X134Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[629]_i_1/I1 SLICE_X134Y155 LUT3 (Prop_lut3_I1_O) 0.124 24.016 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[629]_i_1/O net (fo=1, routed) 0.000 24.016 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[629] SLICE_X134Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X134Y155 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629] ------------------------------------------------------------------- required time 37.169 arrival time -24.016 ------------------------------------------------------------------- slack 13.154 Slack (MET) : 13.154ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.538ns (logic 1.562ns (5.886%) route 24.976ns (94.114%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.901 21.041 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X130Y146 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[629]_i_3/I3 SLICE_X130Y146 LUT4 (Prop_lut4_I3_O) 0.118 21.159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[629]_i_3/O net (fo=1, routed) 1.198 22.357 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[629] SLICE_X134Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[629]_i_2/I0 SLICE_X134Y157 LUT6 (Prop_lut6_I0_O) 0.326 22.683 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[629]_i_2/O net (fo=1, routed) 1.209 23.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[368] SLICE_X134Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[629]_i_1/I1 SLICE_X134Y155 LUT3 (Prop_lut3_I1_O) 0.124 24.016 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[629]_i_1/O net (fo=1, routed) 0.000 24.016 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[629] SLICE_X134Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X134Y155 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629] ------------------------------------------------------------------- required time 37.169 arrival time -24.016 ------------------------------------------------------------------- slack 13.154 Slack (MET) : 13.175ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.605ns (logic 1.612ns (6.059%) route 24.993ns (93.941%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.271ns = ( 37.729 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.059 21.198 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X136Y146 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[731]_i_3/I3 SLICE_X136Y146 LUT4 (Prop_lut4_I3_O) 0.117 21.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[731]_i_3/O net (fo=1, routed) 1.245 22.560 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[731] SLICE_X138Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[731]_i_2/I0 SLICE_X138Y157 LUT6 (Prop_lut6_I0_O) 0.348 22.908 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[731]_i_2/O net (fo=1, routed) 1.021 23.930 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[470] SLICE_X132Y150 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[731]_i_1/I1 SLICE_X132Y150 LUT3 (Prop_lut3_I1_O) 0.153 24.083 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[731]_i_1/O net (fo=1, routed) 0.000 24.083 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[731] SLICE_X132Y150 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.404 37.729 clock pessimism -0.514 37.216 clock uncertainty -0.077 37.139 SLICE_X132Y150 FDCE (Setup_fdce_C_D) 0.118 37.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731] ------------------------------------------------------------------- required time 37.257 arrival time -24.083 ------------------------------------------------------------------- slack 13.175 Slack (MET) : 13.175ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.605ns (logic 1.612ns (6.059%) route 24.993ns (93.941%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.271ns = ( 37.729 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.059 21.198 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X136Y146 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[731]_i_3/I3 SLICE_X136Y146 LUT4 (Prop_lut4_I3_O) 0.117 21.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[731]_i_3/O net (fo=1, routed) 1.245 22.560 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[731] SLICE_X138Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[731]_i_2/I0 SLICE_X138Y157 LUT6 (Prop_lut6_I0_O) 0.348 22.908 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[731]_i_2/O net (fo=1, routed) 1.021 23.930 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[470] SLICE_X132Y150 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[731]_i_1/I1 SLICE_X132Y150 LUT3 (Prop_lut3_I1_O) 0.153 24.083 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[731]_i_1/O net (fo=1, routed) 0.000 24.083 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[731] SLICE_X132Y150 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.404 37.729 clock pessimism -0.514 37.216 clock uncertainty -0.077 37.139 SLICE_X132Y150 FDCE (Setup_fdce_C_D) 0.118 37.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731] ------------------------------------------------------------------- required time 37.257 arrival time -24.083 ------------------------------------------------------------------- slack 13.175 Slack (MET) : 13.189ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.205ns (logic 1.392ns (5.312%) route 24.813ns (94.688%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.682 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400] ------------------------------------------------------------------- required time 36.872 arrival time -23.682 ------------------------------------------------------------------- slack 13.189 Slack (MET) : 13.189ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.205ns (logic 1.392ns (5.312%) route 24.813ns (94.688%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.682 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400] ------------------------------------------------------------------- required time 36.872 arrival time -23.682 ------------------------------------------------------------------- slack 13.189 Slack (MET) : 13.189ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.205ns (logic 1.392ns (5.312%) route 24.813ns (94.688%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.682 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592] ------------------------------------------------------------------- required time 36.872 arrival time -23.682 ------------------------------------------------------------------- slack 13.189 Slack (MET) : 13.189ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.205ns (logic 1.392ns (5.312%) route 24.813ns (94.688%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.682 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592] ------------------------------------------------------------------- required time 36.872 arrival time -23.682 ------------------------------------------------------------------- slack 13.189 Slack (MET) : 13.193ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.240ns (logic 1.164ns (4.436%) route 25.076ns (95.564%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402] ------------------------------------------------------------------- required time 36.911 arrival time -23.717 ------------------------------------------------------------------- slack 13.193 Slack (MET) : 13.193ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.240ns (logic 1.164ns (4.436%) route 25.076ns (95.564%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402] ------------------------------------------------------------------- required time 36.911 arrival time -23.717 ------------------------------------------------------------------- slack 13.193 Slack (MET) : 13.193ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.240ns (logic 1.164ns (4.436%) route 25.076ns (95.564%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466] ------------------------------------------------------------------- required time 36.911 arrival time -23.717 ------------------------------------------------------------------- slack 13.193 Slack (MET) : 13.193ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.240ns (logic 1.164ns (4.436%) route 25.076ns (95.564%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466] ------------------------------------------------------------------- required time 36.911 arrival time -23.717 ------------------------------------------------------------------- slack 13.193 Slack (MET) : 13.240ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.153ns (logic 1.164ns (4.451%) route 24.989ns (95.549%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.028 23.630 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X151Y124 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X151Y124 FDCE (Setup_fdce_C_CE) -0.413 36.870 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383] ------------------------------------------------------------------- required time 36.870 arrival time -23.630 ------------------------------------------------------------------- slack 13.240 Slack (MET) : 13.240ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.153ns (logic 1.164ns (4.451%) route 24.989ns (95.549%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.028 23.630 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X151Y124 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X151Y124 FDCE (Setup_fdce_C_CE) -0.413 36.870 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383] ------------------------------------------------------------------- required time 36.870 arrival time -23.630 ------------------------------------------------------------------- slack 13.240 Slack (MET) : 13.246ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.531ns (logic 1.366ns (5.149%) route 25.165ns (94.851%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.264ns = ( 37.736 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.901 21.041 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X130Y146 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[296]_i_3/I3 SLICE_X130Y146 LUT4 (Prop_lut4_I3_O) 0.124 21.165 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[296]_i_3/O net (fo=1, routed) 1.879 23.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[296] SLICE_X123Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[296]_i_2/I0 SLICE_X123Y131 LUT6 (Prop_lut6_I0_O) 0.124 23.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[296]_i_2/O net (fo=1, routed) 0.717 23.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[35] SLICE_X123Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[296]_i_1/I1 SLICE_X123Y133 LUT3 (Prop_lut3_I1_O) 0.124 24.008 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[296]_i_1/O net (fo=1, routed) 0.000 24.008 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[296] SLICE_X123Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.411 37.736 clock pessimism -0.435 37.301 clock uncertainty -0.077 37.225 SLICE_X123Y133 FDCE (Setup_fdce_C_D) 0.029 37.254 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296] ------------------------------------------------------------------- required time 37.254 arrival time -24.008 ------------------------------------------------------------------- slack 13.246 Slack (MET) : 13.246ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.531ns (logic 1.366ns (5.149%) route 25.165ns (94.851%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.264ns = ( 37.736 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.901 21.041 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X130Y146 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[296]_i_3/I3 SLICE_X130Y146 LUT4 (Prop_lut4_I3_O) 0.124 21.165 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[296]_i_3/O net (fo=1, routed) 1.879 23.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[296] SLICE_X123Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[296]_i_2/I0 SLICE_X123Y131 LUT6 (Prop_lut6_I0_O) 0.124 23.167 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[296]_i_2/O net (fo=1, routed) 0.717 23.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[35] SLICE_X123Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[296]_i_1/I1 SLICE_X123Y133 LUT3 (Prop_lut3_I1_O) 0.124 24.008 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[296]_i_1/O net (fo=1, routed) 0.000 24.008 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[296] SLICE_X123Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.411 37.736 clock pessimism -0.435 37.301 clock uncertainty -0.077 37.225 SLICE_X123Y133 FDCE (Setup_fdce_C_D) 0.029 37.254 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296] ------------------------------------------------------------------- required time 37.254 arrival time -24.008 ------------------------------------------------------------------- slack 13.246 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.480 37.805 clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.480 37.805 clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.480 37.805 clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.480 37.805 clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.480 37.805 clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.480 37.805 clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.277ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.120ns (logic 1.392ns (5.329%) route 24.728ns (94.671%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.279 23.598 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X153Y128 FDCE (Setup_fdce_C_CE) -0.413 36.875 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527] ------------------------------------------------------------------- required time 36.875 arrival time -23.598 ------------------------------------------------------------------- slack 13.277 Slack (MET) : 13.277ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.120ns (logic 1.392ns (5.329%) route 24.728ns (94.671%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.279 23.598 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X153Y128 FDCE (Setup_fdce_C_CE) -0.413 36.875 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527] ------------------------------------------------------------------- required time 36.875 arrival time -23.598 ------------------------------------------------------------------- slack 13.277 Slack (MET) : 13.292ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.141ns (logic 1.164ns (4.453%) route 24.977ns (95.547%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.016 23.618 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X146Y128 FDCE (Setup_fdce_C_CE) -0.377 36.910 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472] ------------------------------------------------------------------- required time 36.910 arrival time -23.618 ------------------------------------------------------------------- slack 13.292 Slack (MET) : 13.292ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.141ns (logic 1.164ns (4.453%) route 24.977ns (95.547%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.016 23.618 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X146Y128 FDCE (Setup_fdce_C_CE) -0.377 36.910 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472] ------------------------------------------------------------------- required time 36.910 arrival time -23.618 ------------------------------------------------------------------- slack 13.292 Slack (MET) : 13.292ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.141ns (logic 1.164ns (4.453%) route 24.977ns (95.547%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.016 23.618 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X146Y128 FDCE (Setup_fdce_C_CE) -0.377 36.910 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478] ------------------------------------------------------------------- required time 36.910 arrival time -23.618 ------------------------------------------------------------------- slack 13.292 Slack (MET) : 13.292ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.141ns (logic 1.164ns (4.453%) route 24.977ns (95.547%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.016 23.618 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X146Y128 FDCE (Setup_fdce_C_CE) -0.377 36.910 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478] ------------------------------------------------------------------- required time 36.910 arrival time -23.618 ------------------------------------------------------------------- slack 13.292 Slack (MET) : 13.301ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.131ns (logic 1.164ns (4.455%) route 24.967ns (95.545%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.203ns = ( 37.797 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.006 23.608 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X152Y127 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.472 37.797 clock pessimism -0.435 37.362 clock uncertainty -0.077 37.286 SLICE_X152Y127 FDCE (Setup_fdce_C_CE) -0.377 36.909 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384] ------------------------------------------------------------------- required time 36.909 arrival time -23.608 ------------------------------------------------------------------- slack 13.301 Slack (MET) : 13.301ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.131ns (logic 1.164ns (4.455%) route 24.967ns (95.545%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.203ns = ( 37.797 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.006 23.608 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X152Y127 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.472 37.797 clock pessimism -0.435 37.362 clock uncertainty -0.077 37.286 SLICE_X152Y127 FDCE (Setup_fdce_C_CE) -0.377 36.909 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384] ------------------------------------------------------------------- required time 36.909 arrival time -23.608 ------------------------------------------------------------------- slack 13.301 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.317ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.018ns (logic 1.164ns (4.474%) route 24.854ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.263ns = ( 37.737 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.894 23.495 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X133Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.412 37.737 clock pessimism -0.435 37.302 clock uncertainty -0.077 37.226 SLICE_X133Y117 FDCE (Setup_fdce_C_CE) -0.413 36.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568] ------------------------------------------------------------------- required time 36.813 arrival time -23.495 ------------------------------------------------------------------- slack 13.317 Slack (MET) : 13.317ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.018ns (logic 1.164ns (4.474%) route 24.854ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.263ns = ( 37.737 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.894 23.495 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X133Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.412 37.737 clock pessimism -0.435 37.302 clock uncertainty -0.077 37.226 SLICE_X133Y117 FDCE (Setup_fdce_C_CE) -0.413 36.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568] ------------------------------------------------------------------- required time 36.813 arrival time -23.495 ------------------------------------------------------------------- slack 13.317 Slack (MET) : 13.317ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.018ns (logic 1.164ns (4.474%) route 24.854ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.263ns = ( 37.737 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.894 23.495 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X133Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.412 37.737 clock pessimism -0.435 37.302 clock uncertainty -0.077 37.226 SLICE_X133Y117 FDCE (Setup_fdce_C_CE) -0.413 36.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574] ------------------------------------------------------------------- required time 36.813 arrival time -23.495 ------------------------------------------------------------------- slack 13.317 Slack (MET) : 13.317ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.018ns (logic 1.164ns (4.474%) route 24.854ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.263ns = ( 37.737 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.894 23.495 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X133Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.412 37.737 clock pessimism -0.435 37.302 clock uncertainty -0.077 37.226 SLICE_X133Y117 FDCE (Setup_fdce_C_CE) -0.413 36.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574] ------------------------------------------------------------------- required time 36.813 arrival time -23.495 ------------------------------------------------------------------- slack 13.317 Slack (MET) : 13.319ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.482ns (logic 1.594ns (6.019%) route 24.888ns (93.981%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.209ns = ( 37.791 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.909 21.049 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X125Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[675]_i_3/I3 SLICE_X125Y147 LUT4 (Prop_lut4_I3_O) 0.150 21.199 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[675]_i_3/O net (fo=1, routed) 1.702 22.901 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[675] SLICE_X141Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[675]_i_2/I0 SLICE_X141Y156 LUT6 (Prop_lut6_I0_O) 0.326 23.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[675]_i_2/O net (fo=1, routed) 0.609 23.835 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[414] SLICE_X142Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[675]_i_1/I1 SLICE_X142Y156 LUT3 (Prop_lut3_I1_O) 0.124 23.959 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[675]_i_1/O net (fo=1, routed) 0.000 23.959 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[675] SLICE_X142Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.466 37.791 clock pessimism -0.514 37.278 clock uncertainty -0.077 37.201 SLICE_X142Y156 FDCE (Setup_fdce_C_D) 0.077 37.278 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675] ------------------------------------------------------------------- required time 37.278 arrival time -23.959 ------------------------------------------------------------------- slack 13.319 Slack (MET) : 13.319ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.482ns (logic 1.594ns (6.019%) route 24.888ns (93.981%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.209ns = ( 37.791 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.909 21.049 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X125Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[675]_i_3/I3 SLICE_X125Y147 LUT4 (Prop_lut4_I3_O) 0.150 21.199 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[675]_i_3/O net (fo=1, routed) 1.702 22.901 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[675] SLICE_X141Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[675]_i_2/I0 SLICE_X141Y156 LUT6 (Prop_lut6_I0_O) 0.326 23.227 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[675]_i_2/O net (fo=1, routed) 0.609 23.835 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[414] SLICE_X142Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[675]_i_1/I1 SLICE_X142Y156 LUT3 (Prop_lut3_I1_O) 0.124 23.959 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[675]_i_1/O net (fo=1, routed) 0.000 23.959 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[675] SLICE_X142Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.466 37.791 clock pessimism -0.514 37.278 clock uncertainty -0.077 37.201 SLICE_X142Y156 FDCE (Setup_fdce_C_D) 0.077 37.278 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675] ------------------------------------------------------------------- required time 37.278 arrival time -23.959 ------------------------------------------------------------------- slack 13.319 Slack (MET) : 13.335ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.094ns (logic 1.164ns (4.461%) route 24.930ns (95.539%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.970 23.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y126 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347] ------------------------------------------------------------------- required time 36.907 arrival time -23.572 ------------------------------------------------------------------- slack 13.335 Slack (MET) : 13.335ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.094ns (logic 1.164ns (4.461%) route 24.930ns (95.539%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.970 23.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y126 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y126 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347] ------------------------------------------------------------------- required time 36.907 arrival time -23.572 ------------------------------------------------------------------- slack 13.335 Slack (MET) : 13.375ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.019ns (logic 1.164ns (4.474%) route 24.855ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.895 23.497 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X143Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X143Y128 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336] ------------------------------------------------------------------- required time 36.872 arrival time -23.497 ------------------------------------------------------------------- slack 13.375 Slack (MET) : 13.375ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.019ns (logic 1.164ns (4.474%) route 24.855ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.895 23.497 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X143Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X143Y128 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336] ------------------------------------------------------------------- required time 36.872 arrival time -23.497 ------------------------------------------------------------------- slack 13.375 Slack (MET) : 13.383ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.512ns (logic 1.562ns (5.892%) route 24.950ns (94.108%)) Logic Levels: 5 (LUT3=1 LUT4=1 LUT5=1 LUT6=2) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.193ns = ( 37.807 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.287 21.427 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X132Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1112]_i_4/I3 SLICE_X132Y142 LUT4 (Prop_lut4_I3_O) 0.116 21.543 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1112]_i_4/O net (fo=1, routed) 0.954 22.497 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[1112] SLICE_X138Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[1112]_i_3/I0 SLICE_X138Y142 LUT6 (Prop_lut6_I0_O) 0.328 22.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[1112]_i_3/O net (fo=1, routed) 1.041 23.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[851] SLICE_X142Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1112]_i_1/I3 SLICE_X142Y142 LUT5 (Prop_lut5_I3_O) 0.124 23.990 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1112]_i_1/O net (fo=1, routed) 0.000 23.990 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[1112] SLICE_X142Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.482 37.807 clock pessimism -0.435 37.372 clock uncertainty -0.077 37.296 SLICE_X142Y142 FDCE (Setup_fdce_C_D) 0.077 37.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112] ------------------------------------------------------------------- required time 37.373 arrival time -23.990 ------------------------------------------------------------------- slack 13.383 Slack (MET) : 13.383ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.512ns (logic 1.562ns (5.892%) route 24.950ns (94.108%)) Logic Levels: 5 (LUT3=1 LUT4=1 LUT5=1 LUT6=2) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.193ns = ( 37.807 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.287 21.427 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X132Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1112]_i_4/I3 SLICE_X132Y142 LUT4 (Prop_lut4_I3_O) 0.116 21.543 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1112]_i_4/O net (fo=1, routed) 0.954 22.497 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[1112] SLICE_X138Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[1112]_i_3/I0 SLICE_X138Y142 LUT6 (Prop_lut6_I0_O) 0.328 22.825 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[1112]_i_3/O net (fo=1, routed) 1.041 23.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[851] SLICE_X142Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1112]_i_1/I3 SLICE_X142Y142 LUT5 (Prop_lut5_I3_O) 0.124 23.990 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1112]_i_1/O net (fo=1, routed) 0.000 23.990 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[1112] SLICE_X142Y142 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.482 37.807 clock pessimism -0.435 37.372 clock uncertainty -0.077 37.296 SLICE_X142Y142 FDCE (Setup_fdce_C_D) 0.077 37.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112] ------------------------------------------------------------------- required time 37.373 arrival time -23.990 ------------------------------------------------------------------- slack 13.383 Slack (MET) : 13.417ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.979ns (logic 1.164ns (4.481%) route 24.815ns (95.519%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.855 23.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X145Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X145Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414] ------------------------------------------------------------------- required time 36.874 arrival time -23.456 ------------------------------------------------------------------- slack 13.417 Slack (MET) : 13.417ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.979ns (logic 1.164ns (4.481%) route 24.815ns (95.519%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.855 23.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X145Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X145Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414] ------------------------------------------------------------------- required time 36.874 arrival time -23.456 ------------------------------------------------------------------- slack 13.417 Slack (MET) : 13.417ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.979ns (logic 1.164ns (4.481%) route 24.815ns (95.519%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.855 23.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X145Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X145Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576] ------------------------------------------------------------------- required time 36.874 arrival time -23.456 ------------------------------------------------------------------- slack 13.417 Slack (MET) : 13.417ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.979ns (logic 1.164ns (4.481%) route 24.815ns (95.519%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.855 23.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X145Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X145Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576] ------------------------------------------------------------------- required time 36.874 arrival time -23.456 ------------------------------------------------------------------- slack 13.417 Slack (MET) : 13.419ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.010ns (logic 1.164ns (4.475%) route 24.846ns (95.525%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.885 23.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X148Y124 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X148Y124 FDCE (Setup_fdce_C_CE) -0.377 36.906 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513] ------------------------------------------------------------------- required time 36.906 arrival time -23.487 ------------------------------------------------------------------- slack 13.419 Slack (MET) : 13.419ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.010ns (logic 1.164ns (4.475%) route 24.846ns (95.525%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.885 23.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X148Y124 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X148Y124 FDCE (Setup_fdce_C_CE) -0.377 36.906 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513] ------------------------------------------------------------------- required time 36.906 arrival time -23.487 ------------------------------------------------------------------- slack 13.419 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.444ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.985ns (logic 1.164ns (4.480%) route 24.821ns (95.520%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.860 23.462 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X140Y127 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X140Y127 FDCE (Setup_fdce_C_CE) -0.377 36.906 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439] ------------------------------------------------------------------- required time 36.906 arrival time -23.462 ------------------------------------------------------------------- slack 13.444 Slack (MET) : 13.444ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.985ns (logic 1.164ns (4.480%) route 24.821ns (95.520%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.860 23.462 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X140Y127 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X140Y127 FDCE (Setup_fdce_C_CE) -0.377 36.906 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439] ------------------------------------------------------------------- required time 36.906 arrival time -23.462 ------------------------------------------------------------------- slack 13.444 Slack (MET) : 13.445ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.951ns (logic 1.164ns (4.485%) route 24.787ns (95.515%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.827 23.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X147Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X147Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416] ------------------------------------------------------------------- required time 36.874 arrival time -23.429 ------------------------------------------------------------------- slack 13.445 Slack (MET) : 13.445ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.951ns (logic 1.164ns (4.485%) route 24.787ns (95.515%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.827 23.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X147Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X147Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416] ------------------------------------------------------------------- required time 36.874 arrival time -23.429 ------------------------------------------------------------------- slack 13.445 Slack (MET) : 13.445ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.951ns (logic 1.164ns (4.485%) route 24.787ns (95.515%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.827 23.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X147Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X147Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480] ------------------------------------------------------------------- required time 36.874 arrival time -23.429 ------------------------------------------------------------------- slack 13.445 Slack (MET) : 13.445ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.951ns (logic 1.164ns (4.485%) route 24.787ns (95.515%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.827 23.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X147Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X147Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480] ------------------------------------------------------------------- required time 36.874 arrival time -23.429 ------------------------------------------------------------------- slack 13.445 Slack (MET) : 13.477ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.957ns (logic 1.392ns (5.363%) route 24.565ns (94.637%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.434 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402] ------------------------------------------------------------------- required time 36.911 arrival time -23.434 ------------------------------------------------------------------- slack 13.477 Slack (MET) : 13.477ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.957ns (logic 1.392ns (5.363%) route 24.565ns (94.637%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.434 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402] ------------------------------------------------------------------- required time 36.911 arrival time -23.434 ------------------------------------------------------------------- slack 13.477 Slack (MET) : 13.477ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.957ns (logic 1.392ns (5.363%) route 24.565ns (94.637%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.434 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466] ------------------------------------------------------------------- required time 36.911 arrival time -23.434 ------------------------------------------------------------------- slack 13.477 Slack (MET) : 13.477ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.957ns (logic 1.392ns (5.363%) route 24.565ns (94.637%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.434 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466] ------------------------------------------------------------------- required time 36.911 arrival time -23.434 ------------------------------------------------------------------- slack 13.477 Slack (MET) : 13.504ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.930ns (logic 1.164ns (4.489%) route 24.766ns (95.511%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.805 23.407 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X144Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X144Y129 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418] ------------------------------------------------------------------- required time 36.911 arrival time -23.407 ------------------------------------------------------------------- slack 13.504 Slack (MET) : 13.504ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.930ns (logic 1.164ns (4.489%) route 24.766ns (95.511%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.805 23.407 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X144Y129 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X144Y129 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418] ------------------------------------------------------------------- required time 36.911 arrival time -23.407 ------------------------------------------------------------------- slack 13.504 Slack (MET) : 13.523ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.869ns (logic 1.392ns (5.381%) route 24.477ns (94.619%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.028 23.347 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X151Y124 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X151Y124 FDCE (Setup_fdce_C_CE) -0.413 36.870 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383] ------------------------------------------------------------------- required time 36.870 arrival time -23.347 ------------------------------------------------------------------- slack 13.523 Slack (MET) : 13.523ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.869ns (logic 1.392ns (5.381%) route 24.477ns (94.619%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.028 23.347 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X151Y124 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X151Y124 FDCE (Setup_fdce_C_CE) -0.413 36.870 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383] ------------------------------------------------------------------- required time 36.870 arrival time -23.347 ------------------------------------------------------------------- slack 13.523 Slack (MET) : 13.528ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.208ns (logic 1.620ns (6.181%) route 24.588ns (93.819%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.271ns = ( 37.729 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 8.784 19.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X105Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[598]_i_3/I3 SLICE_X105Y139 LUT4 (Prop_lut4_I3_O) 0.150 20.074 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[598]_i_3/O net (fo=1, routed) 1.791 21.864 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[598] SLICE_X115Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[598]_i_2/I0 SLICE_X115Y158 LUT6 (Prop_lut6_I0_O) 0.326 22.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[598]_i_2/O net (fo=1, routed) 1.346 23.536 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[337] SLICE_X133Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[598]_i_1/I1 SLICE_X133Y151 LUT3 (Prop_lut3_I1_O) 0.150 23.686 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[598]_i_1/O net (fo=1, routed) 0.000 23.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[598] SLICE_X133Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.404 37.729 clock pessimism -0.514 37.216 clock uncertainty -0.077 37.139 SLICE_X133Y151 FDCE (Setup_fdce_C_D) 0.075 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598] ------------------------------------------------------------------- required time 37.214 arrival time -23.686 ------------------------------------------------------------------- slack 13.528 Slack (MET) : 13.528ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.208ns (logic 1.620ns (6.181%) route 24.588ns (93.819%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.271ns = ( 37.729 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 8.784 19.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X105Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[598]_i_3/I3 SLICE_X105Y139 LUT4 (Prop_lut4_I3_O) 0.150 20.074 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[598]_i_3/O net (fo=1, routed) 1.791 21.864 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[598] SLICE_X115Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[598]_i_2/I0 SLICE_X115Y158 LUT6 (Prop_lut6_I0_O) 0.326 22.190 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[598]_i_2/O net (fo=1, routed) 1.346 23.536 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[337] SLICE_X133Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[598]_i_1/I1 SLICE_X133Y151 LUT3 (Prop_lut3_I1_O) 0.150 23.686 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[598]_i_1/O net (fo=1, routed) 0.000 23.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[598] SLICE_X133Y151 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.404 37.729 clock pessimism -0.514 37.216 clock uncertainty -0.077 37.139 SLICE_X133Y151 FDCE (Setup_fdce_C_D) 0.075 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598] ------------------------------------------------------------------- required time 37.214 arrival time -23.686 ------------------------------------------------------------------- slack 13.528 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.566ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.763ns (logic 1.164ns (4.518%) route 24.599ns (95.482%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.181ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.269ns = ( 37.731 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.639 23.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X138Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.406 37.731 clock pessimism -0.435 37.296 clock uncertainty -0.077 37.220 SLICE_X138Y126 FDCE (Setup_fdce_C_CE) -0.413 36.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413] ------------------------------------------------------------------- required time 36.807 arrival time -23.240 ------------------------------------------------------------------- slack 13.566 Slack (MET) : 13.566ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.763ns (logic 1.164ns (4.518%) route 24.599ns (95.482%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.181ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.269ns = ( 37.731 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.639 23.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X138Y126 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.406 37.731 clock pessimism -0.435 37.296 clock uncertainty -0.077 37.220 SLICE_X138Y126 FDCE (Setup_fdce_C_CE) -0.413 36.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413] ------------------------------------------------------------------- required time 36.807 arrival time -23.240 ------------------------------------------------------------------- slack 13.566