diff --git a/.gitignore b/.gitignore
index bca1624..c269dce 100644
--- a/.gitignore
+++ b/.gitignore
@@ -4,10 +4,7 @@
fpga/.Xil/
fpga/project/
*.xpr
-*.xci
-*.xcix
-*.xdc
-*.bd
+*.xpr
*.dcp
*.jou
*.log
diff --git a/fpga/constraints/soc.xdc b/fpga/constraints/soc.xdc
new file mode 100644
index 0000000..65c8237
--- /dev/null
+++ b/fpga/constraints/soc.xdc
@@ -0,0 +1,265 @@
+
+#clock
+set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS33} [get_ports clk]
+create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk]
+
+#reset
+set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports reset]
+
+#uart
+set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN H18} [get_ports UART_TX]
+set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN J20} [get_ports UART_RX]
+
+#Digital Video
+set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS33} [get_ports video_clk]
+set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS33} [get_ports {video_red[2]}]
+set_property -dict {PACKAGE_PIN F24 IOSTANDARD LVCMOS33} [get_ports {video_red[1]}]
+set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS33} [get_ports {video_red[0]}]
+set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVCMOS33} [get_ports {video_green[2]}]
+set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS33} [get_ports {video_green[1]}]
+set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS33} [get_ports {video_green[0]}]
+set_property -dict {PACKAGE_PIN D25 IOSTANDARD LVCMOS33} [get_ports {video_blue[1]}]
+set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS33} [get_ports {video_blue[0]}]
+set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS33} [get_ports video_hsync]
+set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS33} [get_ports video_vsync]
+set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS33} [get_ports video_de]
+
+#LEDS
+set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS33} [get_ports {leds[0]}]
+set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports {leds[1]}]
+set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS33} [get_ports {leds[2]}]
+set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS33} [get_ports {leds[3]}]
+set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports {leds[4]}]
+set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS33} [get_ports {leds[5]}]
+set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33} [get_ports {leds[6]}]
+set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports {leds[7]}]
+set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS33} [get_ports {leds[8]}]
+set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS33} [get_ports {leds[9]}]
+set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS33} [get_ports {leds[10]}]
+set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {leds[11]}]
+set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports {leds[12]}]
+set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS33} [get_ports {leds[13]}]
+set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports {leds[14]}]
+set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33} [get_ports {leds[15]}]
+
+#DPY0
+set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33} [get_ports {dpy0[0]}]
+set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {dpy0[1]}]
+set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS33} [get_ports {dpy0[2]}]
+set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33} [get_ports {dpy0[3]}]
+set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {dpy0[4]}]
+set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS33} [get_ports {dpy0[5]}]
+set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {dpy0[6]}]
+set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports {dpy0[7]}]
+
+#DPY1
+set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports {dpy1[0]}]
+set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33} [get_ports {dpy1[1]}]
+set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {dpy1[2]}]
+set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS33} [get_ports {dpy1[3]}]
+set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {dpy1[4]}]
+set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {dpy1[5]}]
+set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {dpy1[6]}]
+set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {dpy1[7]}]
+
+#DIP_SW
+set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[0]}]
+set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[1]}]
+set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[2]}]
+set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[3]}]
+set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[4]}]
+set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[5]}]
+set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[6]}]
+set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports {dip_sw[7]}]
+set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports {dip_sw[8]}]
+set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS33} [get_ports {dip_sw[9]}]
+set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS33} [get_ports {dip_sw[10]}]
+set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS33} [get_ports {dip_sw[11]}]
+set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[12]}]
+set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[13]}]
+set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[14]}]
+set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[15]}]
+set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[16]}]
+set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[17]}]
+set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[18]}]
+set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[19]}]
+set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[20]}]
+set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[21]}]
+set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS33} [get_ports {dip_sw[22]}]
+set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[23]}]
+set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[24]}]
+set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[25]}]
+set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[26]}]
+set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[27]}]
+set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[28]}]
+set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[29]}]
+set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports {dip_sw[30]}]
+set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[31]}]
+
+#Touch Button
+set_property -dict {PACKAGE_PIN T2 IOSTANDARD LVCMOS33} [get_ports {touch_btn[0]}]
+set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {touch_btn[1]}]
+set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {touch_btn[2]}]
+set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {touch_btn[3]}]
+
+#SRAM
+set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[0]}]
+set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[1]}]
+set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[2]}]
+set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[3]}]
+set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[4]}]
+set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[5]}]
+set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[6]}]
+set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[7]}]
+set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[8]}]
+set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[9]}]
+set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[10]}]
+set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[11]}]
+set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[12]}]
+set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[13]}]
+set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[14]}]
+set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[15]}]
+set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[16]}]
+set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[17]}]
+set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[18]}]
+set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[19]}]
+set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[1]}]
+set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[0]}]
+set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[3]}]
+set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[2]}]
+set_property -dict {PACKAGE_PIN L24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[0]}]
+set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[1]}]
+set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[2]}]
+set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[3]}]
+set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[4]}]
+set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[5]}]
+set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[6]}]
+set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[7]}]
+set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[8]}]
+set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[9]}]
+set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[10]}]
+set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[11]}]
+set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[12]}]
+set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[13]}]
+set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[14]}]
+set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[15]}]
+set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[16]}]
+set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[17]}]
+set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[18]}]
+set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[19]}]
+set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[20]}]
+set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[21]}]
+set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[22]}]
+set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[23]}]
+set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[24]}]
+set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[25]}]
+set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[26]}]
+set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[27]}]
+set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[28]}]
+set_property -dict {PACKAGE_PIN N23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[29]}]
+set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[30]}]
+set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[31]}]
+set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports base_ram_ce_n]
+set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports base_ram_oe_n]
+set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports base_ram_we_n]
+
+set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[0]}]
+set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[1]}]
+set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[2]}]
+set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[3]}]
+set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[4]}]
+set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[5]}]
+set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[6]}]
+set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[7]}]
+set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[8]}]
+set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[9]}]
+set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[10]}]
+set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[11]}]
+set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[12]}]
+set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[13]}]
+set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[14]}]
+set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[15]}]
+set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[16]}]
+set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[17]}]
+set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[18]}]
+set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[19]}]
+set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[1]}]
+set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[0]}]
+set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[3]}]
+set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[2]}]
+set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[0]}]
+set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[1]}]
+set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[2]}]
+set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[3]}]
+set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[4]}]
+set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[5]}]
+set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[6]}]
+set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[7]}]
+set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[8]}]
+set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[9]}]
+set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[10]}]
+set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[11]}]
+set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[12]}]
+set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[13]}]
+set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[14]}]
+set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[15]}]
+set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[16]}]
+set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[17]}]
+set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[18]}]
+set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[19]}]
+set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[20]}]
+set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[21]}]
+set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[22]}]
+set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[23]}]
+set_property -dict {PACKAGE_PIN AD17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[24]}]
+set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[25]}]
+set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[26]}]
+set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[27]}]
+set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[28]}]
+set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[29]}]
+set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[30]}]
+set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[31]}]
+set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS33} [get_ports ext_ram_ce_n]
+set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports ext_ram_oe_n]
+set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS33} [get_ports ext_ram_we_n]
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+create_generated_clock -name cpu_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0]
+create_generated_clock -name sys_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1]
+
+set_clock_groups -asynchronous -group [get_clocks cpu_clk] -group [get_clocks sys_clk]
+
+set_input_delay -clock sys_clk -max 3 [get_ports {base_ram_data[*]}]
+set_input_delay -clock sys_clk -min 2 [get_ports {base_ram_data[*]}]
+
+set_output_delay -clock sys_clk -max 0.3 [get_ports {base_ram_data[*]}]
+set_output_delay -clock sys_clk -min -0.3 [get_ports {base_ram_data[*]}]
+set_output_delay -clock sys_clk -max 0.3 [get_ports {base_ram_addr[*]}]
+set_output_delay -clock sys_clk -min -0.3 [get_ports {base_ram_addr[*]}]
+set_output_delay -clock sys_clk -max 0.3 [get_ports {base_ram_be_n[*]}]
+set_output_delay -clock sys_clk -min -0.3 [get_ports {base_ram_be_n[*]}]
+set_output_delay -clock sys_clk -max 0.3 [get_ports base_ram_ce_n]
+set_output_delay -clock sys_clk -min -0.3 [get_ports base_ram_ce_n]
+set_output_delay -clock sys_clk -max 0.3 [get_ports base_ram_oe_n]
+set_output_delay -clock sys_clk -min -0.3 [get_ports base_ram_oe_n]
+set_output_delay -clock sys_clk -max 0.3 [get_ports base_ram_we_n]
+set_output_delay -clock sys_clk -min -0.3 [get_ports base_ram_we_n]
+
+set_input_delay -clock sys_clk -max 3 [get_ports {ext_ram_data[*]}]
+set_input_delay -clock sys_clk -min 2 [get_ports {ext_ram_data[*]}]
+
+set_output_delay -clock sys_clk -max 0.3 [get_ports {ext_ram_data[*]}]
+set_output_delay -clock sys_clk -min -0.3 [get_ports {ext_ram_data[*]}]
+set_output_delay -clock sys_clk -max 0.3 [get_ports {ext_ram_addr[*]}]
+set_output_delay -clock sys_clk -min -0.3 [get_ports {ext_ram_addr[*]}]
+set_output_delay -clock sys_clk -max 0.3 [get_ports {ext_ram_be_n[*]}]
+set_output_delay -clock sys_clk -min -0.3 [get_ports {ext_ram_be_n[*]}]
+set_output_delay -clock sys_clk -max 0.3 [get_ports ext_ram_ce_n]
+set_output_delay -clock sys_clk -min -0.3 [get_ports ext_ram_ce_n]
+set_output_delay -clock sys_clk -max 0.3 [get_ports ext_ram_oe_n]
+set_output_delay -clock sys_clk -min -0.3 [get_ports ext_ram_oe_n]
+set_output_delay -clock sys_clk -max 0.3 [get_ports ext_ram_we_n]
+set_output_delay -clock sys_clk -min -0.3 [get_ports ext_ram_we_n]
\ No newline at end of file
diff --git a/rtl/ip/PLL_2018_3/clk_pll.xci b/rtl/ip/PLL_2018_3/clk_pll.xci
new file mode 100644
index 0000000..7d955c8
--- /dev/null
+++ b/rtl/ip/PLL_2018_3/clk_pll.xci
@@ -0,0 +1,722 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ clk_pll
+
+
+ false
+ 100000000
+ false
+ 100000000
+ false
+ 100000000
+ false
+ 100000000
+
+
+
+ 100000000
+ 0
+ 0.000
+
+
+
+ 100000000
+ 0
+ 0.000
+
+
+
+ 100000000
+ 0
+ 0.000
+ 1
+ LEVEL_HIGH
+
+
+
+ 100000000
+ 0
+ 0.000
+ 0
+ 0
+
+ 100000000
+ 0
+ 0.000
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 100000000
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0.000
+ AXI4LITE
+ READ_WRITE
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ MMCM
+ cddcdone
+ cddcreq
+ 0000
+ 0000
+ clkfb_in_n
+ clkfb_in
+ clkfb_in_p
+ SINGLE
+ clkfb_out_n
+ clkfb_out
+ clkfb_out_p
+ clkfb_stopped
+ 200.0
+ 100.0
+ 0000
+ 0000
+ 32.979
+ 0000
+ 0000
+ 50.000
+ BUFG
+ 50.0
+ false
+ 32.979
+ 0.000
+ 50.000
+ 33.000
+ 0.000
+ 1
+ 0000
+ 0000
+ 100.000
+ BUFG
+ 50.0
+ false
+ 50.000
+ 0.000
+ 50.000
+ 50.000
+ 0.000
+ 1
+ 1
+ 0000
+ 0000
+ 100.000
+ BUFG
+ 50.000
+ false
+ 100.000
+ 0.000
+ 50.000
+ 100.000
+ 0.000
+ 1
+ 0
+ 0000
+ 0000
+ 100.000
+ BUFG
+ 50.000
+ false
+ 100.000
+ 0.000
+ 50.000
+ 100.000
+ 0.000
+ 1
+ 0
+ 0000
+ 0000
+ 100.000
+ BUFG
+ 50.000
+ false
+ 100.000
+ 0.000
+ 50.000
+ 100.000
+ 0.000
+ 1
+ 0
+ 0000
+ 0000
+ 100.000
+ BUFG
+ 50.000
+ false
+ 100.000
+ 0.000
+ 50.000
+ 100.000
+ 0.000
+ 1
+ 0
+ BUFG
+ 50.000
+ false
+ 100.000
+ 0.000
+ 50.000
+ 100.000
+ 0.000
+ 1
+ 0
+ VCO
+ clk_in_sel
+ cpu_clk
+ sys_clk
+ clk_out3
+ clk_out4
+ clk_out5
+ clk_out6
+ clk_out7
+ CLK_VALID
+ NA
+ daddr
+ dclk
+ den
+ din
+ 0000
+ 1
+ 0.66
+ 0.33
+ 0.33
+ 0.33
+ 0.33
+ 0.33
+ dout
+ drdy
+ dwe
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ FDBK_AUTO
+ 0000
+ 0000
+ 0
+ Input Clock Freq (MHz) Input Jitter (UI)
+ __primary__________50.000____________0.010
+ no_secondary_input_clock
+ input_clk_stopped
+ 0
+ Units_MHz
+ No_Jitter
+ locked
+ 0000
+ 0000
+ 0000
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ OPTIMIZED
+ 31.000
+ 0.000
+ FALSE
+ 20.000
+ 10.0
+ 47.000
+ 0.500
+ 0.000
+ FALSE
+ 31
+ 0.500
+ 0.000
+ FALSE
+ 1
+ 0.500
+ 0.000
+ FALSE
+ 1
+ 0.500
+ 0.000
+ FALSE
+ FALSE
+ 1
+ 0.500
+ 0.000
+ FALSE
+ 1
+ 0.500
+ 0.000
+ FALSE
+ 1
+ 0.500
+ 0.000
+ FALSE
+ FALSE
+ ZHOLD
+ 1
+ None
+ 0.010
+ 0.010
+ FALSE
+ 2
+ Output Output Phase Duty Cycle Pk-to-Pk Phase
+ Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+ _cpu_clk____32.979______0.000______50.0______130.093____123.600
+ _sys_clk____50.000______0.000______50.0______122.035____123.600
+ no_CLK_OUT3_output
+ no_CLK_OUT4_output
+ no_CLK_OUT5_output
+ no_CLK_OUT6_output
+ no_CLK_OUT7_output
+ 0
+ 0
+ WAVEFORM
+ UNKNOWN
+ false
+ false
+ false
+ false
+ false
+ OPTIMIZED
+ 1
+ 0.000
+ 1.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ CLKFBOUT
+ SYSTEM_SYNCHRONOUS
+ 1
+ No notes
+ 0.010
+ power_down
+ 0000
+ 1
+ clk_in1
+ PLL
+ AUTO
+ 50.000
+ 0.010
+ 10.000
+ Single_ended_clock_capable_pin
+ psclk
+ psdone
+ psen
+ psincdec
+ 100.0
+ 1
+ resetn
+ 100.000
+ 0.010
+ 10.000
+ clk_in2
+ Single_ended_clock_capable_pin
+ CENTER_HIGH
+ 4000
+ 0.004
+ STATUS
+ 11
+ 32
+ 100.0
+ 100.0
+ 100.0
+ 100.0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ clk_pll
+ MMCM
+ false
+ empty
+ cddcdone
+ cddcreq
+ clkfb_in_n
+ clkfb_in
+ clkfb_in_p
+ SINGLE
+ clkfb_out_n
+ clkfb_out
+ clkfb_out_p
+ clkfb_stopped
+ 200.0
+ 0.010
+ 100.0
+ 0.010
+ BUFG
+ 130.093
+ false
+ 123.600
+ 50.000
+ 33.000
+ 0.000
+ 1
+ true
+ BUFG
+ 122.035
+ false
+ 123.600
+ 50.000
+ 50.000
+ 0.000
+ 1
+ true
+ BUFG
+ 0.0
+ false
+ 0.0
+ 50.000
+ 100.000
+ 0.000
+ 1
+ false
+ BUFG
+ 0.0
+ false
+ 0.0
+ 50.000
+ 100.000
+ 0.000
+ 1
+ false
+ BUFG
+ 0.0
+ false
+ 0.0
+ 50.000
+ 100.000
+ 0.000
+ 1
+ false
+ BUFG
+ 0.0
+ false
+ 0.0
+ 50.000
+ 100.000
+ 0.000
+ 1
+ false
+ BUFG
+ 0.0
+ false
+ 0.0
+ 50.000
+ 100.000
+ 0.000
+ 1
+ false
+ 600.000
+ Custom
+ Custom
+ clk_in_sel
+ cpu_clk
+ false
+ sys_clk
+ false
+ clk_out3
+ false
+ clk_out4
+ false
+ clk_out5
+ false
+ clk_out6
+ false
+ clk_out7
+ false
+ CLK_VALID
+ auto
+ clk_pll
+ daddr
+ dclk
+ den
+ Custom
+ Custom
+ din
+ dout
+ drdy
+ dwe
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ FDBK_AUTO
+ input_clk_stopped
+ frequency
+ Enable_AXI
+ Units_MHz
+ Units_UI
+ UI
+ No_Jitter
+ locked
+ OPTIMIZED
+ 31
+ 0.000
+ false
+ 20.000
+ 10.0
+ 47
+ 0.500
+ 0.000
+ false
+ 31
+ 0.500
+ 0.000
+ false
+ 1
+ 0.500
+ 0.000
+ false
+ 1
+ 0.500
+ 0.000
+ false
+ false
+ 1
+ 0.500
+ 0.000
+ false
+ 1
+ 0.500
+ 0.000
+ false
+ 1
+ 0.500
+ 0.000
+ false
+ false
+ ZHOLD
+ 1
+ None
+ 0.010
+ 0.010
+ false
+ 2
+ false
+ false
+ WAVEFORM
+ false
+ UNKNOWN
+ OPTIMIZED
+ 4
+ 0.000
+ 10.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ CLKFBOUT
+ SYSTEM_SYNCHRONOUS
+ 1
+ None
+ 0.010
+ power_down
+ 1
+ clk_in1
+ PLL
+ mmcm_adv
+ 50.000
+ 0.010
+ 10.000
+ Single_ended_clock_capable_pin
+ psclk
+ psdone
+ psen
+ psincdec
+ 100.0
+ REL_PRIMARY
+ Custom
+ resetn
+ ACTIVE_LOW
+ 100.000
+ 0.010
+ 10.000
+ clk_in2
+ Single_ended_clock_capable_pin
+ CENTER_HIGH
+ 250
+ 0.004
+ STATUS
+ empty
+ 100.0
+ 100.0
+ 100.0
+ 100.0
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ false
+ false
+ true
+ false
+ false
+ false
+ true
+ false
+ true
+ false
+ false
+ false
+ artix7
+
+
+ xc7a200t
+ fbg676
+ VERILOG
+
+ MIXED
+ -1
+
+ TRUE
+ TRUE
+ IP_Flow
+ 2
+ TRUE
+ ../../../fpga/project/ipgen/clk_pll
+
+ ../../../fpga/project/ipgen/clk_pll
+ 2018.3
+ OUT_OF_CONTEXT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/rtl/ip/PLL_2019_2/clk_pll.xci b/rtl/ip/PLL_2019_2/clk_pll.xci
new file mode 100644
index 0000000..27c681d
--- /dev/null
+++ b/rtl/ip/PLL_2019_2/clk_pll.xci
@@ -0,0 +1,731 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ clk_pll
+
+
+ false
+ 100000000
+ false
+ 100000000
+ false
+ 100000000
+ false
+ 100000000
+
+
+
+ 100000000
+ 0
+ 0.000
+
+
+
+ 100000000
+ 0
+ 0.000
+
+
+
+ 100000000
+ 0
+ 0.000
+ 1
+ LEVEL_HIGH
+
+
+
+ 100000000
+ 0
+ 0.000
+ 0
+ 0
+
+ 100000000
+ 0
+ 0.000
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 100000000
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0.000
+ AXI4LITE
+ READ_WRITE
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ MMCM
+ cddcdone
+ cddcreq
+ 0000
+ 0000
+ clkfb_in_n
+ clkfb_in
+ clkfb_in_p
+ SINGLE
+ clkfb_out_n
+ clkfb_out
+ clkfb_out_p
+ clkfb_stopped
+ 200.0
+ 100.0
+ 0000
+ 0000
+ 32.97872
+ 0000
+ 0000
+ 50.00000
+ BUFG
+ 50.0
+ false
+ 32.97872
+ 0.000
+ 50.000
+ 33.000
+ 0.000
+ 1
+ 0000
+ 0000
+ 100.000
+ BUFG
+ 50.0
+ false
+ 50.00000
+ 0.000
+ 50.000
+ 50.000
+ 0.000
+ 1
+ 1
+ 0000
+ 0000
+ 100.000
+ BUFG
+ 50.000
+ false
+ 100.000
+ 0.000
+ 50.000
+ 100.000
+ 0.000
+ 1
+ 0
+ 0000
+ 0000
+ 100.000
+ BUFG
+ 50.000
+ false
+ 100.000
+ 0.000
+ 50.000
+ 100.000
+ 0.000
+ 1
+ 0
+ 0000
+ 0000
+ 100.000
+ BUFG
+ 50.000
+ false
+ 100.000
+ 0.000
+ 50.000
+ 100.000
+ 0.000
+ 1
+ 0
+ 0000
+ 0000
+ 100.000
+ BUFG
+ 50.000
+ false
+ 100.000
+ 0.000
+ 50.000
+ 100.000
+ 0.000
+ 1
+ 0
+ BUFG
+ 50.000
+ false
+ 100.000
+ 0.000
+ 50.000
+ 100.000
+ 0.000
+ 1
+ 0
+ VCO
+ clk_in_sel
+ cpu_clk
+ sys_clk
+ clk_out3
+ clk_out4
+ clk_out5
+ clk_out6
+ clk_out7
+ CLK_VALID
+ NA
+ daddr
+ dclk
+ den
+ din
+ 0000
+ 1
+ 0.66
+ 0.33
+ 0.33
+ 0.33
+ 0.33
+ 0.33
+ dout
+ drdy
+ dwe
+ 42.000
+ 1.000
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ FDBK_AUTO
+ 0000
+ 0000
+ 0
+ Input Clock Freq (MHz) Input Jitter (UI)
+ __primary__________50.000____________0.010
+ no_secondary_input_clock
+ input_clk_stopped
+ 0
+ Units_MHz
+ No_Jitter
+ locked
+ 0000
+ 0000
+ 0000
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ OPTIMIZED
+ 31.000
+ 0.000
+ FALSE
+ 20.000
+ 10.0
+ 47.000
+ 0.500
+ 0.000
+ FALSE
+ 31
+ 0.500
+ 0.000
+ FALSE
+ 1
+ 0.500
+ 0.000
+ FALSE
+ 1
+ 0.500
+ 0.000
+ FALSE
+ FALSE
+ 1
+ 0.500
+ 0.000
+ FALSE
+ 1
+ 0.500
+ 0.000
+ FALSE
+ 1
+ 0.500
+ 0.000
+ FALSE
+ FALSE
+ ZHOLD
+ 1
+ None
+ 0.010
+ 0.010
+ FALSE
+ 64.000
+ 2.000
+ 2
+ Output Output Phase Duty Cycle Pk-to-Pk Phase
+ Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+ _cpu_clk__32.97872______0.000______50.0______130.093____123.600
+ _sys_clk__50.00000______0.000______50.0______122.035____123.600
+ no_CLK_OUT3_output
+ no_CLK_OUT4_output
+ no_CLK_OUT5_output
+ no_CLK_OUT6_output
+ no_CLK_OUT7_output
+ 0
+ 0
+ 128.000
+ 1.000
+ WAVEFORM
+ UNKNOWN
+ false
+ false
+ false
+ false
+ false
+ OPTIMIZED
+ 1
+ 0.000
+ 1.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ CLKFBOUT
+ SYSTEM_SYNCHRONOUS
+ 1
+ No notes
+ 0.010
+ power_down
+ 0000
+ 1
+ clk_in1
+ PLL
+ AUTO
+ 50.000
+ 0.010
+ 10.000
+ Single_ended_clock_capable_pin
+ psclk
+ psdone
+ psen
+ psincdec
+ 100.0
+ 1
+ resetn
+ 100.000
+ 0.010
+ 10.000
+ clk_in2
+ Single_ended_clock_capable_pin
+ CENTER_HIGH
+ 4000
+ 0.004
+ STATUS
+ 11
+ 32
+ 100.0
+ 100.0
+ 100.0
+ 100.0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 1600.000
+ 800.000
+ clk_pll
+ MMCM
+ false
+ empty
+ cddcdone
+ cddcreq
+ clkfb_in_n
+ clkfb_in
+ clkfb_in_p
+ SINGLE
+ clkfb_out_n
+ clkfb_out
+ clkfb_out_p
+ clkfb_stopped
+ 200.0
+ 0.010
+ 100.0
+ 0.010
+ BUFG
+ 130.093
+ false
+ 123.600
+ 50.000
+ 33.000
+ 0.000
+ 1
+ true
+ BUFG
+ 122.035
+ false
+ 123.600
+ 50.000
+ 50.000
+ 0.000
+ 1
+ true
+ BUFG
+ 0.0
+ false
+ 0.0
+ 50.000
+ 100.000
+ 0.000
+ 1
+ false
+ BUFG
+ 0.0
+ false
+ 0.0
+ 50.000
+ 100.000
+ 0.000
+ 1
+ false
+ BUFG
+ 0.0
+ false
+ 0.0
+ 50.000
+ 100.000
+ 0.000
+ 1
+ false
+ BUFG
+ 0.0
+ false
+ 0.0
+ 50.000
+ 100.000
+ 0.000
+ 1
+ false
+ BUFG
+ 0.0
+ false
+ 0.0
+ 50.000
+ 100.000
+ 0.000
+ 1
+ false
+ 600.000
+ Custom
+ Custom
+ clk_in_sel
+ cpu_clk
+ false
+ sys_clk
+ false
+ clk_out3
+ false
+ clk_out4
+ false
+ clk_out5
+ false
+ clk_out6
+ false
+ clk_out7
+ false
+ CLK_VALID
+ auto
+ clk_pll
+ daddr
+ dclk
+ den
+ Custom
+ Custom
+ din
+ dout
+ drdy
+ dwe
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ FDBK_AUTO
+ input_clk_stopped
+ frequency
+ Enable_AXI
+ Units_MHz
+ Units_UI
+ UI
+ No_Jitter
+ locked
+ OPTIMIZED
+ 31
+ 0.000
+ false
+ 20.000
+ 10.0
+ 47
+ 0.500
+ 0.000
+ false
+ 31
+ 0.500
+ 0.000
+ false
+ 1
+ 0.500
+ 0.000
+ false
+ 1
+ 0.500
+ 0.000
+ false
+ false
+ 1
+ 0.500
+ 0.000
+ false
+ 1
+ 0.500
+ 0.000
+ false
+ 1
+ 0.500
+ 0.000
+ false
+ false
+ ZHOLD
+ 1
+ None
+ 0.010
+ 0.010
+ false
+ 2
+ false
+ false
+ WAVEFORM
+ false
+ UNKNOWN
+ OPTIMIZED
+ 4
+ 0.000
+ 10.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ 1
+ 0.500
+ 0.000
+ CLKFBOUT
+ SYSTEM_SYNCHRONOUS
+ 1
+ None
+ 0.010
+ power_down
+ 1
+ clk_in1
+ PLL
+ mmcm_adv
+ 50.000
+ 0.010
+ 10.000
+ Single_ended_clock_capable_pin
+ psclk
+ psdone
+ psen
+ psincdec
+ 100.0
+ REL_PRIMARY
+ Custom
+ resetn
+ ACTIVE_LOW
+ 100.000
+ 0.010
+ 10.000
+ clk_in2
+ Single_ended_clock_capable_pin
+ CENTER_HIGH
+ 250
+ 0.004
+ STATUS
+ empty
+ 100.0
+ 100.0
+ 100.0
+ 100.0
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ false
+ false
+ true
+ false
+ false
+ false
+ true
+ false
+ true
+ false
+ false
+ false
+ artix7
+
+
+ xc7a200t
+ fbg676
+ VERILOG
+
+ MIXED
+ -1
+
+
+ TRUE
+ TRUE
+ IP_Flow
+ 4
+ TRUE
+ ../../../fpga/project/ipgen/clk_pll
+
+ ../../../fpga/project/ipgen/clk_pll
+ 2019.2
+ OUT_OF_CONTEXT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v b/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v
deleted file mode 100644
index bf7a3d9..0000000
--- a/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v
+++ /dev/null
@@ -1,224 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Tue Jun 23 00:27:14 2026
-// Host : fedora running 64-bit unknown
-// Command : write_verilog -force -mode funcsim
-// /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v
-// Design : clk_pll
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7a200tfbg676-1
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* NotValidForBitStream *)
-module clk_pll
- (cpu_clk,
- sys_clk,
- resetn,
- locked,
- clk_in1);
- output cpu_clk;
- output sys_clk;
- input resetn;
- output locked;
- input clk_in1;
-
- (* IBUF_LOW_PWR *) wire clk_in1;
- wire cpu_clk;
- wire locked;
- wire resetn;
- wire sys_clk;
-
- clk_pll_clk_pll_clk_wiz inst
- (.clk_in1(clk_in1),
- .cpu_clk(cpu_clk),
- .locked(locked),
- .resetn(resetn),
- .sys_clk(sys_clk));
-endmodule
-
-(* ORIG_REF_NAME = "clk_pll_clk_wiz" *)
-module clk_pll_clk_pll_clk_wiz
- (cpu_clk,
- sys_clk,
- resetn,
- locked,
- clk_in1);
- output cpu_clk;
- output sys_clk;
- input resetn;
- output locked;
- input clk_in1;
-
- wire clk_in1;
- wire clk_in1_clk_pll;
- wire clkfbout_buf_clk_pll;
- wire clkfbout_clk_pll;
- wire cpu_clk;
- wire cpu_clk_clk_pll;
- wire locked;
- wire reset_high;
- wire resetn;
- wire sys_clk;
- wire sys_clk_clk_pll;
- wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
- wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
- wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
- wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
- wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
- wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
-
- (* BOX_TYPE = "PRIMITIVE" *)
- BUFG clkf_buf
- (.I(clkfbout_clk_pll),
- .O(clkfbout_buf_clk_pll));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- IBUF #(
- .IOSTANDARD("DEFAULT"))
- clkin1_ibufg
- (.I(clk_in1),
- .O(clk_in1_clk_pll));
- (* BOX_TYPE = "PRIMITIVE" *)
- BUFG clkout1_buf
- (.I(cpu_clk_clk_pll),
- .O(cpu_clk));
- (* BOX_TYPE = "PRIMITIVE" *)
- BUFG clkout2_buf
- (.I(sys_clk_clk_pll),
- .O(sys_clk));
- (* BOX_TYPE = "PRIMITIVE" *)
- PLLE2_ADV #(
- .BANDWIDTH("OPTIMIZED"),
- .CLKFBOUT_MULT(31),
- .CLKFBOUT_PHASE(0.000000),
- .CLKIN1_PERIOD(20.000000),
- .CLKIN2_PERIOD(0.000000),
- .CLKOUT0_DIVIDE(47),
- .CLKOUT0_DUTY_CYCLE(0.500000),
- .CLKOUT0_PHASE(0.000000),
- .CLKOUT1_DIVIDE(31),
- .CLKOUT1_DUTY_CYCLE(0.500000),
- .CLKOUT1_PHASE(0.000000),
- .CLKOUT2_DIVIDE(1),
- .CLKOUT2_DUTY_CYCLE(0.500000),
- .CLKOUT2_PHASE(0.000000),
- .CLKOUT3_DIVIDE(1),
- .CLKOUT3_DUTY_CYCLE(0.500000),
- .CLKOUT3_PHASE(0.000000),
- .CLKOUT4_DIVIDE(1),
- .CLKOUT4_DUTY_CYCLE(0.500000),
- .CLKOUT4_PHASE(0.000000),
- .CLKOUT5_DIVIDE(1),
- .CLKOUT5_DUTY_CYCLE(0.500000),
- .CLKOUT5_PHASE(0.000000),
- .COMPENSATION("ZHOLD"),
- .DIVCLK_DIVIDE(1),
- .IS_CLKINSEL_INVERTED(1'b0),
- .IS_PWRDWN_INVERTED(1'b0),
- .IS_RST_INVERTED(1'b0),
- .REF_JITTER1(0.010000),
- .REF_JITTER2(0.010000),
- .STARTUP_WAIT("FALSE"))
- plle2_adv_inst
- (.CLKFBIN(clkfbout_buf_clk_pll),
- .CLKFBOUT(clkfbout_clk_pll),
- .CLKIN1(clk_in1_clk_pll),
- .CLKIN2(1'b0),
- .CLKINSEL(1'b1),
- .CLKOUT0(cpu_clk_clk_pll),
- .CLKOUT1(sys_clk_clk_pll),
- .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
- .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
- .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
- .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
- .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .DCLK(1'b0),
- .DEN(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
- .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
- .DWE(1'b0),
- .LOCKED(locked),
- .PWRDWN(1'b0),
- .RST(reset_high));
- LUT1 #(
- .INIT(2'h1))
- plle2_adv_inst_i_1
- (.I0(resetn),
- .O(reset_high));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl b/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl
deleted file mode 100644
index 39ea676..0000000
--- a/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl
+++ /dev/null
@@ -1,170 +0,0 @@
--- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
--- Date : Tue Jun 23 00:27:14 2026
--- Host : fedora running 64-bit unknown
--- Command : write_vhdl -force -mode funcsim
--- /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl
--- Design : clk_pll
--- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--- synthesized. This netlist cannot be used for SDF annotated simulation.
--- Device : xc7a200tfbg676-1
--- --------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity clk_pll_clk_pll_clk_wiz is
- port (
- cpu_clk : out STD_LOGIC;
- sys_clk : out STD_LOGIC;
- resetn : in STD_LOGIC;
- locked : out STD_LOGIC;
- clk_in1 : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of clk_pll_clk_pll_clk_wiz : entity is "clk_pll_clk_wiz";
-end clk_pll_clk_pll_clk_wiz;
-
-architecture STRUCTURE of clk_pll_clk_pll_clk_wiz is
- signal clk_in1_clk_pll : STD_LOGIC;
- signal clkfbout_buf_clk_pll : STD_LOGIC;
- signal clkfbout_clk_pll : STD_LOGIC;
- signal cpu_clk_clk_pll : STD_LOGIC;
- signal reset_high : STD_LOGIC;
- signal sys_clk_clk_pll : STD_LOGIC;
- signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
- signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
- signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
- signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
- signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
- signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
- attribute BOX_TYPE : string;
- attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
- attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
- attribute CAPACITANCE : string;
- attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE : string;
- attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
- attribute IFD_DELAY_VALUE : string;
- attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
- attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
- attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
- attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
-begin
-clkf_buf: unisim.vcomponents.BUFG
- port map (
- I => clkfbout_clk_pll,
- O => clkfbout_buf_clk_pll
- );
-clkin1_ibufg: unisim.vcomponents.IBUF
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => clk_in1,
- O => clk_in1_clk_pll
- );
-clkout1_buf: unisim.vcomponents.BUFG
- port map (
- I => cpu_clk_clk_pll,
- O => cpu_clk
- );
-clkout2_buf: unisim.vcomponents.BUFG
- port map (
- I => sys_clk_clk_pll,
- O => sys_clk
- );
-plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
- generic map(
- BANDWIDTH => "OPTIMIZED",
- CLKFBOUT_MULT => 31,
- CLKFBOUT_PHASE => 0.000000,
- CLKIN1_PERIOD => 20.000000,
- CLKIN2_PERIOD => 0.000000,
- CLKOUT0_DIVIDE => 47,
- CLKOUT0_DUTY_CYCLE => 0.500000,
- CLKOUT0_PHASE => 0.000000,
- CLKOUT1_DIVIDE => 31,
- CLKOUT1_DUTY_CYCLE => 0.500000,
- CLKOUT1_PHASE => 0.000000,
- CLKOUT2_DIVIDE => 1,
- CLKOUT2_DUTY_CYCLE => 0.500000,
- CLKOUT2_PHASE => 0.000000,
- CLKOUT3_DIVIDE => 1,
- CLKOUT3_DUTY_CYCLE => 0.500000,
- CLKOUT3_PHASE => 0.000000,
- CLKOUT4_DIVIDE => 1,
- CLKOUT4_DUTY_CYCLE => 0.500000,
- CLKOUT4_PHASE => 0.000000,
- CLKOUT5_DIVIDE => 1,
- CLKOUT5_DUTY_CYCLE => 0.500000,
- CLKOUT5_PHASE => 0.000000,
- COMPENSATION => "ZHOLD",
- DIVCLK_DIVIDE => 1,
- IS_CLKINSEL_INVERTED => '0',
- IS_PWRDWN_INVERTED => '0',
- IS_RST_INVERTED => '0',
- REF_JITTER1 => 0.010000,
- REF_JITTER2 => 0.010000,
- STARTUP_WAIT => "FALSE"
- )
- port map (
- CLKFBIN => clkfbout_buf_clk_pll,
- CLKFBOUT => clkfbout_clk_pll,
- CLKIN1 => clk_in1_clk_pll,
- CLKIN2 => '0',
- CLKINSEL => '1',
- CLKOUT0 => cpu_clk_clk_pll,
- CLKOUT1 => sys_clk_clk_pll,
- CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED,
- CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
- CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
- CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
- DADDR(6 downto 0) => B"0000000",
- DCLK => '0',
- DEN => '0',
- DI(15 downto 0) => B"0000000000000000",
- DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
- DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
- DWE => '0',
- LOCKED => locked,
- PWRDWN => '0',
- RST => reset_high
- );
-plle2_adv_inst_i_1: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => resetn,
- O => reset_high
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity clk_pll is
- port (
- cpu_clk : out STD_LOGIC;
- sys_clk : out STD_LOGIC;
- resetn : in STD_LOGIC;
- locked : out STD_LOGIC;
- clk_in1 : in STD_LOGIC
- );
- attribute NotValidForBitStream : boolean;
- attribute NotValidForBitStream of clk_pll : entity is true;
-end clk_pll;
-
-architecture STRUCTURE of clk_pll is
-begin
-inst: entity work.clk_pll_clk_pll_clk_wiz
- port map (
- clk_in1 => clk_in1,
- cpu_clk => cpu_clk,
- locked => locked,
- resetn => resetn,
- sys_clk => sys_clk
- );
-end STRUCTURE;
diff --git a/rtl/ip/PLL_2019_2/clk_pll_stub.v b/rtl/ip/PLL_2019_2/clk_pll_stub.v
deleted file mode 100644
index d6ce4de..0000000
--- a/rtl/ip/PLL_2019_2/clk_pll_stub.v
+++ /dev/null
@@ -1,23 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Tue Jun 23 00:27:14 2026
-// Host : fedora running 64-bit unknown
-// Command : write_verilog -force -mode synth_stub
-// /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.v
-// Design : clk_pll
-// Purpose : Stub declaration of top-level module interface
-// Device : xc7a200tfbg676-1
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-module clk_pll(cpu_clk, sys_clk, resetn, locked, clk_in1)
-/* synthesis syn_black_box black_box_pad_pin="cpu_clk,sys_clk,resetn,locked,clk_in1" */;
- output cpu_clk;
- output sys_clk;
- input resetn;
- output locked;
- input clk_in1;
-endmodule
diff --git a/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl b/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl
deleted file mode 100644
index e5ecdc3..0000000
--- a/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl
+++ /dev/null
@@ -1,32 +0,0 @@
--- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
--- Date : Tue Jun 23 00:27:14 2026
--- Host : fedora running 64-bit unknown
--- Command : write_vhdl -force -mode synth_stub
--- /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl
--- Design : clk_pll
--- Purpose : Stub declaration of top-level module interface
--- Device : xc7a200tfbg676-1
--- --------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity clk_pll is
- Port (
- cpu_clk : out STD_LOGIC;
- sys_clk : out STD_LOGIC;
- resetn : in STD_LOGIC;
- locked : out STD_LOGIC;
- clk_in1 : in STD_LOGIC
- );
-
-end clk_pll;
-
-architecture stub of clk_pll is
-attribute syn_black_box : boolean;
-attribute black_box_pad_pin : string;
-attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "cpu_clk,sys_clk,resetn,locked,clk_in1";
-begin
-end;
diff --git a/rtl/ip/PLL_2023_2/clk_pll.xci b/rtl/ip/PLL_2023_2/clk_pll.xci
new file mode 100644
index 0000000..fed8371
--- /dev/null
+++ b/rtl/ip/PLL_2023_2/clk_pll.xci
@@ -0,0 +1,689 @@
+{
+ "schema": "xilinx.com:schema:json_instance:1.0",
+ "ip_inst": {
+ "xci_name": "clk_pll",
+ "component_reference": "xilinx.com:ip:clk_wiz:6.0",
+ "ip_revision": "13",
+ "gen_directory": "../../../fpga/project/ipgen/clk_pll",
+ "parameters": {
+ "component_parameters": {
+ "Component_Name": [ { "value": "clk_pll", "resolve_type": "user", "usage": "all" } ],
+ "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRIMITIVE": [ { "value": "PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
+ "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
+ "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
+ "PRIM_IN_FREQ": [ { "value": "50.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
+ "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
+ "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
+ "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
+ "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
+ "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+ "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
+ "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKIN1_JITTER_PS": [ { "value": "200.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "NUM_OUT_CLKS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT1_PORT": [ { "value": "cpu_clk", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT2_PORT": [ { "value": "sys_clk", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
+ "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
+ "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
+ "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
+ "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
+ "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
+ "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
+ "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
+ "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
+ "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
+ "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
+ "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "33.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "50.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT1_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT2_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT3_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT4_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT5_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT6_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT7_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
+ "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
+ "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+ "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+ "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "RESET_PORT": [ { "value": "resetn", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
+ "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
+ "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
+ "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
+ "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
+ "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
+ "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
+ "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+ "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "MMCM_CLKFBOUT_MULT_F": [ { "value": "31", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKIN1_PERIOD": [ { "value": "20.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_COMPENSATION": [ { "value": "ZHOLD", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "47", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT1_DIVIDE": [ { "value": "31", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+ "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+ "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
+ "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKIN_PERIOD": [ { "value": "20.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
+ "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "RESET_TYPE": [ { "value": "ACTIVE_LOW", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+ "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
+ "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
+ "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_JITTER": [ { "value": "130.093", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_PHASE_ERROR": [ { "value": "123.600", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_JITTER": [ { "value": "122.035", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_PHASE_ERROR": [ { "value": "123.600", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
+ "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
+ "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+ },
+ "model_parameters": {
+ "C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+ "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "c_component_name": [ { "value": "clk_pll", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIM_IN_FREQ": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
+ "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
+ "C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+ "C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
+ "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_RESET_LOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_NUM_OUT_CLKS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
+ "C_INCLK_SUM_ROW1": [ { "value": "__primary__________50.000____________0.010", "resolve_type": "generated", "usage": "all" } ],
+ "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW1": [ { "value": "_cpu_clk__32.97872______0.000______50.0______130.093____123.600", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW2": [ { "value": "_sys_clk__50.00000______0.000______50.0______122.035____123.600", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "33.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_OUT_FREQ": [ { "value": "32.97872", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_OUT_FREQ": [ { "value": "50.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "31.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKIN1_PERIOD": [ { "value": "20.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+ "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+ "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+ "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "47.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "31", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+ "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
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+ "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+ "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
+ "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
+ "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT1_PORT": [ { "value": "cpu_clk", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT2_PORT": [ { "value": "sys_clk", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
+ "C_RESET_PORT": [ { "value": "resetn", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
+ "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
+ "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
+ "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
+ "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
+ "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
+ "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
+ "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
+ "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
+ "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKIN1_JITTER_PS": [ { "value": "200.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PRIMITIVE": [ { "value": "PLL", "resolve_type": "generated", "usage": "all" } ],
+ "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
+ "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+ "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
+ "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
+ "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
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+ "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE2_AUTO": [ { "value": "0.6595744680851063", "resolve_type": "generated", "usage": "all" } ],
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+ "C_DIVIDE6_AUTO": [ { "value": "0.02127659574468085", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE7_AUTO": [ { "value": "0.02127659574468085", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
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+ "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
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+ "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "32.97872", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "50.00000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_D_MAX": [ { "value": "42.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_VCO_MIN": [ { "value": "800.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_VCO_MAX": [ { "value": "1600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
+ },
+ "project_parameters": {
+ "ARCHITECTURE": [ { "value": "artix7" } ],
+ "BASE_BOARD_PART": [ { "value": "" } ],
+ "BOARD_CONNECTIONS": [ { "value": "" } ],
+ "DEVICE": [ { "value": "xc7a200t" } ],
+ "PACKAGE": [ { "value": "fbg676" } ],
+ "PREFHDL": [ { "value": "VERILOG" } ],
+ "SILICON_REVISION": [ { "value": "" } ],
+ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+ "SPEEDGRADE": [ { "value": "-1" } ],
+ "STATIC_POWER": [ { "value": "" } ],
+ "TEMPERATURE_GRADE": [ { "value": "" } ]
+ },
+ "runtime_parameters": {
+ "IPCONTEXT": [ { "value": "IP_Flow" } ],
+ "IPREVISION": [ { "value": "13" } ],
+ "MANAGED": [ { "value": "TRUE" } ],
+ "OUTPUTDIR": [ { "value": "../../../fpga/project/ipgen/clk_pll" } ],
+ "SELECTEDSIMMODEL": [ { "value": "" } ],
+ "SHAREDDIR": [ { "value": "." } ],
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+ "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+ }
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+ "resetn": [ { "direction": "in", "driver_value": "0" } ],
+ "clk_in1": [ { "direction": "in" } ],
+ "cpu_clk": [ { "direction": "out" } ],
+ "sys_clk": [ { "direction": "out" } ],
+ "locked": [ { "direction": "out" } ]
+ },
+ "interfaces": {
+ "resetn": {
+ "vlnv": "xilinx.com:signal:reset:1.0",
+ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+ "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "RST": [ { "physical_name": "resetn" } ]
+ }
+ },
+ "clock_CLK_IN1": {
+ "vlnv": "xilinx.com:signal:clock:1.0",
+ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+ "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
+ },
+ "port_maps": {
+ "CLK_IN1": [ { "physical_name": "clk_in1" } ]
+ }
+ },
+ "clock_CLK_OUT1": {
+ "vlnv": "xilinx.com:signal:clock:1.0",
+ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+ "mode": "master",
+ "parameters": {
+ "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "CLK_OUT1": [ { "physical_name": "cpu_clk" } ]
+ }
+ },
+ "clock_CLK_OUT2": {
+ "vlnv": "xilinx.com:signal:clock:1.0",
+ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+ "mode": "master",
+ "parameters": {
+ "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "CLK_OUT2": [ { "physical_name": "sys_clk" } ]
+ }
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/rtl/ip/bram0/bram0.xci b/rtl/ip/bram0/bram0.xci
new file mode 100644
index 0000000..bd06ce5
--- /dev/null
+++ b/rtl/ip/bram0/bram0.xci
@@ -0,0 +1,315 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ bram0
+
+
+ 4096
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 100000000
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0.000
+ AXI4LITE
+ READ_WRITE
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 100000000
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0.000
+ AXI4LITE
+ READ_WRITE
+ 0
+ 0
+ 0
+ 0
+ 0
+ OTHER
+ NONE
+ 8192
+ 32
+ 1
+
+ OTHER
+ NONE
+ 8192
+ 32
+ 1
+
+
+ 100000000
+ 0
+ 0.000
+ 0
+ 10
+ 10
+ 1
+ 4
+ 0
+ 1
+ 9
+ 0
+ 0
+ 1
+ NONE
+ 0
+ 0
+ 0
+ ./
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ Estimated Power for IP : 5.254725 mW
+ artix7
+ 0
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ bram0.mem
+ no_coe_file_loaded
+ 0
+ 0
+ 1
+ 0
+ 1
+ 1024
+ 1024
+ 1
+ 1
+ 32
+ 32
+ 0
+ 0
+ CE
+ CE
+ ALL
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1024
+ 1024
+ NO_CHANGE
+ WRITE_FIRST
+ 32
+ 32
+ artix7
+ 4
+ Memory_Slave
+ AXI4_Full
+ false
+ Minimum_Area
+ false
+ 9
+ NONE
+ no_coe_file_loaded
+ ALL
+ bram0
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ Use_ENA_Pin
+ Use_ENB_Pin
+ Single_Bit_Error_Injection
+ false
+ Native
+ false
+ no_mem_loaded
+ Simple_Dual_Port_RAM
+ NO_CHANGE
+ WRITE_FIRST
+ 0
+ 0
+ BRAM
+ 0
+ 100
+ 100
+ 50
+ 100
+ 100
+ 0
+ 8kx2
+ false
+ false
+ 1
+ 1
+ 32
+ 32
+ false
+ false
+ false
+ true
+ 0
+ false
+ false
+ CE
+ CE
+ SYNC
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ 1024
+ 32
+ 32
+ No_ECC
+ false
+ false
+ false
+ Stand_Alone
+ artix7
+
+
+ xc7a200t
+ fbg676
+ VERILOG
+
+ MIXED
+ -1
+
+
+ TRUE
+ TRUE
+ IP_Flow
+ 4
+ TRUE
+ .
+
+ .
+ 2019.2
+ OUT_OF_CONTEXT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/rtl/ip/open-la500/IP/data_bank_sram.xcix b/rtl/ip/open-la500/IP/data_bank_sram.xcix
new file mode 100644
index 0000000..7312e3e
Binary files /dev/null and b/rtl/ip/open-la500/IP/data_bank_sram.xcix differ
diff --git a/rtl/ip/open-la500/IP/tagv_sram.xcix b/rtl/ip/open-la500/IP/tagv_sram.xcix
new file mode 100644
index 0000000..e7fcbde
Binary files /dev/null and b/rtl/ip/open-la500/IP/tagv_sram.xcix differ