fallensigh/ciciec2026
Archived
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add matmul AXI master path

Browse Source
This commit is contained in:
FallenSigh
2026-07-01 23:13:28 +08:00
parent 2b6e29f761
commit fd03aaaaa1
4 changed files with 2198 additions and 1748 deletions
Download Patch File Download Diff File Expand all files Collapse all files

365
rtl/ip/matmul/matmul_axi_slave.v
View File

@@ -95,6 +95,47 @@ module matmul_axi_slave (
output reg [31:0] ep_rd_data, output reg [31:0] ep_rd_data,
output ep_rd_ready, output ep_rd_ready,
// AXI master port for autonomous matrix stream load/store
output reg [3:0] m_axi_awid,
output reg [31:0] m_axi_awaddr,
output reg [7:0] m_axi_awlen,
output reg [2:0] m_axi_awsize,
output reg [1:0] m_axi_awburst,
output reg m_axi_awlock,
output reg [3:0] m_axi_awcache,
output reg [2:0] m_axi_awprot,
output reg m_axi_awvalid,
input m_axi_awready,
output reg [31:0] m_axi_wdata,
output reg [3:0] m_axi_wstrb,
output reg m_axi_wlast,
output reg m_axi_wvalid,
input m_axi_wready,
input [3:0] m_axi_bid,
input [1:0] m_axi_bresp,
input m_axi_bvalid,
output reg m_axi_bready,
output reg [3:0] m_axi_arid,
output reg [31:0] m_axi_araddr,
output reg [7:0] m_axi_arlen,
output reg [2:0] m_axi_arsize,
output reg [1:0] m_axi_arburst,
output reg m_axi_arlock,
output reg [3:0] m_axi_arcache,
output reg [2:0] m_axi_arprot,
output reg m_axi_arvalid,
input m_axi_arready,
input [3:0] m_axi_rid,
input [31:0] m_axi_rdata,
input [1:0] m_axi_rresp,
input m_axi_rlast,
input m_axi_rvalid,
output reg m_axi_rready,
// Interrupt output (active high level, pulsed by calc_done) // Interrupt output (active high level, pulsed by calc_done)
output intr output intr
); );
@@ -105,6 +146,11 @@ module matmul_axi_slave (
localparam ADDR_CTRL = 12'h000; localparam ADDR_CTRL = 12'h000;
localparam ADDR_STATUS = 12'h004; localparam ADDR_STATUS = 12'h004;
localparam ADDR_CRC = 12'h010; localparam ADDR_CRC = 12'h010;
localparam ADDR_DMA_SRC_BASE = 12'h020;
localparam ADDR_DMA_DST_BASE = 12'h024;
localparam ADDR_DMA_GROUPS = 12'h028;
localparam ADDR_DMA_SRC_STRIDE = 12'h02C;
localparam ADDR_DMA_DST_STRIDE = 12'h030;
localparam ADDR_B0_A = 12'h100; localparam ADDR_B0_A = 12'h100;
localparam ADDR_B0_B = 12'h140; localparam ADDR_B0_B = 12'h140;
@@ -131,6 +177,28 @@ module matmul_axi_slave (
reg [31:0] b1_b [0:15]; reg [31:0] b1_b [0:15];
reg [65:0] b1_c [0:15]; reg [65:0] b1_c [0:15];
reg [31:0] dma_src_base;
reg [31:0] dma_dst_base;
reg [31:0] dma_groups;
reg [31:0] dma_src_stride;
reg [31:0] dma_dst_stride;
reg dma_busy;
reg dma_done;
reg [31:0] load_group;
reg [31:0] store_group;
reg [31:0] completed_groups;
reg [1:0] bank_loaded;
reg [1:0] bank_store_pending;
reg [1:0] bank_storing;
reg [1:0] bank_compute_pending;
reg dma_compute_bank;
reg dma_load_bank;
reg dma_store_bank;
reg dma_start_pulse;
reg dma_done_clear_pulse;
reg dma_req0_pulse;
reg dma_req1_pulse;
assign ep_wr_ready = 1'b1; assign ep_wr_ready = 1'b1;
assign ep_rd_ready = 1'b1; assign ep_rd_ready = 1'b1;
@@ -177,12 +245,15 @@ module matmul_axi_slave (
reg [31:0] crc32_table [0:255]; reg [31:0] crc32_table [0:255];
reg [31:0] crc_reg; reg [31:0] crc_reg;
wire [31:0] crc_stream_data = ep_rd_valid ? ep_rd_data : s_axi_rdata; wire crc_dma_valid;
wire [31:0] crc_dma_data;
wire [31:0] crc_stream_data = crc_dma_valid ? crc_dma_data :
(ep_rd_valid ? ep_rd_data : s_axi_rdata);
wire crc_axi_valid = (r_state == R_DATA) && s_axi_rvalid && s_axi_rready && wire crc_axi_valid = (r_state == R_DATA) && s_axi_rvalid && s_axi_rready &&
((r_offset >= ADDR_B0_C && r_offset < (ADDR_B0_C + 12'h0C0)) || ((r_offset >= ADDR_B0_C && r_offset < (ADDR_B0_C + 12'h0C0)) ||
(r_offset >= ADDR_B1_C && r_offset < (ADDR_B1_C + 12'h0C0))); (r_offset >= ADDR_B1_C && r_offset < (ADDR_B1_C + 12'h0C0)));
wire crc_ep_valid = ep_rd_valid && ep_rd_ready && (ep_rd_word_addr < 8'd48); wire crc_ep_valid = ep_rd_valid && ep_rd_ready && (ep_rd_word_addr < 8'd48);
wire crc_stream_valid = crc_axi_valid || crc_ep_valid; wire crc_stream_valid = crc_axi_valid || crc_ep_valid || crc_dma_valid;
wire [31:0] crc_t0, crc_c0, crc_t1, crc_c1, crc_t2, crc_c2, crc_t3, crc_next; wire [31:0] crc_t0, crc_c0, crc_t1, crc_c1, crc_t2, crc_c2, crc_t3, crc_next;
assign crc_t0 = crc32_table[(crc_reg[7:0] ^ crc_stream_data[7:0])]; assign crc_t0 = crc32_table[(crc_reg[7:0] ^ crc_stream_data[7:0])];
@@ -349,6 +420,46 @@ module matmul_axi_slave (
reg cur_bank; reg cur_bank;
reg calc_done_pulse; reg calc_done_pulse;
localparam DMA_RD_IDLE = 2'd0;
localparam DMA_RD_ADDR = 2'd1;
localparam DMA_RD_DATA = 2'd2;
reg [1:0] dma_rd_state;
reg [4:0] dma_rd_count;
reg dma_rd_bank;
wire [3:0] dma_rd_word_idx = dma_rd_count[3:0];
wire dma_rd_commit = (dma_rd_state == DMA_RD_DATA) && m_axi_rvalid && m_axi_rready;
localparam DMA_WR_IDLE = 2'd0;
localparam DMA_WR_ADDR = 2'd1;
localparam DMA_WR_DATA = 2'd2;
localparam DMA_WR_RESP = 2'd3;
reg [1:0] dma_wr_state;
reg [5:0] dma_wr_count;
wire [7:0] dma_wr_elem_raw = dma_wr_count / 6'd3;
wire [7:0] dma_wr_part_raw = dma_wr_count % 6'd3;
wire [3:0] dma_wr_elem = dma_wr_elem_raw[3:0];
wire [1:0] dma_wr_part = dma_wr_part_raw[1:0];
wire [65:0] dma_wr_c0 = b0_c[dma_wr_elem];
wire [65:0] dma_wr_c1 = b1_c[dma_wr_elem];
wire [65:0] dma_wr_c = dma_store_bank ? dma_wr_c1 : dma_wr_c0;
wire [31:0] dma_wr_word =
(dma_wr_part == 2'd0) ? dma_wr_c[31:0] :
(dma_wr_part == 2'd1) ? dma_wr_c[63:32] :
{30'b0, dma_wr_c[65:64]};
wire [5:0] dma_wr_next_count = dma_wr_count + 6'd1;
wire [7:0] dma_wr_next_elem_raw = dma_wr_next_count / 6'd3;
wire [7:0] dma_wr_next_part_raw = dma_wr_next_count % 6'd3;
wire [3:0] dma_wr_next_elem = dma_wr_next_elem_raw[3:0];
wire [1:0] dma_wr_next_part = dma_wr_next_part_raw[1:0];
wire [65:0] dma_wr_next_c0 = b0_c[dma_wr_next_elem];
wire [65:0] dma_wr_next_c1 = b1_c[dma_wr_next_elem];
wire [65:0] dma_wr_next_c = dma_store_bank ? dma_wr_next_c1 : dma_wr_next_c0;
wire [31:0] dma_wr_word_next =
(dma_wr_next_part == 2'd0) ? dma_wr_next_c[31:0] :
(dma_wr_next_part == 2'd1) ? dma_wr_next_c[63:32] :
{30'b0, dma_wr_next_c[65:64]};
// 【修改点 1】单独引出一个写脉冲信号给 CRC 清零用 // 【修改点 1】单独引出一个写脉冲信号给 CRC 清零用
wire crc_clear_pulse = (w_state == W_DATA) && s_axi_wvalid && s_axi_wready && (w_offset == ADDR_CRC); wire crc_clear_pulse = (w_state == W_DATA) && s_axi_wvalid && s_axi_wready && (w_offset == ADDR_CRC);
wire done_clear_pulse = (w_state == W_DATA) && s_axi_wvalid && s_axi_wready && wire done_clear_pulse = (w_state == W_DATA) && s_axi_wvalid && s_axi_wready &&
@@ -364,7 +475,17 @@ module matmul_axi_slave (
req_1 <= 1'b0; req_1 <= 1'b0;
done_count <= 2'd0; done_count <= 2'd0;
error <= 1'b0; error <= 1'b0;
dma_src_base <= 32'd0;
dma_dst_base <= 32'd0;
dma_groups <= 32'd0;
dma_src_stride <= 32'd128;
dma_dst_stride <= 32'd192;
dma_start_pulse <= 1'b0;
dma_done_clear_pulse <= 1'b0;
end else begin end else begin
dma_start_pulse <= 1'b0;
dma_done_clear_pulse <= 1'b0;
if (ep_wr_valid && ep_wr_ready) begin if (ep_wr_valid && ep_wr_ready) begin
if (ep_wr_bank[0] == 1'b0) begin if (ep_wr_bank[0] == 1'b0) begin
if (ep_wr_word_addr < 8'd16) if (ep_wr_word_addr < 8'd16)
@@ -383,8 +504,24 @@ module matmul_axi_slave (
end end
end end
if (dma_rd_commit) begin
if (dma_rd_bank == 1'b0) begin
if (dma_rd_count < 5'd16)
b0_a[dma_rd_word_idx] <= m_axi_rdata;
else
b0_b[dma_rd_word_idx] <= m_axi_rdata;
end else begin
if (dma_rd_count < 5'd16)
b1_a[dma_rd_word_idx] <= m_axi_rdata;
else
b1_b[dma_rd_word_idx] <= m_axi_rdata;
end
end
if (req_0 && state == C_RUN && cur_bank == 1'b0) req_0 <= 1'b0; if (req_0 && state == C_RUN && cur_bank == 1'b0) req_0 <= 1'b0;
if (req_1 && state == C_RUN && cur_bank == 1'b1) req_1 <= 1'b0; if (req_1 && state == C_RUN && cur_bank == 1'b1) req_1 <= 1'b0;
if (dma_req0_pulse) req_0 <= 1'b1;
if (dma_req1_pulse) req_1 <= 1'b1;
case (w_state) case (w_state)
W_IDLE: begin W_IDLE: begin
@@ -403,10 +540,22 @@ module matmul_axi_slave (
if (w_offset == ADDR_CTRL) begin if (w_offset == ADDR_CTRL) begin
if (s_axi_wdata[0]) req_0 <= 1'b1; if (s_axi_wdata[0]) req_0 <= 1'b1;
if (s_axi_wdata[1]) req_1 <= 1'b1; if (s_axi_wdata[1]) req_1 <= 1'b1;
if (s_axi_wdata[8]) dma_start_pulse <= 1'b1;
end end
else if (w_offset == ADDR_STATUS) begin else if (w_offset == ADDR_STATUS) begin
if (s_axi_wdata[2]) error <= 1'b0; if (s_axi_wdata[2]) error <= 1'b0;
if (s_axi_wdata[4]) dma_done_clear_pulse <= 1'b1;
end end
else if (w_offset == ADDR_DMA_SRC_BASE)
dma_src_base <= apply_wstrb(dma_src_base, s_axi_wdata, s_axi_wstrb);
else if (w_offset == ADDR_DMA_DST_BASE)
dma_dst_base <= apply_wstrb(dma_dst_base, s_axi_wdata, s_axi_wstrb);
else if (w_offset == ADDR_DMA_GROUPS)
dma_groups <= apply_wstrb(dma_groups, s_axi_wdata, s_axi_wstrb);
else if (w_offset == ADDR_DMA_SRC_STRIDE)
dma_src_stride <= apply_wstrb(dma_src_stride, s_axi_wdata, s_axi_wstrb);
else if (w_offset == ADDR_DMA_DST_STRIDE)
dma_dst_stride <= apply_wstrb(dma_dst_stride, s_axi_wdata, s_axi_wstrb);
// 【修改点 2】删除 else if (w_offset == ADDR_CRC) { crc_reg <= ... } 防止多重驱动 // 【修改点 2】删除 else if (w_offset == ADDR_CRC) { crc_reg <= ... } 防止多重驱动
else if (w_offset >= ADDR_B0_A && w_offset < ADDR_B0_B) else if (w_offset >= ADDR_B0_A && w_offset < ADDR_B0_B)
b0_a[(w_offset - ADDR_B0_A) >> 2] <= apply_wstrb(b0_a[(w_offset - ADDR_B0_A) >> 2], s_axi_wdata, s_axi_wstrb); b0_a[(w_offset - ADDR_B0_A) >> 2] <= apply_wstrb(b0_a[(w_offset - ADDR_B0_A) >> 2], s_axi_wdata, s_axi_wstrb);
@@ -528,7 +677,17 @@ module matmul_axi_slave (
else if (current_r_offset == ADDR_CRC) else if (current_r_offset == ADDR_CRC)
s_axi_rdata = crc_reg ^ 32'hFFFFFFFF; s_axi_rdata = crc_reg ^ 32'hFFFFFFFF;
else if (current_r_offset == ADDR_STATUS) else if (current_r_offset == ADDR_STATUS)
s_axi_rdata = {29'b0, error, done, busy}; s_axi_rdata = {27'b0, dma_done, dma_busy, error, done, busy};
else if (current_r_offset == ADDR_DMA_SRC_BASE)
s_axi_rdata = dma_src_base;
else if (current_r_offset == ADDR_DMA_DST_BASE)
s_axi_rdata = dma_dst_base;
else if (current_r_offset == ADDR_DMA_GROUPS)
s_axi_rdata = dma_groups;
else if (current_r_offset == ADDR_DMA_SRC_STRIDE)
s_axi_rdata = dma_src_stride;
else if (current_r_offset == ADDR_DMA_DST_STRIDE)
s_axi_rdata = dma_dst_stride;
else if (current_r_offset >= ADDR_B0_A && current_r_offset < ADDR_B0_B) else if (current_r_offset >= ADDR_B0_A && current_r_offset < ADDR_B0_B)
s_axi_rdata = b0_a[(current_r_offset - ADDR_B0_A) >> 2]; s_axi_rdata = b0_a[(current_r_offset - ADDR_B0_A) >> 2];
else if (current_r_offset >= ADDR_B0_B && current_r_offset < ADDR_B0_C) else if (current_r_offset >= ADDR_B0_B && current_r_offset < ADDR_B0_C)
@@ -709,6 +868,206 @@ module matmul_axi_slave (
end end
end end
// ==========================================
// Autonomous AXI master loader/storer
// ==========================================
assign crc_dma_valid = (dma_wr_state == DMA_WR_DATA) && m_axi_wvalid && m_axi_wready;
assign crc_dma_data = m_axi_wdata;
always @(posedge clk) begin
if (!resetn) begin
dma_busy <= 1'b0;
dma_done <= 1'b0;
load_group <= 32'd0;
store_group <= 32'd0;
completed_groups <= 32'd0;
bank_loaded <= 2'b00;
bank_store_pending <= 2'b00;
bank_storing <= 2'b00;
bank_compute_pending <= 2'b00;
dma_compute_bank <= 1'b0;
dma_load_bank <= 1'b0;
dma_store_bank <= 1'b0;
dma_rd_state <= DMA_RD_IDLE;
dma_rd_count <= 5'd0;
dma_rd_bank <= 1'b0;
dma_wr_state <= DMA_WR_IDLE;
dma_wr_count <= 6'd0;
m_axi_arid <= 4'd0;
m_axi_araddr <= 32'd0;
m_axi_arlen <= 8'd31;
m_axi_arsize <= 3'd2;
m_axi_arburst <= 2'b01;
m_axi_arlock <= 1'b0;
m_axi_arcache <= 4'b0;
m_axi_arprot <= 3'b0;
m_axi_arvalid <= 1'b0;
m_axi_rready <= 1'b0;
m_axi_awid <= 4'd0;
m_axi_awaddr <= 32'd0;
m_axi_awlen <= 8'd47;
m_axi_awsize <= 3'd2;
m_axi_awburst <= 2'b01;
m_axi_awlock <= 1'b0;
m_axi_awcache <= 4'b0;
m_axi_awprot <= 3'b0;
m_axi_awvalid <= 1'b0;
m_axi_wdata <= 32'd0;
m_axi_wstrb <= 4'hF;
m_axi_wlast <= 1'b0;
m_axi_wvalid <= 1'b0;
m_axi_bready <= 1'b0;
dma_req0_pulse <= 1'b0;
dma_req1_pulse <= 1'b0;
end else begin
dma_req0_pulse <= 1'b0;
dma_req1_pulse <= 1'b0;
if (dma_done_clear_pulse)
dma_done <= 1'b0;
if (dma_start_pulse && !dma_busy && dma_groups != 32'd0) begin
dma_busy <= 1'b1;
dma_done <= 1'b0;
load_group <= 32'd0;
store_group <= 32'd0;
completed_groups <= 32'd0;
bank_loaded <= 2'b00;
bank_store_pending <= 2'b00;
bank_storing <= 2'b00;
bank_compute_pending <= 2'b00;
dma_compute_bank <= 1'b0;
dma_load_bank <= 1'b0;
dma_store_bank <= 1'b0;
dma_rd_state <= DMA_RD_IDLE;
dma_wr_state <= DMA_WR_IDLE;
end
if (dma_busy) begin
if (state == C_RUN)
bank_compute_pending[cur_bank] <= 1'b0;
if (bank_loaded[0] && !req_0 && !bank_store_pending[0] && !bank_storing[0] &&
!bank_compute_pending[0] && !(state == C_RUN && cur_bank == 1'b0)) begin
dma_req0_pulse <= 1'b1;
bank_loaded[0] <= 1'b0;
bank_compute_pending[0] <= 1'b1;
dma_compute_bank <= 1'b0;
end else if (bank_loaded[1] && !req_1 && !bank_store_pending[1] && !bank_storing[1] &&
!bank_compute_pending[1] && !(state == C_RUN && cur_bank == 1'b1)) begin
dma_req1_pulse <= 1'b1;
bank_loaded[1] <= 1'b0;
bank_compute_pending[1] <= 1'b1;
dma_compute_bank <= 1'b1;
end
end
if (calc_done_pulse && dma_busy) begin
bank_store_pending[cur_bank] <= 1'b1;
end
case (dma_rd_state)
DMA_RD_IDLE: begin
m_axi_arvalid <= 1'b0;
m_axi_rready <= 1'b0;
if (dma_busy && load_group < dma_groups && !bank_loaded[dma_load_bank] &&
!bank_compute_pending[dma_load_bank] &&
!((dma_load_bank == 1'b0) ? req_0 : req_1) &&
!(state == C_RUN && cur_bank == dma_load_bank)) begin
dma_rd_bank <= dma_load_bank;
dma_rd_count <= 5'd0;
m_axi_araddr <= dma_src_base + (load_group * dma_src_stride);
m_axi_arlen <= 8'd31;
m_axi_arsize <= 3'd2;
m_axi_arburst <= 2'b01;
m_axi_arvalid <= 1'b1;
dma_rd_state <= DMA_RD_ADDR;
end
end
DMA_RD_ADDR: begin
if (m_axi_arvalid && m_axi_arready) begin
m_axi_arvalid <= 1'b0;
m_axi_rready <= 1'b1;
dma_rd_state <= DMA_RD_DATA;
end
end
DMA_RD_DATA: begin
if (m_axi_rvalid && m_axi_rready) begin
if (m_axi_rlast) begin
m_axi_rready <= 1'b0;
bank_loaded[dma_rd_bank] <= 1'b1;
load_group <= load_group + 32'd1;
dma_load_bank <= ~dma_load_bank;
dma_rd_state <= DMA_RD_IDLE;
end else begin
dma_rd_count <= dma_rd_count + 5'd1;
end
end
end
default: dma_rd_state <= DMA_RD_IDLE;
endcase
case (dma_wr_state)
DMA_WR_IDLE: begin
m_axi_awvalid <= 1'b0;
m_axi_wvalid <= 1'b0;
m_axi_bready <= 1'b0;
if (dma_busy && bank_store_pending[dma_store_bank]) begin
dma_wr_count <= 6'd0;
bank_store_pending[dma_store_bank] <= 1'b0;
bank_storing[dma_store_bank] <= 1'b1;
m_axi_awaddr <= dma_dst_base + (store_group * dma_dst_stride);
m_axi_awlen <= 8'd47;
m_axi_awsize <= 3'd2;
m_axi_awburst <= 2'b01;
m_axi_awvalid <= 1'b1;
dma_wr_state <= DMA_WR_ADDR;
end
end
DMA_WR_ADDR: begin
if (m_axi_awvalid && m_axi_awready) begin
m_axi_awvalid <= 1'b0;
m_axi_wvalid <= 1'b1;
m_axi_wdata <= dma_wr_word;
m_axi_wlast <= 1'b0;
dma_wr_state <= DMA_WR_DATA;
end
end
DMA_WR_DATA: begin
if (m_axi_wvalid && m_axi_wready) begin
if (dma_wr_count == 6'd47) begin
m_axi_wvalid <= 1'b0;
m_axi_wlast <= 1'b0;
m_axi_bready <= 1'b1;
dma_wr_state <= DMA_WR_RESP;
end else begin
dma_wr_count <= dma_wr_count + 6'd1;
m_axi_wdata <= dma_wr_word_next;
m_axi_wlast <= (dma_wr_count == 6'd46);
end
end
end
DMA_WR_RESP: begin
if (m_axi_bvalid && m_axi_bready) begin
m_axi_bready <= 1'b0;
bank_storing[dma_store_bank] <= 1'b0;
dma_store_bank <= ~dma_store_bank;
store_group <= store_group + 32'd1;
completed_groups <= completed_groups + 32'd1;
if ((completed_groups + 32'd1) >= dma_groups) begin
dma_busy <= 1'b0;
dma_done <= 1'b1;
end
dma_wr_state <= DMA_WR_IDLE;
end
end
default: dma_wr_state <= DMA_WR_IDLE;
endcase
end
end
assign intr = done; assign intr = done;
endmodule endmodule

143
rtl/soc_top.v
View File

@@ -361,6 +361,43 @@ wire [1 :0] dma_m_bresp ;
wire dma_m_bvalid ; wire dma_m_bvalid ;
wire dma_m_bready ; wire dma_m_bready ;
wire [3 :0] cdma_m_arid ;
wire [31:0] cdma_m_araddr ;
wire [7 :0] cdma_m_arlen ;
wire [2 :0] cdma_m_arsize ;
wire [1 :0] cdma_m_arburst;
wire cdma_m_arlock ;
wire [3 :0] cdma_m_arcache;
wire [2 :0] cdma_m_arprot ;
wire cdma_m_arvalid;
wire cdma_m_arready = 1'b0;
wire [3 :0] cdma_m_rid = 4'd0;
wire [31:0] cdma_m_rdata = 32'd0;
wire [1 :0] cdma_m_rresp = 2'd0;
wire cdma_m_rlast = 1'b0;
wire cdma_m_rvalid = 1'b0;
wire cdma_m_rready ;
wire [3 :0] cdma_m_awid ;
wire [31:0] cdma_m_awaddr ;
wire [7 :0] cdma_m_awlen ;
wire [2 :0] cdma_m_awsize ;
wire [1 :0] cdma_m_awburst;
wire cdma_m_awlock ;
wire [3 :0] cdma_m_awcache;
wire [2 :0] cdma_m_awprot ;
wire cdma_m_awvalid;
wire cdma_m_awready = 1'b0;
wire [3 :0] cdma_m_wid ;
wire [31:0] cdma_m_wdata ;
wire [3 :0] cdma_m_wstrb ;
wire cdma_m_wlast ;
wire cdma_m_wvalid ;
wire cdma_m_wready = 1'b0;
wire [3 :0] cdma_m_bid = 4'd0;
wire [1 :0] cdma_m_bresp = 2'd0;
wire cdma_m_bvalid = 1'b0;
wire cdma_m_bready ;
wire [4 :0] dma_s_arid ; wire [4 :0] dma_s_arid ;
wire [31:0] dma_s_araddr ; wire [31:0] dma_s_araddr ;
wire [7 :0] dma_s_arlen ; wire [7 :0] dma_s_arlen ;
@@ -1546,6 +1583,42 @@ matmul_axi_slave u_matmul_axi_slave (
.ep_rd_data (dma_ep_rd_data), .ep_rd_data (dma_ep_rd_data),
.ep_rd_ready (dma_ep_rd_ready), .ep_rd_ready (dma_ep_rd_ready),
.m_axi_awid (dma_m_awid),
.m_axi_awaddr (dma_m_awaddr),
.m_axi_awlen (dma_m_awlen),
.m_axi_awsize (dma_m_awsize),
.m_axi_awburst (dma_m_awburst),
.m_axi_awlock (dma_m_awlock),
.m_axi_awcache (dma_m_awcache),
.m_axi_awprot (dma_m_awprot),
.m_axi_awvalid (dma_m_awvalid),
.m_axi_awready (dma_m_awready),
.m_axi_wdata (dma_m_wdata),
.m_axi_wstrb (dma_m_wstrb),
.m_axi_wlast (dma_m_wlast),
.m_axi_wvalid (dma_m_wvalid),
.m_axi_wready (dma_m_wready),
.m_axi_bid (dma_m_bid),
.m_axi_bresp (dma_m_bresp),
.m_axi_bvalid (dma_m_bvalid),
.m_axi_bready (dma_m_bready),
.m_axi_arid (dma_m_arid),
.m_axi_araddr (dma_m_araddr),
.m_axi_arlen (dma_m_arlen),
.m_axi_arsize (dma_m_arsize),
.m_axi_arburst (dma_m_arburst),
.m_axi_arlock (dma_m_arlock),
.m_axi_arcache (dma_m_arcache),
.m_axi_arprot (dma_m_arprot),
.m_axi_arvalid (dma_m_arvalid),
.m_axi_arready (dma_m_arready),
.m_axi_rid (dma_m_rid),
.m_axi_rdata (dma_m_rdata),
.m_axi_rresp (dma_m_rresp),
.m_axi_rlast (dma_m_rlast),
.m_axi_rvalid (dma_m_rvalid),
.m_axi_rready (dma_m_rready),
.intr (matmul_intr) .intr (matmul_intr)
); );
@@ -1671,48 +1744,48 @@ snix_axil_cdma_mux #(
.s_axil_rready (cdma_s_rready), .s_axil_rready (cdma_s_rready),
// AXI4 主机接口 (接 Crossbar 去搬运数据) // AXI4 主机接口 (接 Crossbar 去搬运数据)
.mm2mm_awid (dma_m_awid), .mm2mm_awid (cdma_m_awid),
.mm2mm_awaddr (dma_m_awaddr), .mm2mm_awaddr (cdma_m_awaddr),
.mm2mm_awlen (dma_m_awlen), .mm2mm_awlen (cdma_m_awlen),
.mm2mm_awsize (dma_m_awsize), .mm2mm_awsize (cdma_m_awsize),
.mm2mm_awburst (dma_m_awburst), .mm2mm_awburst (cdma_m_awburst),
.mm2mm_awlock (dma_m_awlock), .mm2mm_awlock (cdma_m_awlock),
.mm2mm_awcache (dma_m_awcache), .mm2mm_awcache (cdma_m_awcache),
.mm2mm_awprot (dma_m_awprot), .mm2mm_awprot (cdma_m_awprot),
.mm2mm_awqos (), // 悬空即可 .mm2mm_awqos (), // 悬空即可
.mm2mm_awuser (), // 悬空即可 .mm2mm_awuser (), // 悬空即可
.mm2mm_awvalid (dma_m_awvalid), .mm2mm_awvalid (cdma_m_awvalid),
.mm2mm_awready (dma_m_awready), .mm2mm_awready (cdma_m_awready),
.mm2mm_wdata (dma_m_wdata), .mm2mm_wdata (cdma_m_wdata),
.mm2mm_wstrb (dma_m_wstrb), .mm2mm_wstrb (cdma_m_wstrb),
.mm2mm_wlast (dma_m_wlast), .mm2mm_wlast (cdma_m_wlast),
.mm2mm_wuser (), // 悬空即可 .mm2mm_wuser (), // 悬空即可
.mm2mm_wvalid (dma_m_wvalid), .mm2mm_wvalid (cdma_m_wvalid),
.mm2mm_wready (dma_m_wready), .mm2mm_wready (cdma_m_wready),
.mm2mm_bid (dma_m_bid), .mm2mm_bid (cdma_m_bid),
.mm2mm_bresp (dma_m_bresp), .mm2mm_bresp (cdma_m_bresp),
.mm2mm_buser (1'b0), .mm2mm_buser (1'b0),
.mm2mm_bvalid (dma_m_bvalid), .mm2mm_bvalid (cdma_m_bvalid),
.mm2mm_bready (dma_m_bready), .mm2mm_bready (cdma_m_bready),
.mm2mm_arid (dma_m_arid), .mm2mm_arid (cdma_m_arid),
.mm2mm_araddr (dma_m_araddr), .mm2mm_araddr (cdma_m_araddr),
.mm2mm_arlen (dma_m_arlen), .mm2mm_arlen (cdma_m_arlen),
.mm2mm_arsize (dma_m_arsize), .mm2mm_arsize (cdma_m_arsize),
.mm2mm_arburst (dma_m_arburst), .mm2mm_arburst (cdma_m_arburst),
.mm2mm_arlock (dma_m_arlock), .mm2mm_arlock (cdma_m_arlock),
.mm2mm_arcache (dma_m_arcache), .mm2mm_arcache (cdma_m_arcache),
.mm2mm_arprot (dma_m_arprot), .mm2mm_arprot (cdma_m_arprot),
.mm2mm_arqos (), // 悬空即可 .mm2mm_arqos (), // 悬空即可
.mm2mm_aruser (), // 悬空即可 .mm2mm_aruser (), // 悬空即可
.mm2mm_arvalid (dma_m_arvalid), .mm2mm_arvalid (cdma_m_arvalid),
.mm2mm_arready (dma_m_arready), .mm2mm_arready (cdma_m_arready),
.mm2mm_rid (dma_m_rid), .mm2mm_rid (cdma_m_rid),
.mm2mm_rdata (dma_m_rdata), .mm2mm_rdata (cdma_m_rdata),
.mm2mm_rresp (dma_m_rresp), .mm2mm_rresp (cdma_m_rresp),
.mm2mm_rlast (dma_m_rlast), .mm2mm_rlast (cdma_m_rlast),
.mm2mm_ruser (1'b0), .mm2mm_ruser (1'b0),
.mm2mm_rvalid (dma_m_rvalid), .mm2mm_rvalid (cdma_m_rvalid),
.mm2mm_rready (dma_m_rready), .mm2mm_rready (cdma_m_rready),
.ep_wr_valid (dma_ep_wr_valid), .ep_wr_valid (dma_ep_wr_valid),
.ep_wr_id (dma_ep_wr_id), .ep_wr_id (dma_ep_wr_id),

108
sdk/axi_ram.mif
View File

@@ -52,7 +52,7 @@
00000011100000000110000000001101 00000011100000000110000000001101
00000100000000000000000110101100 00000100000000000000000110101100
00011100000000000000000000101100 00011100000000000000000000101100
00000010101100111111000110001100 00000010101101001111000110001100
00011100000000000001000000001101 00011100000000000001000000001101
00000010101111001001000110101101 00000010101111001001000110101101
00011100000000000001000000001110 00011100000000000001000000001110
@@ -94,7 +94,7 @@
00000000000101010000000000001110 00000000000101010000000000001110
00101001000000000001000110101110 00101001000000000001000110101110
00011100000000000000000000001100 00011100000000000000000000001100
00000010100011000001000110001100 00000010100011010001000110001100
00000100000000000011000000101100 00000100000000000011000000101100
00000011100000000000010000001101 00000011100000000000010000001101
00000100000000010001000000101101 00000100000000010001000000101101
@@ -146,67 +146,70 @@
00010101011111100000000000010000 00010101011111100000000000010000
00101001100000000111000001100001 00101001100000000111000001100001
00101001100000000110000001110111 00101001100000000110000001110111
00101001100000000101000001111000
00000010100000010011010000001100 00000010100000010011010000001100
00011100000000000001000000001111 00011100000000000001000000001111
00000010101101101011000111101111 00000010101101101010000111101111
00000011100000000001011000001101 00000011100000000001011000001101
00101001100000000011000001101100 00101001100000000011000001101100
00101010000000000011000001101110 00101010000000000011000001101110
00000010100000000000010111101111 00000010100000000000010111101111
00000011010000000000000000000000
00101010000000000000000110101100 00101010000000000000000110101100
00000011010000001000000110001100 00000011010000001000000110001100
01011011111111111111100110000000 01011011111111111111100110000000
00101001000000000000001000001110 00101001000000000000001000001110
00101000000000000000000111101100 00101000000000000000000111101100
01011111111111111101110110000000 01011111111111111110000110000000
01010100000001100011100000000000 01010100000001100111100000000000
00010101011111100110000000001100 00010101011111101010000000001100
00000011100010000000000110001100 00000011100000000100000110010001
00000010100000000000100000001110 00101001100000000000001000100000
00101001100000000001000110001110 00000010100000000101100000010000
00010100001110001000000000001101 00000011100000000001000110001101
00101001100000000010000110001101 00101001100000000000000110110000
00000011100101000000000110110011 00010100001110001000000000001110
00000010100000000010100000010010 00000011100000001000000110001111
00101001100000000011000110010011 00101001100000000000000111101110
00101001100000000100000110010010 00000011100101000000000111000101
00010100001111101010000000010001 00000000000101010000000010011000
00000010100000100000000000010000 00000011100000001001000110000100
00101001100000000101000110010001 00101001100000000000000010000101
00101001100000000110000110010000 00000011100000001010000110010011
00000010100000110000000000001111 00000010100000000010100000010100
00000010100000000000010000001110 00101001100000000000001001110100
00101001100000000111000110001111 00000011100000001011000110010001
00000000000101010000000010010111 00000010100000100000000000010010
00000000000101010000000110001101 00101001100000000000001000110010
00000011100000001100000110001111
00000010100000110000000000010000
00000010100001000000000000001110
00101001100000000000000111110000
00010101011111101010000000010111
00101001100000000000000110001110 00101001100000000000000110001110
00000011010000000000000000000000 00101000100000000000000110101100
00101000100000000001000110101100 00000011010000000100000110001100
00000011010000000000100110001100
01011011111111111111100110000000 01011011111111111111100110000000
00000010100000000000100000001100 00000010100000000100000000001100
00101001100000000001000110101100 00101001100000000000000110101100
01010100000001011100110000000000 01010100000001011111110000000000
00011100000000000001000000001110 00011100000000000001000000001101
00000010101101011000000111001110 00000010101101010100000110101101
00101000100000000000000111010010 00000011100000000100001011110111
00010101011111101010000000001101 00101000100000000000000110110010
00101000100000000000001011110001
00010100000000000001111010001100 00010100000000000001111010001100
00000011100000000100000110101101
00010101011111100000000000010000 00010101011111100000000000010000
00000011100010010000000110001110 00000011100010010000000110001110
00000000000100010101110010000100 00000000000100010110000010000100
00000000001000010011101001010011 00000000001000010011101001010011
01011100000000000000100111000000 01011100000000000000100111000000
00000000001010100000000000000111 00000000001010100000000000000111
00101000100000000000000110110001 00000010100000010011010000001100
00000000001000010100110010010010 00000000001000010100110010010010
01011100000000000000101001100000 01011100000000000000101001100000
00000000001010100000000000000111 00000000001010100000000000000111
00000010100000010011010000001100
00011100000000000001000000001111 00011100000000000001000000001111
00000010101100110101000111101111 00000010101100110010000111101111
00000011100000000001011000001101 00000011100000000001011000001101
00101001100000000011000001101100 00101001100000000011000001101100
00101010000000000011000001101110 00101010000000000011000001101110
@@ -222,6 +225,7 @@
00000010100000000010010000010100 00000010100000000010010000010100
00000010101111111111000000010011 00000010101111111111000000010011
00000011100000000001011000001101 00000011100000000001011000001101
00000011010000000000000000000000
00000000000101111011101000101100 00000000000101111011101000101100
00000011010000000011110110001100 00000011010000000011110110001100
00000010100000010101110110001111 00000010100000010101110110001111
@@ -236,7 +240,7 @@
00010101011111100000000000010000 00010101011111100000000000010000
00000010100000000011010000001100 00000010100000000011010000001100
00011100000000000001000000001111 00011100000000000001000000001111
00000010101100011011000111101111 00000010101100010111000111101111
00000011100000000001011000001101 00000011100000000001011000001101
00101001100000000011000001101100 00101001100000000011000001101100
00101010000000000011000001101110 00101010000000000011000001101110
@@ -248,11 +252,11 @@
00101001000000000000001000001110 00101001000000000000001000001110
00101000000000000000000111101100 00101000000000000000000111101100
01011111111111111101110110000000 01011111111111111101110110000000
01010100000000101001100000000000 01010100000000101100100000000000
00010101011111100000000000010000 00010101011111100000000000010000
00000010100000000011010000001100 00000010100000000011010000001100
00011100000000000001000000001111 00011100000000000001000000001111
00000010101100010000000111101111 00000010101100001100000111101111
00000011100000000001011000001101 00000011100000000001011000001101
00101001100000000011000001101100 00101001100000000011000001101100
00101010000000000011000001101110 00101010000000000011000001101110
@@ -265,11 +269,11 @@
00101000000000000000000111101100 00101000000000000000000111101100
01011111111111111101110110000000 01011111111111111101110110000000
00000000000101010000001001000100 00000000000101010000001001000100
01010100000000100101010000000000 01010100000000101000010000000000
00010101011111100000000000010000 00010101011111100000000000010000
00000010100000000011010000001100 00000010100000000011010000001100
00011100000000000001000000001111 00011100000000000001000000001111
00000010101100000100000111101111 00000010101100000000000111101111
00000011100000000001011000001101 00000011100000000001011000001101
00101001100000000011000001101100 00101001100000000011000001101100
00101010000000000011000001101110 00101010000000000011000001101110
@@ -282,10 +286,22 @@
01011111111111111110000110000000 01011111111111111110000110000000
00101000100000000111000001100001 00101000100000000111000001100001
00101000100000000110000001110111 00101000100000000110000001110111
00101000100000000101000001111000
00000000000101010000000000000100 00000000000101010000000000000100
00000010100000001000000001100011 00000010100000001000000001100011
01001100000000000000000000100000 01001100000000000000000000100000
00000011010000000000000000000000 00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000010101111100001000001100011 00000010101111100001000001100011
00101001100000011110000001100001 00101001100000011110000001100001
00101001100000011101000001100010 00101001100000011101000001100010

42
sdk/software/examples/asm/user-sample.c
View File

@@ -1,13 +1,7 @@
/** /**
* user-sample - CIC-IEC 2026 Stage 3 Evaluation Program * user-sample - CIC-IEC 2026 Stage 3 Evaluation Program
* *
* (ULTIMATE PERFORMANCE DMA + PING-PONG BUFFER ARCHITECTURE v2) * Matmul AXI-master path.
*
* Optimizations over v1:
* 1. Pre-fire DMA Ch0 load at loop tail → fully overlaps with IP compute
* 2. Inlined wait loops → zero function-call overhead in hot path
* 3. Inlined DMA start → skips redundant STATUS_BUSY_BIT check
* 4. XOR bank toggle → avoids g%2 recomputation per iteration
*/ */
#include <dma.h> #include <dma.h>
@@ -82,12 +76,19 @@ unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
#define MATMUL_CTRL (MATMUL_BASE_UNCACHED + 0x000) #define MATMUL_CTRL (MATMUL_BASE_UNCACHED + 0x000)
#define MATMUL_STATUS (MATMUL_BASE_UNCACHED + 0x004) #define MATMUL_STATUS (MATMUL_BASE_UNCACHED + 0x004)
#define MATMUL_BASE_PHYS_FOR_DMA MATMUL_BASE_PHYS #define MATMUL_DMA_SRC_BASE (MATMUL_BASE_UNCACHED + 0x020)
#define MATMUL_DMA_DST_BASE (MATMUL_BASE_UNCACHED + 0x024)
#define MATMUL_DMA_GROUPS (MATMUL_BASE_UNCACHED + 0x028)
#define MATMUL_DMA_SRC_STRIDE (MATMUL_BASE_UNCACHED + 0x02C)
#define MATMUL_DMA_DST_STRIDE (MATMUL_BASE_UNCACHED + 0x030)
#define CTRL_START_B0 0x1 #define CTRL_START_B0 0x1
#define CTRL_START_B1 0x2 #define CTRL_START_B1 0x2
#define CTRL_DMA_START (1 << 8)
#define STATUS_DONE 0x2 #define STATUS_DONE 0x2
#define STATUS_ERROR 0x4 #define STATUS_ERROR 0x4
#define STATUS_DMA_BUSY (1 << 3)
#define STATUS_DMA_DONE (1 << 4)
#define MATMUL_CRC (MATMUL_BASE_UNCACHED + 0x010) #define MATMUL_CRC (MATMUL_BASE_UNCACHED + 0x010)
@@ -101,8 +102,9 @@ int main(void)
if (MATMUL_GROUP_NUM <= 0) return 0; if (MATMUL_GROUP_NUM <= 0) return 0;
/* ── Hot-path local volatile pointers (one-time addr calc) ──────── */ /* ── Hot-path local volatile pointers (one-time addr calc) ──────── */
volatile unsigned int *mat_crc = (volatile unsigned int *)MATMUL_CRC; volatile unsigned int *mat_ctrl = (volatile unsigned int *)MATMUL_CTRL;
volatile dma_seq_regs_t *seq = DMA_SEQ; volatile unsigned int *mat_status = (volatile unsigned int *)MATMUL_STATUS;
volatile unsigned int *mat_crc = (volatile unsigned int *)MATMUL_CRC;
unsigned int crc; unsigned int crc;
unsigned int cycle_start, cycle_end, cycles, time_us; unsigned int cycle_start, cycle_end, cycles, time_us;
@@ -111,16 +113,16 @@ int main(void)
uart_puts("MATMUL_START\r\n"); uart_puts("MATMUL_START\r\n");
cycle_start = get_clock_count(); cycle_start = get_clock_count();
seq->STATUS = SEQ_DONE_BIT; *(volatile unsigned int *)MATMUL_CRC = 0;
seq->SRC_BASE = EXTRAM_PHYS_AB(0); *mat_status = STATUS_DMA_DONE | STATUS_DONE | STATUS_ERROR;
seq->DST_BASE = EXTRAM_PHYS_C(0); *(volatile unsigned int *)MATMUL_DMA_SRC_BASE = EXTRAM_PHYS_AB(0);
seq->GROUPS = MATMUL_GROUP_NUM; *(volatile unsigned int *)MATMUL_DMA_DST_BASE = EXTRAM_PHYS_C(0);
seq->MAT_BASE = MATMUL_BASE_PHYS_FOR_DMA; *(volatile unsigned int *)MATMUL_DMA_GROUPS = MATMUL_GROUP_NUM;
seq->SRC_STRIDE = 128; *(volatile unsigned int *)MATMUL_DMA_SRC_STRIDE = 128;
seq->DST_STRIDE = 192; *(volatile unsigned int *)MATMUL_DMA_DST_STRIDE = 192;
seq->CTRL = SEQ_START_BIT; *mat_ctrl = CTRL_DMA_START;
while (!(seq->STATUS & SEQ_DONE_BIT)) {} while (!(*mat_status & STATUS_DMA_DONE)) {}
seq->STATUS = SEQ_DONE_BIT; *mat_status = STATUS_DMA_DONE;
cycle_end = get_clock_count(); cycle_end = get_clock_count();
cycles = cycle_end - cycle_start; cycles = cycle_end - cycle_start;
time_us = cycles / (CORE_CLOCKS_PER_SEC / 1000000UL); time_us = cycles / (CORE_CLOCKS_PER_SEC / 1000000UL);