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Add matmul AXI master path

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FallenSigh
2026-07-01 23:13:28 +08:00
parent 2b6e29f761
commit fd03aaaaa1
4 changed files with 2198 additions and 1748 deletions
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42
sdk/software/examples/asm/user-sample.c
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@@ -1,13 +1,7 @@
/**
* user-sample - CIC-IEC 2026 Stage 3 Evaluation Program
*
* (ULTIMATE PERFORMANCE DMA + PING-PONG BUFFER ARCHITECTURE v2)
*
* Optimizations over v1:
* 1. Pre-fire DMA Ch0 load at loop tail → fully overlaps with IP compute
* 2. Inlined wait loops → zero function-call overhead in hot path
* 3. Inlined DMA start → skips redundant STATUS_BUSY_BIT check
* 4. XOR bank toggle → avoids g%2 recomputation per iteration
* Matmul AXI-master path.
*/
#include <dma.h>
@@ -82,12 +76,19 @@ unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
#define MATMUL_CTRL (MATMUL_BASE_UNCACHED + 0x000)
#define MATMUL_STATUS (MATMUL_BASE_UNCACHED + 0x004)
#define MATMUL_BASE_PHYS_FOR_DMA MATMUL_BASE_PHYS
#define MATMUL_DMA_SRC_BASE (MATMUL_BASE_UNCACHED + 0x020)
#define MATMUL_DMA_DST_BASE (MATMUL_BASE_UNCACHED + 0x024)
#define MATMUL_DMA_GROUPS (MATMUL_BASE_UNCACHED + 0x028)
#define MATMUL_DMA_SRC_STRIDE (MATMUL_BASE_UNCACHED + 0x02C)
#define MATMUL_DMA_DST_STRIDE (MATMUL_BASE_UNCACHED + 0x030)
#define CTRL_START_B0 0x1
#define CTRL_START_B1 0x2
#define CTRL_DMA_START (1 << 8)
#define STATUS_DONE 0x2
#define STATUS_ERROR 0x4
#define STATUS_DMA_BUSY (1 << 3)
#define STATUS_DMA_DONE (1 << 4)
#define MATMUL_CRC (MATMUL_BASE_UNCACHED + 0x010)
@@ -101,8 +102,9 @@ int main(void)
if (MATMUL_GROUP_NUM <= 0) return 0;
/* ── Hot-path local volatile pointers (one-time addr calc) ──────── */
volatile unsigned int *mat_crc = (volatile unsigned int *)MATMUL_CRC;
volatile dma_seq_regs_t *seq = DMA_SEQ;
volatile unsigned int *mat_ctrl = (volatile unsigned int *)MATMUL_CTRL;
volatile unsigned int *mat_status = (volatile unsigned int *)MATMUL_STATUS;
volatile unsigned int *mat_crc = (volatile unsigned int *)MATMUL_CRC;
unsigned int crc;
unsigned int cycle_start, cycle_end, cycles, time_us;
@@ -111,16 +113,16 @@ int main(void)
uart_puts("MATMUL_START\r\n");
cycle_start = get_clock_count();
seq->STATUS = SEQ_DONE_BIT;
seq->SRC_BASE = EXTRAM_PHYS_AB(0);
seq->DST_BASE = EXTRAM_PHYS_C(0);
seq->GROUPS = MATMUL_GROUP_NUM;
seq->MAT_BASE = MATMUL_BASE_PHYS_FOR_DMA;
seq->SRC_STRIDE = 128;
seq->DST_STRIDE = 192;
seq->CTRL = SEQ_START_BIT;
while (!(seq->STATUS & SEQ_DONE_BIT)) {}
seq->STATUS = SEQ_DONE_BIT;
*(volatile unsigned int *)MATMUL_CRC = 0;
*mat_status = STATUS_DMA_DONE | STATUS_DONE | STATUS_ERROR;
*(volatile unsigned int *)MATMUL_DMA_SRC_BASE = EXTRAM_PHYS_AB(0);
*(volatile unsigned int *)MATMUL_DMA_DST_BASE = EXTRAM_PHYS_C(0);
*(volatile unsigned int *)MATMUL_DMA_GROUPS = MATMUL_GROUP_NUM;
*(volatile unsigned int *)MATMUL_DMA_SRC_STRIDE = 128;
*(volatile unsigned int *)MATMUL_DMA_DST_STRIDE = 192;
*mat_ctrl = CTRL_DMA_START;
while (!(*mat_status & STATUS_DMA_DONE)) {}
*mat_status = STATUS_DMA_DONE;
cycle_end = get_clock_count();
cycles = cycle_end - cycle_start;
time_us = cycles / (CORE_CLOCKS_PER_SEC / 1000000UL);