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add vivado reports

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FallenSigh
2026-07-08 03:48:37 +08:00
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 02:57:50 2026
| Host : fedora running 64-bit unknown
| Command : report_utilization -hierarchical -file /home/fallensigh/vivado_reports_withdsp/utilization_hier.rpt
| Design : soc_top
| Device : 7a200tfbg676-1
| Design State : Routed
---------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Utilization by Hierarchy
1. Utilization by Hierarchy
---------------------------
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| soc_top | (top) | 53691 | 51836 | 740 | 1115 | 39141 | 8 | 31 | 56 |
| (soc_top) | (top) | 102 | 46 | 56 | 0 | 9 | 0 | 0 | 0 |
| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| inst | clk_pll__clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| pll_clk.u_rst_mlkem | rst_sync_0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| pll_clk.u_rst_sys | rst_sync_1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 381 | 381 | 0 | 0 | 151 | 0 | 0 | 0 |
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 6 | 6 | 0 | 0 | 24 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_82 | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_65 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_81 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_66 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_80 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_67 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_79 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_76 | 27 | 27 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_77 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_78 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_73 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_74 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_75 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_70 | 20 | 20 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_71 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_72 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 23 | 23 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 96 | 96 | 0 | 0 | 25 | 0 | 0 | 0 |
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 75 | 75 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1_69 | 21 | 21 | 0 | 0 | 13 | 0 | 0 | 0 |
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 40 | 40 | 0 | 0 | 18 | 0 | 0 | 0 |
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 20 | 20 | 0 | 0 | 16 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1_68 | 21 | 21 | 0 | 0 | 2 | 0 | 0 | 0 |
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 53 | 53 | 0 | 0 | 17 | 0 | 0 | 0 |
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 38 | 38 | 0 | 0 | 8 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 32 | 32 | 0 | 0 | 14 | 0 | 0 | 0 |
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 20 | 20 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_Axi_CDC | Axi_CDC | 412 | 284 | 128 | 0 | 317 | 0 | 0 | 0 |
| arFifo | StreamFifoCC_3_48 | 185 | 149 | 36 | 0 | 77 | 0 | 0 | 0 |
| (arFifo) | StreamFifoCC_3_48 | 180 | 144 | 36 | 0 | 65 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_63 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_64 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| awFifo | StreamFifoCC_49 | 102 | 66 | 36 | 0 | 79 | 0 | 0 | 0 |
| (awFifo) | StreamFifoCC_49 | 98 | 62 | 36 | 0 | 65 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_10_60 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_61 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_62 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| bFifo | StreamFifoCC_2_50 | 14 | 14 | 0 | 0 | 26 | 0 | 0 | 0 |
| (bFifo) | StreamFifoCC_2_50 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_5_57 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_4_58 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_6_59 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| rFifo | StreamFifoCC_4_51 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 |
| (rFifo) | StreamFifoCC_4_51 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_55 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_1_56 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| wFifo | StreamFifoCC_1_52 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 |
| (wFifo) | StreamFifoCC_1_52 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_7_53 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_8_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| u_axi_axil_adapter | axi_axil_adapter | 1072 | 1072 | 0 | 0 | 173 | 0 | 0 | 0 |
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 497 | 497 | 0 | 0 | 85 | 0 | 0 | 0 |
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 575 | 575 | 0 | 0 | 88 | 0 | 0 | 0 |
| u_axi_dvi | axi_dvi | 284 | 284 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_axi_ram | axi_wrap_ram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_sram_sp | axi2sram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_uart_controller | axi_uart_controller | 683 | 667 | 16 | 0 | 457 | 0 | 0 | 0 |
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 251 | 251 | 0 | 0 | 120 | 0 | 0 | 0 |
| uart0 | UART_TOP | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
| regs | uart_regs | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
| (regs) | uart_regs | 119 | 119 | 0 | 0 | 155 | 0 | 0 | 0 |
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 |
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
| fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 |
| (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 |
| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
| transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 |
| (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 |
| fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 |
| (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 |
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
| u_cdma_matmul_bridge | cdma_matmul_bridge | 250 | 250 | 0 | 0 | 578 | 0 | 0 | 0 |
| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 |
| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 |
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
| u_cpu | core_top | 8556 | 8304 | 252 | 0 | 5591 | 0 | 20 | 0 |
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
| addr_trans | addr_trans | 2247 | 2107 | 140 | 0 | 1244 | 0 | 0 | 0 |
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
| tlb_entry | tlb_entry | 2247 | 2107 | 140 | 0 | 1204 | 0 | 0 | 0 |
| axi_bridge | axi_bridge | 39 | 39 | 0 | 0 | 214 | 0 | 0 | 0 |
| btb | btb | 1048 | 968 | 80 | 0 | 1611 | 0 | 0 | 0 |
| (btb) | btb | 1045 | 965 | 80 | 0 | 1611 | 0 | 0 | 0 |
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
| dcache | dcache | 552 | 520 | 32 | 0 | 146 | 0 | 10 | 0 |
| (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 |
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
| tagv_ram_way[1].u | tagv_sram_46 | 43 | 43 | 0 | 0 | 0 | 0 | 1 | 0 |
| exe_stage | exe_stage | 665 | 665 | 0 | 0 | 233 | 0 | 0 | 0 |
| (exe_stage) | exe_stage | 634 | 634 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
| icache | icache | 234 | 234 | 0 | 0 | 55 | 0 | 10 | 0 |
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
| tagv_ram_way[1].u | tagv_sram_35 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
| id_stage | id_stage | 1052 | 1052 | 0 | 0 | 108 | 0 | 0 | 0 |
| if_stage | if_stage | 134 | 134 | 0 | 0 | 173 | 0 | 0 | 0 |
| mem_stage | mem_stage | 115 | 115 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
| u_div | div | 142 | 142 | 0 | 0 | 107 | 0 | 0 | 0 |
| u_mul | mul | 933 | 933 | 0 | 0 | 592 | 0 | 0 | 0 |
| wb_stage | wb_stage | 689 | 689 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 32945 | 31724 | 112 | 1109 | 26787 | 8 | 10 | 40 |
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| u_fft_controller | fft_controller | 2647 | 1607 | 0 | 1040 | 1083 | 6 | 4 | 16 |
| (u_fft_controller) | fft_controller | 123 | 123 | 0 | 0 | 100 | 0 | 0 | 0 |
| u_FFT | FFT | 2495 | 1455 | 0 | 1040 | 983 | 6 | 0 | 16 |
| SU1 | SdfUnit | 1070 | 302 | 0 | 768 | 197 | 2 | 0 | 4 |
| (SU1) | SdfUnit | 205 | 205 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_25 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer | 562 | 50 | 0 | 512 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized0 | 256 | 0 | 0 | 256 | 32 | 0 | 0 | 0 |
| MU | Multiply_26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 |
| TW | Twiddle_27 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU2 | SdfUnit__parameterized0 | 492 | 300 | 0 | 192 | 197 | 2 | 0 | 4 |
| (SU2) | SdfUnit__parameterized0 | 73 | 73 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
| MU | Multiply_22 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
| TW | Twiddle_23 | 3 | 3 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU3 | SdfUnit__parameterized1 | 347 | 299 | 0 | 48 | 197 | 0 | 0 | 4 |
| (SU3) | SdfUnit__parameterized1 | 75 | 75 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_17 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
| MU | Multiply_19 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
| SU4 | SdfUnit__parameterized2 | 327 | 295 | 0 | 32 | 197 | 2 | 0 | 4 |
| (SU4) | SdfUnit__parameterized2 | 69 | 69 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_15 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
| MU | Multiply | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
| TW | Twiddle | 2 | 2 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU5 | SdfUnit__parameterized3 | 260 | 260 | 0 | 0 | 195 | 0 | 0 | 0 |
| (SU5) | SdfUnit__parameterized3 | 68 | 68 | 0 | 0 | 99 | 0 | 0 | 0 |
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
| u_in0 | my_bram0 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_in1 | my_bram0_12 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out0 | my_bram0_13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out1 | my_bram0_14 | 25 | 25 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_mlkem_axi_cdc | Axi_CDC_5 | 256 | 144 | 112 | 0 | 272 | 0 | 0 | 0 |
| arFifo | StreamFifoCC_3 | 51 | 23 | 28 | 0 | 55 | 0 | 0 | 0 |
| (arFifo) | StreamFifoCC_3 | 42 | 14 | 28 | 0 | 43 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_10 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| awFifo | StreamFifoCC | 40 | 16 | 24 | 0 | 49 | 0 | 0 | 0 |
| (awFifo) | StreamFifoCC | 31 | 7 | 24 | 0 | 35 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| bFifo | StreamFifoCC_2 | 18 | 14 | 4 | 0 | 27 | 0 | 0 | 0 |
| (bFifo) | StreamFifoCC_2 | 11 | 7 | 4 | 0 | 13 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_4 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_6 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
| rFifo | StreamFifoCC_4 | 56 | 28 | 28 | 0 | 72 | 0 | 0 | 0 |
| (rFifo) | StreamFifoCC_4 | 49 | 21 | 28 | 0 | 56 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_1 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 |
| wFifo | StreamFifoCC_1 | 91 | 63 | 28 | 0 | 69 | 0 | 0 | 0 |
| (wFifo) | StreamFifoCC_1 | 86 | 58 | 28 | 0 | 53 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_8 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| u_mlkem_axi_slave | mlkem_axi_slave | 30043 | 29974 | 0 | 69 | 25426 | 2 | 6 | 24 |
| (u_mlkem_axi_slave) | mlkem_axi_slave | 1278 | 1278 | 0 | 0 | 1064 | 0 | 0 | 0 |
| u_mlkem | mlkem_top | 28768 | 28699 | 0 | 69 | 24362 | 2 | 6 | 24 |
| (u_mlkem) | mlkem_top | 2326 | 2326 | 0 | 0 | 4911 | 0 | 0 | 0 |
| u_bank_a | sd_bram__parameterized0 | 49 | 49 | 0 | 0 | 0 | 1 | 1 | 0 |
| u_bank_se | sd_bram__parameterized1 | 61 | 61 | 0 | 0 | 0 | 1 | 0 | 0 |
| u_bank_t | sd_bram__parameterized2 | 488 | 488 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_c_in_bram | sd_bram | 1291 | 1291 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_cbd | sample_cbd_sync_shared | 2512 | 2512 | 0 | 0 | 3199 | 0 | 0 | 0 |
| u_comp | comp_decomp_sync | 322 | 321 | 0 | 1 | 269 | 0 | 0 | 3 |
| u_ct_bram | sd_bram_6 | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_dkp_bram | sd_bram_7 | 73 | 73 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_ek_bram | sd_bram_8 | 388 | 388 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_keccak | keccak_core | 5622 | 5622 | 0 | 0 | 1606 | 0 | 0 | 0 |
| u_ntt | ntt_core | 8192 | 8149 | 0 | 43 | 3743 | 0 | 0 | 6 |
| (u_ntt) | ntt_core | 6140 | 6124 | 0 | 16 | 3364 | 0 | 0 | 0 |
| u_bf | butterfly_unit_pipe | 1922 | 1896 | 0 | 26 | 224 | 0 | 0 | 3 |
| (u_bf) | butterfly_unit_pipe | 69 | 44 | 0 | 25 | 75 | 0 | 0 | 0 |
| u_barrett | barrett_mul_pipe_9 | 1854 | 1853 | 0 | 1 | 149 | 0 | 0 | 3 |
| u_scl | barrett_mul_pipe | 131 | 130 | 0 | 1 | 155 | 0 | 0 | 3 |
| u_pmul | poly_mul_sync | 2830 | 2805 | 0 | 25 | 6577 | 0 | 0 | 15 |
| (u_pmul) | poly_mul_sync | 2474 | 2474 | 0 | 0 | 6299 | 0 | 0 | 0 |
| u_bc | basecase_mul_pipe | 421 | 396 | 0 | 25 | 278 | 0 | 0 | 15 |
| u_sha3 | sha3_top_shared | 3175 | 3175 | 0 | 0 | 2388 | 0 | 0 | 0 |
| u_snt | sample_ntt_sync_shared | 1439 | 1439 | 0 | 0 | 1669 | 0 | 0 | 0 |
| u_matmul_axi_slave | matmul_axi_slave | 6600 | 6418 | 176 | 6 | 2831 | 0 | 0 | 16 |
| (u_matmul_axi_slave) | matmul_axi_slave | 5796 | 5614 | 176 | 6 | 2303 | 0 | 0 | 0 |
| mult_inst[0].u_mult | pipelined_mult_32x32 | 203 | 203 | 0 | 0 | 132 | 0 | 0 | 4 |
| mult_inst[1].u_mult | pipelined_mult_32x32_2 | 202 | 202 | 0 | 0 | 132 | 0 | 0 | 4 |
| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 202 | 202 | 0 | 0 | 132 | 0 | 0 | 4 |
| mult_inst[3].u_mult | pipelined_mult_32x32_4 | 200 | 200 | 0 | 0 | 132 | 0 | 0 | 4 |
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1673 | 1673 | 0 | 0 | 1476 | 0 | 1 | 0 |
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 687 | 687 | 0 | 0 | 1180 | 0 | 0 | 0 |
| u_core_engine | snix_axi_mm2mm | 988 | 988 | 0 | 0 | 296 | 0 | 1 | 0 |
| (u_core_engine) | snix_axi_mm2mm | 763 | 763 | 0 | 0 | 243 | 0 | 0 | 0 |
| axis_fifo_u0 | snix_axis_fifo | 225 | 225 | 0 | 0 | 53 | 0 | 1 | 0 |
| u_fifo | snix_sync_fifo | 225 | 225 | 0 | 0 | 53 | 0 | 1 | 0 |
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining