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add vivado reports

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FallenSigh
2026-07-08 03:48:37 +08:00
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commit f676fc6e60
58 changed files with 257494 additions and 426061 deletions
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fpga/vivado_reports_withdsp/design_analysis_timing.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 02:58:13 2026
| Host : fedora running 64-bit unknown
| Command : report_design_analysis -timing -file /home/fallensigh/vivado_reports_withdsp/design_analysis_timing.rpt
| Design : soc_top
| Device : xc7a200t
| Design State : Routed
-------------------------------------------------------------------------------------------------------------------------
Report Design Analysis
Table of Contents
-----------------
1. Setup Path Characteristics 1-1
1. Setup Path Characteristics 1-1
---------------------------------
+---------------------------+----------------------------------------------------------------------------------------+
| Characteristics | Path #1 |
+---------------------------+----------------------------------------------------------------------------------------+
| Requirement | 20.000 |
| Path Delay | 15.252 |
| Logic Delay | 7.003(46%) |
| Net Delay | 8.249(54%) |
| Clock Skew | -3.954 |
| Slack | 0.424 |
| Clock Relationship | Safely Timed |
| Logic Levels | 14 |
| Routes | 12 |
| Logical Path | FDCE LUT4 LUT5 LUT6 CARRY4 CARRY4 CARRY4 CARRY4 CARRY4 LUT6 CARRY4 LUT6 LUT6 LUT6 OBUF |
| Start Point Clock | sys_clk |
| End Point Clock | sys_clk |
| DSP Block | None |
| BRAM | None |
| IO Crossings | 3 |
| Config Crossings | 0 |
| SLR Crossings | 0 |
| PBlocks | 0 |
| High Fanout | 80 |
| Dont Touch | 0 |
| Mark Debug | 0 |
| Start Point Pin Primitive | FDCE/C |
| End Point Pin Primitive | base_ram_be_n[3] |
| Start Point Pin | ax_req_q_len_reg[1]/C |
| End Point Pin | base_ram_be_n[3] |
+---------------------------+----------------------------------------------------------------------------------------+
* Bounding box calculated as % of dimensions for the target device (436, 500)