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add vivado reports

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FallenSigh
2026-07-08 03:48:37 +08:00
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 02:58:45 2026
| Host : fedora running 64-bit unknown
| Command : report_design_analysis -complexity -file /home/fallensigh/vivado_reports_withdsp/design_analysis_complexity.rpt
| Design : soc_top
| Device : xc7a200t
| Design State : Routed
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Report Design Analysis
Table of Contents
-----------------
1. Complexity Characteristics (Cells)
1. Complexity Characteristics (Cells)
-------------------------------------
+---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM |
+---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
| (top) | soc_top | 0.49 | 3.76 | 108219 | 710(1.2%) | 5229(8.7%) | 8166(13.7%) | 8097(13.5%) | 8459(14.1%) | 29130(48.7%) | 1175 | 56 | 39 | 6074 | 0 |
| u_axi_axil_adapter | axi_axil_adapter | 0.50 | 5.92 | 1309 | 0(0.0%) | 8(0.7%) | 43(3.8%) | 100(8.9%) | 200(17.7%) | 776(68.9%) | 0 | 0 | 0 | 0 | 0 |
| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 |
| u_cdma_matmul_bridge | cdma_matmul_bridge | 0.56 | 2.22 | 1003 | 1(0.3%) | 66(17.3%) | 39(10.2%) | 174(45.7%) | 13(3.4%) | 88(23.1%) | 0 | 0 | 0 | 0 | 0 |
| u_cpu | core_top | 0.56 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 |
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.53 | 3.70 | 70959 | 286(0.8%) | 3478(9.4%) | 4960(13.4%) | 5940(16.0%) | 4261(11.5%) | 18098(48.9%) | 1169 | 40 | 18 | 5241 | 0 |
| u_matmul_axi_slave | matmul_axi_slave | 0.69 | 3.39 | 10715 | 18(0.2%) | 465(6.4%) | 1463(20.2%) | 312(4.3%) | 1333(18.4%) | 3646(50.4%) | 6 | 16 | 0 | 512 | 0 |
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.45 | 3.68 | 3535 | 136(7.0%) | 181(9.3%) | 328(16.8%) | 258(13.2%) | 297(15.2%) | 750(38.5%) | 0 | 0 | 1 | 4 | 0 |
+---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
* Complexity Ranges
** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal, 0.65 - 0.85 -> high, 0.85 - 1.0 -> very high
*** -* -> Not computable as cell size is very small