add vivado reports
This commit is contained in:
28
fpga/vivado_reports_withdsp/clock_interaction.rpt
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28
fpga/vivado_reports_withdsp/clock_interaction.rpt
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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--------------------------------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Wed Jul 8 02:57:58 2026
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| Host : fedora running 64-bit unknown
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| Command : report_clock_interaction -file /home/fallensigh/vivado_reports_withdsp/clock_interaction.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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--------------------------------------------------------------------------------------------------------------
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Clock Interaction Report
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Clock Interaction Table
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-----------------------
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WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock
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From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints
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----------------- ----------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- -------------------
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cpu_clk cpu_clk rise - rise 1.14 0.00 0 17264 30.32 Clean Timed
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cpu_clk sys_clk 0 162 Ignored Asynchronous Groups
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mlkem_clk_clk_pll mlkem_clk_clk_pll rise - rise 12.91 0.00 0 74882 40.00 Clean Timed
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mlkem_clk_clk_pll sys_clk rise - rise 16.72 0.00 0 61 20.00 Clean Timed
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sys_clk cpu_clk 0 59 Ignored Asynchronous Groups
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sys_clk mlkem_clk_clk_pll rise - rise 8.52 0.00 0 112 20.00 Clean Timed
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sys_clk sys_clk rise - rise 0.42 0.00 0 23732 20.00 Clean Timed
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76
fpga/vivado_reports_withdsp/clocks.rpt
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76
fpga/vivado_reports_withdsp/clocks.rpt
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Wed Jul 8 02:57:58 2026
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| Host : fedora running 64-bit unknown
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| Command : report_clocks -file /home/fallensigh/vivado_reports_withdsp/clocks.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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----------------------------------------------------------------------------------------
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Clock Report
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Attributes
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P: Propagated
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G: Generated
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A: Auto-derived
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R: Renamed
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V: Virtual
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I: Inverted
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S: Pin phase-shifted with Latency mode
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Clock Period(ns) Waveform(ns) Attributes Sources
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clk 20.000 {0.000 10.000} P {clk}
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clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
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cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
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mlkem_clk_clk_pll 40.000 {0.000 20.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
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sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
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====================================================
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Generated Clocks
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====================================================
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Generated Clock : clkfbout_clk_pll
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Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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Master Clock : clk
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Multiply By : 1
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Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
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Generated Clock : cpu_clk
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Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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Master Clock : clk
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Edges : {1 2 3}
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Edge Shifts(ns) : {0.000 5.161 10.323}
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Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
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Generated Clock : mlkem_clk_clk_pll
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Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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Master Clock : clk
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Edges : {1 2 3}
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Edge Shifts(ns) : {0.000 10.000 20.000}
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Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
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Generated Clock : sys_clk
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Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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Master Clock : clk
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Multiply By : 1
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Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
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====================================================
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User Uncertainty
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====================================================
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====================================================
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User Jitter
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====================================================
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Clock Jitter(ns)
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clk 0.200
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37
fpga/vivado_reports_withdsp/design_analysis_complexity.rpt
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37
fpga/vivado_reports_withdsp/design_analysis_complexity.rpt
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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---------------------------------------------------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Wed Jul 8 02:58:45 2026
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| Host : fedora running 64-bit unknown
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| Command : report_design_analysis -complexity -file /home/fallensigh/vivado_reports_withdsp/design_analysis_complexity.rpt
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| Design : soc_top
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| Device : xc7a200t
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| Design State : Routed
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---------------------------------------------------------------------------------------------------------------------------------
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Report Design Analysis
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Table of Contents
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-----------------
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1. Complexity Characteristics (Cells)
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1. Complexity Characteristics (Cells)
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-------------------------------------
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+---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
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| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM |
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+---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
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| (top) | soc_top | 0.49 | 3.76 | 108219 | 710(1.2%) | 5229(8.7%) | 8166(13.7%) | 8097(13.5%) | 8459(14.1%) | 29130(48.7%) | 1175 | 56 | 39 | 6074 | 0 |
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| u_axi_axil_adapter | axi_axil_adapter | 0.50 | 5.92 | 1309 | 0(0.0%) | 8(0.7%) | 43(3.8%) | 100(8.9%) | 200(17.7%) | 776(68.9%) | 0 | 0 | 0 | 0 | 0 |
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| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 |
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| u_cdma_matmul_bridge | cdma_matmul_bridge | 0.56 | 2.22 | 1003 | 1(0.3%) | 66(17.3%) | 39(10.2%) | 174(45.7%) | 13(3.4%) | 88(23.1%) | 0 | 0 | 0 | 0 | 0 |
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| u_cpu | core_top | 0.56 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 |
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| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.53 | 3.70 | 70959 | 286(0.8%) | 3478(9.4%) | 4960(13.4%) | 5940(16.0%) | 4261(11.5%) | 18098(48.9%) | 1169 | 40 | 18 | 5241 | 0 |
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| u_matmul_axi_slave | matmul_axi_slave | 0.69 | 3.39 | 10715 | 18(0.2%) | 465(6.4%) | 1463(20.2%) | 312(4.3%) | 1333(18.4%) | 3646(50.4%) | 6 | 16 | 0 | 512 | 0 |
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| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.45 | 3.68 | 3535 | 136(7.0%) | 181(9.3%) | 328(16.8%) | 258(13.2%) | 297(15.2%) | 750(38.5%) | 0 | 0 | 1 | 4 | 0 |
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+---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
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* Complexity Ranges
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** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal, 0.65 - 0.85 -> high, 0.85 - 1.0 -> very high
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*** -* -> Not computable as cell size is very small
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52
fpga/vivado_reports_withdsp/design_analysis_timing.rpt
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52
fpga/vivado_reports_withdsp/design_analysis_timing.rpt
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@@ -0,0 +1,52 @@
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Wed Jul 8 02:58:13 2026
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| Host : fedora running 64-bit unknown
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| Command : report_design_analysis -timing -file /home/fallensigh/vivado_reports_withdsp/design_analysis_timing.rpt
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| Design : soc_top
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| Device : xc7a200t
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| Design State : Routed
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-------------------------------------------------------------------------------------------------------------------------
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Report Design Analysis
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Table of Contents
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-----------------
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1. Setup Path Characteristics 1-1
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1. Setup Path Characteristics 1-1
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---------------------------------
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+---------------------------+----------------------------------------------------------------------------------------+
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| Characteristics | Path #1 |
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+---------------------------+----------------------------------------------------------------------------------------+
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| Requirement | 20.000 |
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| Path Delay | 15.252 |
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| Logic Delay | 7.003(46%) |
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| Net Delay | 8.249(54%) |
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| Clock Skew | -3.954 |
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| Slack | 0.424 |
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| Clock Relationship | Safely Timed |
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| Logic Levels | 14 |
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| Routes | 12 |
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| Logical Path | FDCE LUT4 LUT5 LUT6 CARRY4 CARRY4 CARRY4 CARRY4 CARRY4 LUT6 CARRY4 LUT6 LUT6 LUT6 OBUF |
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| Start Point Clock | sys_clk |
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| End Point Clock | sys_clk |
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| DSP Block | None |
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| BRAM | None |
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| IO Crossings | 3 |
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| Config Crossings | 0 |
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| SLR Crossings | 0 |
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| PBlocks | 0 |
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| High Fanout | 80 |
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| Dont Touch | 0 |
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| Mark Debug | 0 |
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| Start Point Pin Primitive | FDCE/C |
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| End Point Pin Primitive | base_ram_be_n[3] |
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| Start Point Pin | ax_req_q_len_reg[1]/C |
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| End Point Pin | base_ram_be_n[3] |
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+---------------------------+----------------------------------------------------------------------------------------+
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* Bounding box calculated as % of dimensions for the target device (436, 500)
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911
fpga/vivado_reports_withdsp/drc.rpt
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911
fpga/vivado_reports_withdsp/drc.rpt
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@@ -0,0 +1,911 @@
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------
|
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
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| Date : Wed Jul 8 02:57:43 2026
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| Host : fedora running 64-bit unknown
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| Command : report_drc -file /home/fallensigh/vivado_reports_withdsp/drc.rpt
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| Design : soc_top
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| Device : xc7a200tfbg676-1
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| Speed File : -1
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| Design State : Fully Routed
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------------------------------------------------------------------------------------
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Report DRC
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: netlist
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Floorplan: impl_1
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Design limits: <entire design considered>
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Ruledeck: default
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Max violations: <unlimited>
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Violations found: 174
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+-----------+----------+----------------------------+------------+
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| Rule | Severity | Description | Violations |
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+-----------+----------+----------------------------+------------+
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| CHECK-3 | Warning | Report rule limit reached | 2 |
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| DPIP-1 | Warning | Input pipelining | 47 |
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| DPOP-1 | Warning | PREG Output pipelining | 29 |
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| DPOP-2 | Warning | MREG Output pipelining | 56 |
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| REQP-1839 | Warning | RAMB36 async control check | 20 |
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| REQP-1840 | Warning | RAMB18 async control check | 20 |
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+-----------+----------+----------------------------+------------+
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2. REPORT DETAILS
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-----------------
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CHECK-3#1 Warning
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Report rule limit reached
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REQP-1839 rule limit reached: 20 violations have been found.
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Related violations: <none>
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CHECK-3#2 Warning
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Report rule limit reached
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REQP-1840 rule limit reached: 20 violations have been found.
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Related violations: <none>
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DPIP-1#1 Warning
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Input pipelining
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DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#2 Warning
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Input pipelining
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DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#3 Warning
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Input pipelining
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DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#4 Warning
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Input pipelining
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DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#5 Warning
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Input pipelining
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DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#6 Warning
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Input pipelining
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DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
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Related violations: <none>
|
||||
|
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DPIP-1#7 Warning
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Input pipelining
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DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
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Related violations: <none>
|
||||
|
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DPIP-1#8 Warning
|
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Input pipelining
|
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DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
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Related violations: <none>
|
||||
|
||||
DPIP-1#9 Warning
|
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Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#10 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#11 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#12 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#13 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#14 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#15 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#16 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#17 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#18 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#19 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#20 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#21 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#22 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#23 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#24 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#25 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#26 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#27 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#28 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#29 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#30 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#31 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#32 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#33 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#34 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#35 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#36 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#37 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#38 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#39 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#40 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#41 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#42 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#43 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#44 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#45 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#46 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#47 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#1 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#2 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#3 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#4 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#5 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#6 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#7 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#8 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#9 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#10 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#11 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#12 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#13 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#14 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#15 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#16 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#17 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#18 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#19 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#20 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#21 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#22 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16 output u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#23 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#24 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0 output u_matmul_axi_slave/mult_inst[1].u_mult/prod0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#25 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#26 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0 output u_matmul_axi_slave/mult_inst[2].u_mult/prod0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#27 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#28 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0 output u_matmul_axi_slave/mult_inst[3].u_mult/prod0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#29 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#1 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#2 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#3 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#4 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#5 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#6 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#7 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#8 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#9 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#10 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#11 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#12 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#13 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#14 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#15 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#16 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#17 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#18 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#19 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#20 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#21 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#22 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#23 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#24 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#25 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#26 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#27 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#28 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#29 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#30 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#31 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#32 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#33 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#34 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#35 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#36 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#37 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#38 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#39 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#40 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#41 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16 multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#42 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#43 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#44 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#45 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0 multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#46 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#47 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#48 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#49 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0 multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#50 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#51 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#52 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#53 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0 multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#54 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#55 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#56 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#1 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#2 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#3 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#4 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#5 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#6 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#7 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#8 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#9 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#10 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#11 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#12 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#13 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#14 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#15 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#16 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#17 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#18 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#19 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#20 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#1 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#2 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#3 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#4 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#5 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#6 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#7 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#8 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#9 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#10 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#11 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#12 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#13 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#14 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#15 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#16 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#17 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#18 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#19 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#20 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
221
fpga/vivado_reports_withdsp/high_fanout.rpt
Normal file
221
fpga/vivado_reports_withdsp/high_fanout.rpt
Normal file
@@ -0,0 +1,221 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 02:57:58 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/vivado_reports_withdsp/high_fanout.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
High Fan-out Nets Information
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
| Net Name | Fanout | Driver Type |
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/delay_reg[1] | 24229 | LUT5 |
|
||||
| pll_clk.u_clk_pll/inst/sys_clk | 9603 | BUFG |
|
||||
| pll_clk.u_rst_sys/prst | 3749 | LUT1 |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_0 | 2140 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mb_en | 2121 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0] | 2048 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 | 1611 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0] | 1608 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state[2]_i_3_n_0 | 1604 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 | 1601 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[1] | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[2] | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 | 1600 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1122 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE |
|
||||
| pll_clk.u_rst_mlkem/delay_reg[1]_0 | 1066 | LUT1 |
|
||||
| u_cpu/reset | 799 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sel0[3] | 773 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0] | 769 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1] | 769 | CARRY4 |
|
||||
| u_cpu/u_mul/E[0] | 716 | LUT1 |
|
||||
| u_matmul_axi_slave/w_addr[2] | 667 | FDRE |
|
||||
| u_matmul_axi_slave/w_addr[3] | 604 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[0]_0[0] | 512 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sel0[4] | 388 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2] | 385 | CARRY4 |
|
||||
| u_cpu/wb_stage/w_index[0] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[1] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[2] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[3] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[4] | 358 | LUT6 |
|
||||
| u_matmul_axi_slave/Q[0] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[0] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[1] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[2] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[3] | 354 | FDRE |
|
||||
| u_cpu/wb_stage/we_0 | 324 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 290 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_4 | 288 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[4] | 272 | FDCE |
|
||||
| u_matmul_axi_slave/sel0[1] | 264 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 263 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 263 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 262 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 262 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 261 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[0] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[10] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[11] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[1] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[2] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[5] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[6] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[7] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[8] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[9] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/E[0] | 256 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 |
|
||||
| u_matmul_axi_slave/mult_inst[0].u_mult/E[0] | 256 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT3 |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[0] | 244 | FDSE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[7] | 239 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[2] | 238 | FDCE |
|
||||
| u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 |
|
||||
| u_cpu/mem_stage/E[0] | 234 | LUT6 |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/axiOut_7_wstrb[0] | 232 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[382]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[510]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[5] | 223 | FDCE |
|
||||
| u_matmul_axi_slave/w_addr[5] | 223 | FDRE |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 |
|
||||
| u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 |
|
||||
| u_cpu/u_csr/tlbw_r_tlbidx[2] | 210 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0] | 203 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[1] | 203 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2] | 196 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[6] | 195 | FDCE |
|
||||
| u_cpu/wb_stage/Q[33] | 194 | FDRE |
|
||||
| u_cpu/wb_stage/Q[34] | 194 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5] | 194 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3] | 193 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4] | 188 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r_reg[3]_rep_n_0 | 187 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1] | 184 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6] | 184 | FDCE |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/_zz_ram_port1_reg[32] | 182 | LUT4 |
|
||||
| u_cpu/wb_stage/ws_valid_reg_0 | 180 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r_reg[5]_rep_n_0 | 180 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1] | 179 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[0] | 177 | FDCE |
|
||||
| u_matmul_axi_slave/p_0_in__0 | 176 | LUT4 |
|
||||
| u_matmul_axi_slave/p_0_in__0__0 | 176 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 174 | FDCE |
|
||||
| u_cpu/wb_stage/Q[37] | 173 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_out[0] | 169 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[2]_rep__0_n_0 | 168 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[4] | 165 | FDCE |
|
||||
| u_cpu/wb_stage/Q[32] | 164 | FDRE |
|
||||
| u_cpu/wb_stage/Q[35] | 163 | FDRE |
|
||||
| u_cpu/wb_stage/Q[36] | 162 | FDRE |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0 | 161 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[6] | 161 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0] | 160 | FDCE |
|
||||
| u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]_0 | 160 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[3] | 158 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3] | 156 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_5 | 153 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[0] | 153 | FDCE |
|
||||
| u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0 | 151 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep_n_0 | 151 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[7] | 151 | FDCE |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1 | 150 | CARRY4 |
|
||||
| u_cpu/dcache/awaddr[31]_i_3_n_0 | 148 | LUT2 |
|
||||
| u_cpu/dcache/awaddr[31]_i_4_n_0 | 148 | LUT2 |
|
||||
| u_matmul_axi_slave/mult_inst[3].u_mult/FSM_sequential_state_reg | 148 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 146 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_57_n_0 | 144 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[1] | 142 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[4] | 141 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[5] | 141 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[6] | 141 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[7] | 141 | FDCE |
|
||||
| u_cpu/dcache/write_buffer_state | 140 | FDRE |
|
||||
| u_matmul_axi_slave/mult_inst[3].u_mult/cur_bank_reg_rep | 140 | LUT3 |
|
||||
| u_matmul_axi_slave/mult_inst[3].u_mult/req_0_reg | 140 | LUT3 |
|
||||
| u_snix_axil_cdma_mux_8ch/ADDRA[0] | 140 | LUT6 |
|
||||
| u_cpu/u_csr/tlbw_r_tlbidx[0] | 139 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[3] | 139 | FDCE |
|
||||
| u_matmul_axi_slave/sel0[0] | 139 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[3] | 138 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[2] | 138 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]_i_5_n_7 | 137 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_6_11_i_34_n_0 | 137 | LUT4 |
|
||||
| u_cpu/u_csr/tlbw_r_tlbidx[1] | 136 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1080]_i_5_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1081]_i_5_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1082]_i_5_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1083]_i_5_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1084]_i_6_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_3_n_0 | 136 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_9_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1087]_i_3_n_0 | 136 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/rl_idx[3] | 136 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 | 136 | FDCE |
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
|
||||
|
||||
1653
fpga/vivado_reports_withdsp/methodology.rpt
Normal file
1653
fpga/vivado_reports_withdsp/methodology.rpt
Normal file
File diff suppressed because it is too large
Load Diff
5918
fpga/vivado_reports_withdsp/mlkem_clk_timing.rpt
Normal file
5918
fpga/vivado_reports_withdsp/mlkem_clk_timing.rpt
Normal file
File diff suppressed because it is too large
Load Diff
179
fpga/vivado_reports_withdsp/power.rpt
Normal file
179
fpga/vivado_reports_withdsp/power.rpt
Normal file
@@ -0,0 +1,179 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 02:58:09 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_power -file /home/fallensigh/vivado_reports_withdsp/power.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Design State : routed
|
||||
| Grade : commercial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
--------------------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
1.1 On-Chip Components
|
||||
1.2 Power Supply Summary
|
||||
1.3 Confidence Level
|
||||
2. Settings
|
||||
2.1 Environment
|
||||
2.2 Clock Constraints
|
||||
3. Detailed Reports
|
||||
3.1 By Hierarchy
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 0.512 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 0.371 |
|
||||
| Device Static (W) | 0.141 |
|
||||
| Effective TJA (C/W) | 1.9 |
|
||||
| Max Ambient (C) | 84.0 |
|
||||
| Junction Temperature (C) | 26.0 |
|
||||
| Confidence Level | Low |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
| Design Nets Matched | NA |
|
||||
+--------------------------+--------------+
|
||||
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
||||
|
||||
|
||||
1.1 On-Chip Components
|
||||
----------------------
|
||||
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| Clocks | 0.037 | 7 | --- | --- |
|
||||
| Slice Logic | 0.056 | 109753 | --- | --- |
|
||||
| LUT as Logic | 0.052 | 56469 | 133800 | 42.20 |
|
||||
| CARRY4 | 0.001 | 1802 | 33450 | 5.39 |
|
||||
| Register | <0.001 | 39141 | 267600 | 14.63 |
|
||||
| LUT as Shift Register | <0.001 | 1175 | 46200 | 2.54 |
|
||||
| LUT as Distributed RAM | <0.001 | 740 | 46200 | 1.60 |
|
||||
| F7/F8 Muxes | <0.001 | 6090 | 133800 | 4.55 |
|
||||
| Others | 0.000 | 334 | --- | --- |
|
||||
| Signals | 0.095 | 78236 | --- | --- |
|
||||
| Block RAM | 0.018 | 23.5 | 365 | 6.44 |
|
||||
| PLL | 0.132 | 1 | 10 | 10.00 |
|
||||
| DSPs | 0.010 | 56 | 740 | 7.57 |
|
||||
| I/O | 0.023 | 202 | 400 | 50.50 |
|
||||
| Static Power | 0.141 | | | |
|
||||
| Total | 0.512 | | | |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
1.2 Power Supply Summary
|
||||
------------------------
|
||||
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Vccint | 1.000 | 0.257 | 0.225 | 0.032 |
|
||||
| Vccaux | 1.800 | 0.099 | 0.069 | 0.031 |
|
||||
| Vcco33 | 3.300 | 0.011 | 0.006 | 0.005 |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccbram | 1.000 | 0.003 | 0.001 | 0.001 |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
|
||||
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | High | User specified more than 95% of clocks | |
|
||||
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Low | | |
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
2. Settings
|
||||
-----------
|
||||
|
||||
2.1 Environment
|
||||
---------------
|
||||
|
||||
+-----------------------+--------------------------+
|
||||
| Ambient Temp (C) | 25.0 |
|
||||
| ThetaJA (C/W) | 1.9 |
|
||||
| Airflow (LFM) | 250 |
|
||||
| Heat Sink | medium (Medium Profile) |
|
||||
| ThetaSA (C/W) | 3.4 |
|
||||
| Board Selection | medium (10"x10") |
|
||||
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
||||
| Board Temperature (C) | 25.0 |
|
||||
+-----------------------+--------------------------+
|
||||
|
||||
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+-------------------+------------------------------------------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+-------------------+------------------------------------------+-----------------+
|
||||
| clk | clk | 20.0 |
|
||||
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
|
||||
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
|
||||
| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 40.0 |
|
||||
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
|
||||
+-------------------+------------------------------------------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
-------------------
|
||||
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+----------------------------+-----------+
|
||||
| Name | Power (W) |
|
||||
+----------------------------+-----------+
|
||||
| soc_top | 0.371 |
|
||||
| pll_clk.u_clk_pll | 0.133 |
|
||||
| inst | 0.133 |
|
||||
| u_Axi_CDC | 0.002 |
|
||||
| wFifo | 0.001 |
|
||||
| u_axi_uart_controller | 0.001 |
|
||||
| u_cdma_matmul_bridge | 0.001 |
|
||||
| u_cpu | 0.017 |
|
||||
| addr_trans | 0.002 |
|
||||
| tlb_entry | 0.002 |
|
||||
| btb | 0.003 |
|
||||
| dcache | 0.004 |
|
||||
| icache | 0.005 |
|
||||
| u_csr | 0.001 |
|
||||
| u_fft_mlkem_axi_slave | 0.134 |
|
||||
| u_fft_controller | 0.032 |
|
||||
| u_FFT | 0.030 |
|
||||
| u_mlkem_axi_cdc | 0.001 |
|
||||
| u_mlkem_axi_slave | 0.101 |
|
||||
| u_mlkem | 0.098 |
|
||||
| u_matmul_axi_slave | 0.047 |
|
||||
| u_snix_axil_cdma_mux_8ch | 0.008 |
|
||||
| u_core_engine | 0.004 |
|
||||
| axis_fifo_u0 | 0.002 |
|
||||
+----------------------------+-----------+
|
||||
|
||||
|
||||
BIN
fpga/vivado_reports_withdsp/resource.png
Normal file
BIN
fpga/vivado_reports_withdsp/resource.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 45 KiB |
12
fpga/vivado_reports_withdsp/route_status.rpt
Normal file
12
fpga/vivado_reports_withdsp/route_status.rpt
Normal file
@@ -0,0 +1,12 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
# of logical nets.......................... : 116330 :
|
||||
# of nets not needing routing.......... : 38083 :
|
||||
# of internally routed nets........ : 37618 :
|
||||
# of nets with no loads............ : 465 :
|
||||
# of routable nets..................... : 78247 :
|
||||
# of fully routed nets............. : 78247 :
|
||||
# of nets with routing errors.......... : 0 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
16762
fpga/vivado_reports_withdsp/timing_hold_paths.rpt
Normal file
16762
fpga/vivado_reports_withdsp/timing_hold_paths.rpt
Normal file
File diff suppressed because it is too large
Load Diff
33570
fpga/vivado_reports_withdsp/timing_setup_paths.rpt
Normal file
33570
fpga/vivado_reports_withdsp/timing_setup_paths.rpt
Normal file
File diff suppressed because it is too large
Load Diff
39192
fpga/vivado_reports_withdsp/timing_summary_full.rpt
Normal file
39192
fpga/vivado_reports_withdsp/timing_summary_full.rpt
Normal file
File diff suppressed because it is too large
Load Diff
32172
fpga/vivado_reports_withdsp/timing_summary_hold_full.rpt
Normal file
32172
fpga/vivado_reports_withdsp/timing_summary_hold_full.rpt
Normal file
File diff suppressed because it is too large
Load Diff
237
fpga/vivado_reports_withdsp/utilization.rpt
Normal file
237
fpga/vivado_reports_withdsp/utilization.rpt
Normal file
@@ -0,0 +1,237 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 02:57:49 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -file /home/fallensigh/vivado_reports_withdsp/utilization.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Routed
|
||||
--------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Slice Logic Distribution
|
||||
3. Memory
|
||||
4. DSP
|
||||
5. IO and GT Specific
|
||||
6. Clocking
|
||||
7. Specific Feature
|
||||
8. Primitives
|
||||
9. Black Boxes
|
||||
10. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Slice LUTs | 53691 | 0 | 133800 | 40.13 |
|
||||
| LUT as Logic | 51836 | 0 | 133800 | 38.74 |
|
||||
| LUT as Memory | 1855 | 0 | 46200 | 4.02 |
|
||||
| LUT as Distributed RAM | 740 | 0 | | |
|
||||
| LUT as Shift Register | 1115 | 0 | | |
|
||||
| Slice Registers | 39141 | 0 | 267600 | 14.63 |
|
||||
| Register as Flip Flop | 39141 | 0 | 267600 | 14.63 |
|
||||
| Register as Latch | 0 | 0 | 267600 | 0.00 |
|
||||
| F7 Muxes | 4519 | 0 | 66900 | 6.75 |
|
||||
| F8 Muxes | 1571 | 0 | 33450 | 4.70 |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 24 | Yes | - | Set |
|
||||
| 26265 | Yes | - | Reset |
|
||||
| 126 | Yes | Set | - |
|
||||
| 12726 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Slice Logic Distribution
|
||||
---------------------------
|
||||
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
| Slice | 18732 | 0 | 33450 | 56.00 |
|
||||
| SLICEL | 12122 | 0 | | |
|
||||
| SLICEM | 6610 | 0 | | |
|
||||
| LUT as Logic | 51836 | 0 | 133800 | 38.74 |
|
||||
| using O5 output only | 4 | | | |
|
||||
| using O6 output only | 43877 | | | |
|
||||
| using O5 and O6 | 7955 | | | |
|
||||
| LUT as Memory | 1855 | 0 | 46200 | 4.02 |
|
||||
| LUT as Distributed RAM | 740 | 0 | | |
|
||||
| using O5 output only | 0 | | | |
|
||||
| using O6 output only | 60 | | | |
|
||||
| using O5 and O6 | 680 | | | |
|
||||
| LUT as Shift Register | 1115 | 0 | | |
|
||||
| using O5 output only | 47 | | | |
|
||||
| using O6 output only | 1008 | | | |
|
||||
| using O5 and O6 | 60 | | | |
|
||||
| Slice Registers | 39141 | 0 | 267600 | 14.63 |
|
||||
| Register driven from within the Slice | 19059 | | | |
|
||||
| Register driven from outside the Slice | 20082 | | | |
|
||||
| LUT in front of the register is unused | 11401 | | | |
|
||||
| LUT in front of the register is used | 8681 | | | |
|
||||
| Unique Control Sets | 1440 | | 33450 | 4.30 |
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
|
||||
3. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 23.5 | 0 | 365 | 6.44 |
|
||||
| RAMB36/FIFO* | 8 | 0 | 365 | 2.19 |
|
||||
| RAMB36E1 only | 8 | | | |
|
||||
| RAMB18 | 31 | 0 | 730 | 4.25 |
|
||||
| RAMB18E1 only | 31 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
4. DSP
|
||||
------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| DSPs | 56 | 0 | 740 | 7.57 |
|
||||
| DSP48E1 only | 56 | | | |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 202 | 202 | 400 | 50.50 |
|
||||
| IOB Master Pads | 97 | | | |
|
||||
| IOB Slave Pads | 102 | | | |
|
||||
| Bonded IPADs | 0 | 0 | 26 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 16 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 10 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 384 | 0.00 |
|
||||
| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 400 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 400 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 4 | 0 | 32 | 12.50 |
|
||||
| BUFIO | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
|
||||
| BUFMRCE | 0 | 0 | 20 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 120 | 0.00 |
|
||||
| BUFR | 0 | 0 | 40 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
8. Primitives
|
||||
-------------
|
||||
|
||||
+-----------+-------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+-----------+-------+---------------------+
|
||||
| LUT6 | 29130 | LUT |
|
||||
| FDCE | 26265 | Flop & Latch |
|
||||
| FDRE | 12726 | Flop & Latch |
|
||||
| LUT5 | 8459 | LUT |
|
||||
| LUT3 | 8166 | LUT |
|
||||
| LUT4 | 8097 | LUT |
|
||||
| LUT2 | 5229 | LUT |
|
||||
| MUXF7 | 4519 | MuxFx |
|
||||
| CARRY4 | 1802 | CarryLogic |
|
||||
| MUXF8 | 1571 | MuxFx |
|
||||
| RAMD32 | 1060 | Distributed Memory |
|
||||
| SRLC32E | 992 | Distributed Memory |
|
||||
| LUT1 | 710 | LUT |
|
||||
| RAMS32 | 328 | Distributed Memory |
|
||||
| SRL16E | 183 | Distributed Memory |
|
||||
| FDSE | 126 | Flop & Latch |
|
||||
| IBUF | 104 | IO |
|
||||
| OBUF | 98 | IO |
|
||||
| OBUFT | 66 | IO |
|
||||
| DSP48E1 | 56 | Block Arithmetic |
|
||||
| RAMD64E | 32 | Distributed Memory |
|
||||
| RAMB18E1 | 31 | Block Memory |
|
||||
| FDPE | 24 | Flop & Latch |
|
||||
| RAMB36E1 | 8 | Block Memory |
|
||||
| BUFG | 4 | Clock |
|
||||
| PLLE2_ADV | 1 | Clock |
|
||||
+-----------+-------+---------------------+
|
||||
|
||||
|
||||
9. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
10. Instantiated Netlists
|
||||
-------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
| clk_pll | 1 |
|
||||
+----------+------+
|
||||
|
||||
|
||||
276
fpga/vivado_reports_withdsp/utilization_hier.rpt
Normal file
276
fpga/vivado_reports_withdsp/utilization_hier.rpt
Normal file
@@ -0,0 +1,276 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 02:57:50 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -hierarchical -file /home/fallensigh/vivado_reports_withdsp/utilization_hier.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Utilization by Hierarchy
|
||||
|
||||
1. Utilization by Hierarchy
|
||||
---------------------------
|
||||
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
| soc_top | (top) | 53691 | 51836 | 740 | 1115 | 39141 | 8 | 31 | 56 |
|
||||
| (soc_top) | (top) | 102 | 46 | 56 | 0 | 9 | 0 | 0 | 0 |
|
||||
| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| inst | clk_pll__clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_mlkem | rst_sync_0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_sys | rst_sync_1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 381 | 381 | 0 | 0 | 151 | 0 | 0 | 0 |
|
||||
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 6 | 6 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_82 | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_65 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_81 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_66 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_80 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_67 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_79 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_76 | 27 | 27 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_77 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_78 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_73 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_74 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_75 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_70 | 20 | 20 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_71 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_72 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 23 | 23 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 96 | 96 | 0 | 0 | 25 | 0 | 0 | 0 |
|
||||
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 75 | 75 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1_69 | 21 | 21 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 40 | 40 | 0 | 0 | 18 | 0 | 0 | 0 |
|
||||
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 20 | 20 | 0 | 0 | 16 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1_68 | 21 | 21 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 53 | 53 | 0 | 0 | 17 | 0 | 0 | 0 |
|
||||
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 38 | 38 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
|
||||
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 32 | 32 | 0 | 0 | 14 | 0 | 0 | 0 |
|
||||
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 20 | 20 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_Axi_CDC | Axi_CDC | 412 | 284 | 128 | 0 | 317 | 0 | 0 | 0 |
|
||||
| arFifo | StreamFifoCC_3_48 | 185 | 149 | 36 | 0 | 77 | 0 | 0 | 0 |
|
||||
| (arFifo) | StreamFifoCC_3_48 | 180 | 144 | 36 | 0 | 65 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_63 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_64 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| awFifo | StreamFifoCC_49 | 102 | 66 | 36 | 0 | 79 | 0 | 0 | 0 |
|
||||
| (awFifo) | StreamFifoCC_49 | 98 | 62 | 36 | 0 | 65 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_10_60 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_61 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_62 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| bFifo | StreamFifoCC_2_50 | 14 | 14 | 0 | 0 | 26 | 0 | 0 | 0 |
|
||||
| (bFifo) | StreamFifoCC_2_50 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_5_57 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_4_58 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_6_59 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| rFifo | StreamFifoCC_4_51 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 |
|
||||
| (rFifo) | StreamFifoCC_4_51 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_55 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_1_56 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| wFifo | StreamFifoCC_1_52 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 |
|
||||
| (wFifo) | StreamFifoCC_1_52 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_7_53 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_8_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_axi_axil_adapter | axi_axil_adapter | 1072 | 1072 | 0 | 0 | 173 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 497 | 497 | 0 | 0 | 85 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 575 | 575 | 0 | 0 | 88 | 0 | 0 | 0 |
|
||||
| u_axi_dvi | axi_dvi | 284 | 284 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_axi_ram | axi_wrap_ram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_sram_sp | axi2sram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_uart_controller | axi_uart_controller | 683 | 667 | 16 | 0 | 457 | 0 | 0 | 0 |
|
||||
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 251 | 251 | 0 | 0 | 120 | 0 | 0 | 0 |
|
||||
| uart0 | UART_TOP | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| regs | uart_regs | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| (regs) | uart_regs | 119 | 119 | 0 | 0 | 155 | 0 | 0 | 0 |
|
||||
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 |
|
||||
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
|
||||
| fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 |
|
||||
| (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 |
|
||||
| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 |
|
||||
| (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 |
|
||||
| fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 |
|
||||
| (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_cdma_matmul_bridge | cdma_matmul_bridge | 250 | 250 | 0 | 0 | 578 | 0 | 0 | 0 |
|
||||
| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 |
|
||||
| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 |
|
||||
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
|
||||
| u_cpu | core_top | 8556 | 8304 | 252 | 0 | 5591 | 0 | 20 | 0 |
|
||||
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
|
||||
| addr_trans | addr_trans | 2247 | 2107 | 140 | 0 | 1244 | 0 | 0 | 0 |
|
||||
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
|
||||
| tlb_entry | tlb_entry | 2247 | 2107 | 140 | 0 | 1204 | 0 | 0 | 0 |
|
||||
| axi_bridge | axi_bridge | 39 | 39 | 0 | 0 | 214 | 0 | 0 | 0 |
|
||||
| btb | btb | 1048 | 968 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| (btb) | btb | 1045 | 965 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| dcache | dcache | 552 | 520 | 32 | 0 | 146 | 0 | 10 | 0 |
|
||||
| (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_46 | 43 | 43 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| exe_stage | exe_stage | 665 | 665 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| (exe_stage) | exe_stage | 634 | 634 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| icache | icache | 234 | 234 | 0 | 0 | 55 | 0 | 10 | 0 |
|
||||
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_35 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| id_stage | id_stage | 1052 | 1052 | 0 | 0 | 108 | 0 | 0 | 0 |
|
||||
| if_stage | if_stage | 134 | 134 | 0 | 0 | 173 | 0 | 0 | 0 |
|
||||
| mem_stage | mem_stage | 115 | 115 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
|
||||
| u_div | div | 142 | 142 | 0 | 0 | 107 | 0 | 0 | 0 |
|
||||
| u_mul | mul | 933 | 933 | 0 | 0 | 592 | 0 | 0 | 0 |
|
||||
| wb_stage | wb_stage | 689 | 689 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 32945 | 31724 | 112 | 1109 | 26787 | 8 | 10 | 40 |
|
||||
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| u_fft_controller | fft_controller | 2647 | 1607 | 0 | 1040 | 1083 | 6 | 4 | 16 |
|
||||
| (u_fft_controller) | fft_controller | 123 | 123 | 0 | 0 | 100 | 0 | 0 | 0 |
|
||||
| u_FFT | FFT | 2495 | 1455 | 0 | 1040 | 983 | 6 | 0 | 16 |
|
||||
| SU1 | SdfUnit | 1070 | 302 | 0 | 768 | 197 | 2 | 0 | 4 |
|
||||
| (SU1) | SdfUnit | 205 | 205 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_25 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer | 562 | 50 | 0 | 512 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized0 | 256 | 0 | 0 | 256 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| TW | Twiddle_27 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU2 | SdfUnit__parameterized0 | 492 | 300 | 0 | 192 | 197 | 2 | 0 | 4 |
|
||||
| (SU2) | SdfUnit__parameterized0 | 73 | 73 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_22 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| TW | Twiddle_23 | 3 | 3 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU3 | SdfUnit__parameterized1 | 347 | 299 | 0 | 48 | 197 | 0 | 0 | 4 |
|
||||
| (SU3) | SdfUnit__parameterized1 | 75 | 75 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_17 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_19 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| SU4 | SdfUnit__parameterized2 | 327 | 295 | 0 | 32 | 197 | 2 | 0 | 4 |
|
||||
| (SU4) | SdfUnit__parameterized2 | 69 | 69 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_15 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| TW | Twiddle | 2 | 2 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU5 | SdfUnit__parameterized3 | 260 | 260 | 0 | 0 | 195 | 0 | 0 | 0 |
|
||||
| (SU5) | SdfUnit__parameterized3 | 68 | 68 | 0 | 0 | 99 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
|
||||
| u_in0 | my_bram0 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_in1 | my_bram0_12 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out0 | my_bram0_13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out1 | my_bram0_14 | 25 | 25 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_mlkem_axi_cdc | Axi_CDC_5 | 256 | 144 | 112 | 0 | 272 | 0 | 0 | 0 |
|
||||
| arFifo | StreamFifoCC_3 | 51 | 23 | 28 | 0 | 55 | 0 | 0 | 0 |
|
||||
| (arFifo) | StreamFifoCC_3 | 42 | 14 | 28 | 0 | 43 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_10 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| awFifo | StreamFifoCC | 40 | 16 | 24 | 0 | 49 | 0 | 0 | 0 |
|
||||
| (awFifo) | StreamFifoCC | 31 | 7 | 24 | 0 | 35 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| bFifo | StreamFifoCC_2 | 18 | 14 | 4 | 0 | 27 | 0 | 0 | 0 |
|
||||
| (bFifo) | StreamFifoCC_2 | 11 | 7 | 4 | 0 | 13 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_4 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_6 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| rFifo | StreamFifoCC_4 | 56 | 28 | 28 | 0 | 72 | 0 | 0 | 0 |
|
||||
| (rFifo) | StreamFifoCC_4 | 49 | 21 | 28 | 0 | 56 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_1 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| wFifo | StreamFifoCC_1 | 91 | 63 | 28 | 0 | 69 | 0 | 0 | 0 |
|
||||
| (wFifo) | StreamFifoCC_1 | 86 | 58 | 28 | 0 | 53 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_8 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_mlkem_axi_slave | mlkem_axi_slave | 30043 | 29974 | 0 | 69 | 25426 | 2 | 6 | 24 |
|
||||
| (u_mlkem_axi_slave) | mlkem_axi_slave | 1278 | 1278 | 0 | 0 | 1064 | 0 | 0 | 0 |
|
||||
| u_mlkem | mlkem_top | 28768 | 28699 | 0 | 69 | 24362 | 2 | 6 | 24 |
|
||||
| (u_mlkem) | mlkem_top | 2326 | 2326 | 0 | 0 | 4911 | 0 | 0 | 0 |
|
||||
| u_bank_a | sd_bram__parameterized0 | 49 | 49 | 0 | 0 | 0 | 1 | 1 | 0 |
|
||||
| u_bank_se | sd_bram__parameterized1 | 61 | 61 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| u_bank_t | sd_bram__parameterized2 | 488 | 488 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_c_in_bram | sd_bram | 1291 | 1291 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_cbd | sample_cbd_sync_shared | 2512 | 2512 | 0 | 0 | 3199 | 0 | 0 | 0 |
|
||||
| u_comp | comp_decomp_sync | 322 | 321 | 0 | 1 | 269 | 0 | 0 | 3 |
|
||||
| u_ct_bram | sd_bram_6 | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_dkp_bram | sd_bram_7 | 73 | 73 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_ek_bram | sd_bram_8 | 388 | 388 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_keccak | keccak_core | 5622 | 5622 | 0 | 0 | 1606 | 0 | 0 | 0 |
|
||||
| u_ntt | ntt_core | 8192 | 8149 | 0 | 43 | 3743 | 0 | 0 | 6 |
|
||||
| (u_ntt) | ntt_core | 6140 | 6124 | 0 | 16 | 3364 | 0 | 0 | 0 |
|
||||
| u_bf | butterfly_unit_pipe | 1922 | 1896 | 0 | 26 | 224 | 0 | 0 | 3 |
|
||||
| (u_bf) | butterfly_unit_pipe | 69 | 44 | 0 | 25 | 75 | 0 | 0 | 0 |
|
||||
| u_barrett | barrett_mul_pipe_9 | 1854 | 1853 | 0 | 1 | 149 | 0 | 0 | 3 |
|
||||
| u_scl | barrett_mul_pipe | 131 | 130 | 0 | 1 | 155 | 0 | 0 | 3 |
|
||||
| u_pmul | poly_mul_sync | 2830 | 2805 | 0 | 25 | 6577 | 0 | 0 | 15 |
|
||||
| (u_pmul) | poly_mul_sync | 2474 | 2474 | 0 | 0 | 6299 | 0 | 0 | 0 |
|
||||
| u_bc | basecase_mul_pipe | 421 | 396 | 0 | 25 | 278 | 0 | 0 | 15 |
|
||||
| u_sha3 | sha3_top_shared | 3175 | 3175 | 0 | 0 | 2388 | 0 | 0 | 0 |
|
||||
| u_snt | sample_ntt_sync_shared | 1439 | 1439 | 0 | 0 | 1669 | 0 | 0 | 0 |
|
||||
| u_matmul_axi_slave | matmul_axi_slave | 6600 | 6418 | 176 | 6 | 2831 | 0 | 0 | 16 |
|
||||
| (u_matmul_axi_slave) | matmul_axi_slave | 5796 | 5614 | 176 | 6 | 2303 | 0 | 0 | 0 |
|
||||
| mult_inst[0].u_mult | pipelined_mult_32x32 | 203 | 203 | 0 | 0 | 132 | 0 | 0 | 4 |
|
||||
| mult_inst[1].u_mult | pipelined_mult_32x32_2 | 202 | 202 | 0 | 0 | 132 | 0 | 0 | 4 |
|
||||
| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 202 | 202 | 0 | 0 | 132 | 0 | 0 | 4 |
|
||||
| mult_inst[3].u_mult | pipelined_mult_32x32_4 | 200 | 200 | 0 | 0 | 132 | 0 | 0 | 4 |
|
||||
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1673 | 1673 | 0 | 0 | 1476 | 0 | 1 | 0 |
|
||||
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 687 | 687 | 0 | 0 | 1180 | 0 | 0 | 0 |
|
||||
| u_core_engine | snix_axi_mm2mm | 988 | 988 | 0 | 0 | 296 | 0 | 1 | 0 |
|
||||
| (u_core_engine) | snix_axi_mm2mm | 763 | 763 | 0 | 0 | 243 | 0 | 0 | 0 |
|
||||
| axis_fifo_u0 | snix_axis_fifo | 225 | 225 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
| u_fifo | snix_sync_fifo | 225 | 225 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
|
||||
|
||||
|
||||
Reference in New Issue
Block a user