add vivado reports
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fpga/vivado_reports_nodsp/power.rpt
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180
fpga/vivado_reports_nodsp/power.rpt
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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------------------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Wed Jul 8 03:34:25 2026
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| Host : fedora running 64-bit unknown
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| Command : report_power -file /home/fallensigh/vivado_reports_nodsp/power.rpt
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| Design : soc_top
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| Device : xc7a200tfbg676-1
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| Design State : routed
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| Grade : commercial
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| Process : typical
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| Characterization : Production
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------------------------------------------------------------------------------------------------
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Power Report
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Table of Contents
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-----------------
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1. Summary
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1.1 On-Chip Components
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1.2 Power Supply Summary
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1.3 Confidence Level
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2. Settings
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2.1 Environment
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2.2 Clock Constraints
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3. Detailed Reports
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3.1 By Hierarchy
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1. Summary
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----------
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+--------------------------+--------------+
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| Total On-Chip Power (W) | 0.549 |
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| Design Power Budget (W) | Unspecified* |
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| Power Budget Margin (W) | NA |
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| Dynamic (W) | 0.409 |
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| Device Static (W) | 0.141 |
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| Effective TJA (C/W) | 1.9 |
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| Max Ambient (C) | 84.0 |
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| Junction Temperature (C) | 26.0 |
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| Confidence Level | Low |
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| Setting File | --- |
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| Simulation Activity File | --- |
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| Design Nets Matched | NA |
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+--------------------------+--------------+
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* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
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1.1 On-Chip Components
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----------------------
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+--------------------------+-----------+----------+-----------+-----------------+
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| On-Chip | Power (W) | Used | Available | Utilization (%) |
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+--------------------------+-----------+----------+-----------+-----------------+
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| Clocks | 0.042 | 7 | --- | --- |
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| Slice Logic | 0.069 | 120086 | --- | --- |
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| LUT as Logic | 0.064 | 63754 | 133800 | 47.65 |
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| CARRY4 | 0.002 | 2859 | 33450 | 8.55 |
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| LUT as Distributed RAM | <0.001 | 740 | 46200 | 1.60 |
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| Register | <0.001 | 39931 | 267600 | 14.92 |
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| LUT as Shift Register | <0.001 | 1175 | 46200 | 2.54 |
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| F7/F8 Muxes | <0.001 | 6036 | 133800 | 4.51 |
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| Others | 0.000 | 318 | --- | --- |
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| Signals | 0.115 | 85084 | --- | --- |
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| Block RAM | 0.019 | 23.5 | 365 | 6.44 |
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| PLL | 0.132 | 1 | 10 | 10.00 |
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| DSPs | 0.009 | 16 | 740 | 2.16 |
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| I/O | 0.023 | 202 | 400 | 50.50 |
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| Static Power | 0.141 | | | |
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| Total | 0.549 | | | |
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+--------------------------+-----------+----------+-----------+-----------------+
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1.2 Power Supply Summary
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------------------------
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+-----------+-------------+-----------+-------------+------------+
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| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
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+-----------+-------------+-----------+-------------+------------+
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| Vccint | 1.000 | 0.294 | 0.262 | 0.032 |
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| Vccaux | 1.800 | 0.099 | 0.069 | 0.031 |
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| Vcco33 | 3.300 | 0.011 | 0.006 | 0.005 |
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| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
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| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
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| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
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| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
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| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
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| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
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| Vccbram | 1.000 | 0.003 | 0.001 | 0.001 |
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| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
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| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
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| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
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+-----------+-------------+-----------+-------------+------------+
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1.3 Confidence Level
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--------------------
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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| User Input Data | Confidence | Details | Action |
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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| Design implementation state | High | Design is routed | |
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| Clock nodes activity | High | User specified more than 95% of clocks | |
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| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
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| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
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| Device models | High | Device models are Production | |
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| | | | |
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| Overall confidence level | Low | | |
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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2. Settings
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-----------
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2.1 Environment
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---------------
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+-----------------------+--------------------------+
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| Ambient Temp (C) | 25.0 |
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| ThetaJA (C/W) | 1.9 |
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| Airflow (LFM) | 250 |
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| Heat Sink | medium (Medium Profile) |
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| ThetaSA (C/W) | 3.4 |
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| Board Selection | medium (10"x10") |
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| # of Board Layers | 12to15 (12 to 15 Layers) |
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| Board Temperature (C) | 25.0 |
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+-----------------------+--------------------------+
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2.2 Clock Constraints
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---------------------
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+-------------------+------------------------------------------+-----------------+
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| Clock | Domain | Constraint (ns) |
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+-------------------+------------------------------------------+-----------------+
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| clk | clk | 20.0 |
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| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
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| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
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| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 40.0 |
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| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
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+-------------------+------------------------------------------+-----------------+
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3. Detailed Reports
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-------------------
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3.1 By Hierarchy
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----------------
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+----------------------------+-----------+
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| Name | Power (W) |
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+----------------------------+-----------+
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| soc_top | 0.409 |
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| pll_clk.u_clk_pll | 0.133 |
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| inst | 0.133 |
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| u_Axi_CDC | 0.002 |
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| u_axi_uart_controller | 0.001 |
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| uart0 | 0.001 |
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| regs | 0.001 |
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| u_cdma_matmul_bridge | 0.001 |
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| u_cpu | 0.018 |
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| addr_trans | 0.002 |
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| tlb_entry | 0.002 |
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| btb | 0.002 |
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| dcache | 0.004 |
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| icache | 0.005 |
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| u_csr | 0.002 |
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| u_fft_mlkem_axi_slave | 0.148 |
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| u_fft_controller | 0.032 |
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| u_FFT | 0.029 |
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| u_mlkem_axi_cdc | 0.002 |
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| u_mlkem_axi_slave | 0.115 |
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| u_mlkem | 0.113 |
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| u_matmul_axi_slave | 0.065 |
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| u_snix_axil_cdma_mux_8ch | 0.009 |
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| u_core_engine | 0.004 |
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| axis_fifo_u0 | 0.003 |
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+----------------------------+-----------+
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