add vivado reports

2026-07-08 03:48:37 +08:00
parent b003fc057f
commit f676fc6e60
58 changed files with 257494 additions and 426061 deletions
--- a/fpga/vivado_reports_nodsp/clocks.rpt
+++ b/fpga/vivado_reports_nodsp/clocks.rpt
@@ -0,0 +1,76 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+| Date         : Wed Jul  8 03:34:13 2026
+| Host         : fedora running 64-bit unknown
+| Command      : report_clocks -file /home/fallensigh/vivado_reports_nodsp/clocks.rpt
+| Design       : soc_top
+| Device       : 7a200t-fbg676
+| Speed File   : -1  PRODUCTION 1.23 2018-06-13
+--------------------------------------------------------------------------------------
+
+Clock Report
+
+
+Attributes
+  P: Propagated
+  G: Generated
+  A: Auto-derived
+  R: Renamed
+  V: Virtual
+  I: Inverted
+  S: Pin phase-shifted with Latency mode
+
+Clock              Period(ns)  Waveform(ns)    Attributes  Sources
+clk                20.000      {0.000 10.000}  P           {clk}
+clkfbout_clk_pll   20.000      {0.000 10.000}  P,G,A       {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
+cpu_clk            30.323      {0.000 15.161}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
+mlkem_clk_clk_pll  40.000      {0.000 20.000}  P,G,A       {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
+sys_clk            20.000      {0.000 10.000}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
+
+
+====================================================
+Generated Clocks
+====================================================
+
+Generated Clock     : clkfbout_clk_pll
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Multiply By         : 1
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
+
+Generated Clock     : cpu_clk
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Edges               : {1 2 3}
+Edge Shifts(ns)     : {0.000 5.161 10.323}
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
+
+Generated Clock     : mlkem_clk_clk_pll
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Edges               : {1 2 3}
+Edge Shifts(ns)     : {0.000 10.000 20.000}
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
+
+Generated Clock     : sys_clk
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Multiply By         : 1
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
+
+
+
+====================================================
+User Uncertainty
+====================================================
+
+
+
+====================================================
+User Jitter
+====================================================
+
+Clock  Jitter(ns)
+clk    0.200
+