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add vivado reports

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FallenSigh
2026-07-08 03:48:37 +08:00
parent b003fc057f
commit f676fc6e60
58 changed files with 257494 additions and 426061 deletions
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fpga/vivado_reports_nodsp/clock_interaction.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 03:34:13 2026
| Host : fedora running 64-bit unknown
| Command : report_clock_interaction -file /home/fallensigh/vivado_reports_nodsp/clock_interaction.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
------------------------------------------------------------------------------------------------------------
Clock Interaction Report
Clock Interaction Table
-----------------------
WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock
From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints
----------------- ----------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- -------------------
cpu_clk cpu_clk rise - rise 2.72 0.00 0 17264 30.32 Clean Timed
cpu_clk sys_clk 0 162 Ignored Asynchronous Groups
mlkem_clk_clk_pll mlkem_clk_clk_pll rise - rise 10.81 0.00 0 74168 40.00 Clean Timed
mlkem_clk_clk_pll sys_clk rise - rise 11.25 0.00 0 61 20.00 Clean Timed
sys_clk cpu_clk 0 59 Ignored Asynchronous Groups
sys_clk mlkem_clk_clk_pll rise - rise 9.16 0.00 0 112 20.00 Clean Timed
sys_clk sys_clk rise - rise 0.17 0.00 0 23704 20.00 Clean Timed