Add CDMA matmul sequencer
This commit is contained in:
256
sdk/axi_ram.mif
256
sdk/axi_ram.mif
@@ -52,7 +52,7 @@
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00000011100000000110000000001101
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00000100000000000000000110101100
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00011100000000000000000000101100
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00000010101110101111000110001100
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00000010101100111111000110001100
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00011100000000000001000000001101
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00000010101111001001000110101101
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00011100000000000001000000001110
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@@ -94,7 +94,7 @@
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00000000000101010000000000001110
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00101001000000000001000110101110
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00011100000000000000000000001100
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00000010100100110001000110001100
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00000010100011000001000110001100
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00000100000000000011000000101100
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00000011100000000000010000001101
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00000100000000010001000000101101
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@@ -142,17 +142,13 @@
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00000000000000000000000000000000
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00000000000000000000000000000000
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00000000000000000000000000000000
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00000010101111110100000001100011
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00000010100000000000100000001101
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00000010100000000000010000001110
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00000010101111111000000001100011
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00010101011111100000000000010000
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00101001100000000110000001101110
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00101001100000000111000001101101
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00101001100000001011000001100001
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00101001100000001010000001110111
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00101001100000000111000001100001
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00101001100000000110000001110111
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00000010100000010011010000001100
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00011100000000000001000000001111
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00000010101101100111000111101111
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00000010101101101011000111101111
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00000011100000000001011000001101
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00101001100000000011000001101100
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00101010000000000011000001101110
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@@ -164,134 +160,36 @@
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00101001000000000000001000001110
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00101000000000000000000111101100
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01011111111111111101110110000000
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01010100000001111110100000000000
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00010101011111101010000000001100
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00000011100000000001000110001110
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00000010100000000001100000001111
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00101001100000000000000111001111
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00000011100000000100000110001101
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00101001100000000000000110100000
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01010100000001100011100000000000
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00010101011111100110000000001100
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00010100001110001000000000010010
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00101001100000000000000110010010
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00101001100000000001000110000000
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00000011100010000000000110001100
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00000010100000000000100000001110
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00101001100000000001000110001110
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00010100001110001000000000001101
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00101001100000000010000110001101
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00000011100101000000000110110011
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00000010100000000010100000010010
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00101001100000000011000110010011
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00101001100000000100000110010010
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00010100001111101010000000010001
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00000010100000100000000000010000
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00101001100000000010000110010000
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00000010100000000000010000001111
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00101001100000000110000110001111
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00000011101111110100010000001110
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00101001100000000111000110000000
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00101001100000000101000110010001
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00101001100000000110000110010000
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00000010100000110000000000001111
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00000010100000000000010000001110
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00101001100000000111000110001111
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00000000000101010000000010010111
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00010101011111100110000000010001
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00101001100000000100000110001110
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00101000100000000101001000101100
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00000011010000000000100110001100
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01011011111111111111100110000000
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00000010100000000000100000001100
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00101001100000000101001000101100
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00101000100000000110000001100101
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00010100001110001000000000010100
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00010101011111101010000000010010
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00101001100000000000001001000101
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00000011100000100000001010001110
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00101001100000000000001000101110
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00101001100000000001001000100000
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00000010100000100000000000000100
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00101001100000000010001000100100
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00000010100000000000010000001100
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00000011101111110100010000000111
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00010100001110001001001110001001
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00010101011111100110000000001101
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00010100000000000000000000100110
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00101001100000000110001000101100
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00101001100000000111001000101100
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00101001100000000100001000100111
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00000011100100000000000100101001
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00000011100001000000001010010100
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00000010100000000000010000010000
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00000010100000000000010000010011
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00000011100011100001110011000110
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00000010100000000000100000010010
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00000010100000000000010000000101
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00000011100000010000000110101110
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00000010100000110000000000001000
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00000011101111110100010000000100
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00000010100000100000000000000111
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00000011110000000000011000010001
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00101000100000000000000111101100
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00000011010000000000100110001100
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01011011111111111111100110000000
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00101001100000000000000111110010
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01011000000000000001101001100101
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00000000000101010000000110001101
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00101001100000000000000110001110
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00000011010000000000000000000000
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00101000100000000101000111001100
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00000011010000000000100110001100
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01011011111111111111100110000000
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00101001100000000101000111010010
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00101001100000000000000111000000
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00101001100000000001000111001001
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00101001100000000010000111001000
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00101001100000000110000111010010
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00101001100000000111000111010001
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00101001100000000100000111000100
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00101000100000000101000110101100
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00000011010000000000100110001100
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01011011111111111111100110000000
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00000010100000001000000001101100
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00000000010000001000101000010000
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00101001100000000101000110110010
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00000000000100000100000110010000
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00101000101111111110001000001100
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00101001100000000000000101001100
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01011000000000000011001001100110
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00101001100000000000000110110100
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00101001100000000001000110100000
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00101001100000000010000110100111
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00101001100000000110000110100101
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00101001100000000111000110110001
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00000010100000000000011001110011
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00000010100000100000001010010100
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00000010100000110000000100101001
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00000000000101010000001000110000
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00101001100000000100000110100100
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01010011111111110110111111111111
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00010101011111101010000000001110
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00000011100000000001000111001110
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00101000100000000000000111001100
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00101000100000000001000110101100
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00000011010000000000100110001100
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01011011111111111111100110000000
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00000010100000000000100000001100
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00010101011111100110000000001101
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00101001100000000000000111001100
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00000011100000010000000110101101
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00101000100000000101000110101100
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00000011010000000000100110001100
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01011011111111111111100110000000
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00000010100000000000100000001111
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00101001100000000101000110101111
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00010100001110001011000011001100
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00101001100000000000000110100000
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00000010100000110000000000010010
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00000011101001010000000110001100
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00101001100000000001000110101100
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00101001100000000010000110110010
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00000010100000000000010000010001
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00000011101111110100010000010000
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00010101011111100110000000001110
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00101001100000000110000110101111
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00101001100000000111000110110001
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00000011100000010000000111001110
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00101001100000000100000110110000
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00101000100000000101000111001100
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00000011010000000000100110001100
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01011011111111111111100110000000
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00000010100000000000100000001100
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00101001100000000101000111001100
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01010100000001011111010000000000
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01010100000001011100110000000000
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00011100000000000001000000001110
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00000010101011110010000111001110
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00000010101101011000000111001110
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00101000100000000000000111010010
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00010101011111101010000000001101
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00010100000000000001111010001100
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@@ -299,16 +197,46 @@
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00010101011111100000000000010000
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00000011100010010000000110001110
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00000000000100010101110010000100
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00000000001000010011101001010001
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00000000001000010011101001010011
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01011100000000000000100111000000
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00000000001010100000000000000111
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00101000100000000000000110110100
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00000000001000010100010010010010
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01011100000000000000101000100000
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00101000100000000000000110110001
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00000000001000010100110010010010
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01011100000000000000101001100000
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00000000001010100000000000000111
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00000010100000010011010000001100
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00011100000000000001000000001111
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00000010101011001111000111101111
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00000010101100110101000111101111
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00000011100000000001011000001101
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00101001100000000011000001101100
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00101010000000000011000001101110
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00000010100000000000010111101111
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00101010000000000000000110101100
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00000011010000001000000110001100
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01011011111111111111100110000000
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00101001000000000000001000001110
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00101000000000000000000111101100
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01011111111111111110000110000000
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00010101011111100000000000010000
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00000010100000000111000000001110
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00000010100000000010010000010100
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00000010101111111111000000010011
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00000011100000000001011000001101
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00000000000101111011101000101100
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00000011010000000011110110001100
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00000010100000010101110110001111
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01101000000000000000101010001100
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00000010100000001100000110001111
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00101010000000000000000110101100
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00000011010000001000000110001100
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01011011111111111111100110000000
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00101001000000000000001000001111
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00000010101111111111000111001110
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01011111111111111101100111010011
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00010101011111100000000000010000
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00000010100000000011010000001100
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00011100000000000001000000001111
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00000010101100011011000111101111
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00000011100000000001011000001101
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00101001100000000011000001101100
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00101010000000000011000001101110
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@@ -320,57 +248,28 @@
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00101001000000000000001000001110
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00101000000000000000000111101100
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01011111111111111101110110000000
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00010101011111100000000000010000
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00000010100000000111000000001110
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00000010100000000010010000010011
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00000010101111111111000000010001
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00000011100000000001011000001101
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00000000000101111011101010001100
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00000011010000000011110110001100
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00000010100000010101110110001111
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01101000000000000000101001101100
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00000010100000001100000110001111
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00101010000000000000000110101100
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00000011010000001000000110001100
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01011011111111111111100110000000
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00101001000000000000001000001111
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00000010101111111111000111001110
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01011111111111111101100111010001
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01010100000000101001100000000000
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00010101011111100000000000010000
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00000010100000000011010000001100
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00011100000000000001000000001111
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00000010101010110100000111101111
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00000010101100010000000111101111
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00000011100000000001011000001101
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00101001100000000011000001101100
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00101010000000000011000001101110
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00000010100000000000010111101111
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00000011010000000000000000000000
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00101010000000000000000110101100
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00000011010000001000000110001100
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01011011111111111111100110000000
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00101001000000000000001000001110
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00101000000000000000000111101100
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01011111111111111110000110000000
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01010100000000101100000000000000
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00010101011111100000000000010000
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00000010100000000011010000001100
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00011100000000000001000000001111
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00000010101010101010000111101111
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00000011100000000001011000001101
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00101001100000000011000001101100
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00101010000000000011000001101110
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00000010100000000000010111101111
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00101010000000000000000110101100
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00000011010000001000000110001100
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01011011111111111111100110000000
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00101001000000000000001000001110
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00101000000000000000000111101100
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01011111111111111110000110000000
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01011111111111111101110110000000
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00000000000101010000001001000100
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01010100000000101000000000000000
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01010100000000100101010000000000
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00010101011111100000000000010000
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00000010100000000011010000001100
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00011100000000000001000000001111
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00000010101010011111000111101111
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00000010101100000100000111101111
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00000011100000000001011000001101
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00101001100000000011000001101100
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00101010000000000011000001101110
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@@ -381,23 +280,12 @@
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00101001000000000000001000001110
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00101000000000000000000111101100
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01011111111111111110000110000000
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00101000100000001011000001100001
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00101000100000001010000001110111
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00101000100000000111000001100001
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00101000100000000110000001110111
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00000000000101010000000000000100
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00000010100000001100000001100011
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00000010100000001000000001100011
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01001100000000000000000000100000
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00000000000000000000000000000000
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00000000000000000000000000000000
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00000000000000000000000000000000
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00000000000000000000000000000000
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00000000000000000000000000000000
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00000000000000000000000000000000
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00000000000000000000000000000000
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00000000000000000000000000000000
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00000000000000000000000000000000
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00000000000000000000000000000000
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00000000000000000000000000000000
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00000000000000000000000000000000
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00000011010000000000000000000000
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00000010101111100001000001100011
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00101001100000011110000001100001
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00101001100000011101000001100010
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@@ -18,6 +18,19 @@ typedef struct {
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#define CDMA_MUX_BASE 0xbf300000
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#define DMA_CH(i) ((volatile dma_ch_regs_t*)(CDMA_MUX_BASE + (i) * 0x40))
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typedef struct {
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volatile u32 CTRL; // 0x200: bit0 start
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volatile u32 STATUS; // 0x204: bit0 busy, bit1 done (W1C)
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volatile u32 SRC_BASE; // 0x208
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volatile u32 DST_BASE; // 0x20C
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volatile u32 GROUPS; // 0x210
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volatile u32 MAT_BASE; // 0x214
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volatile u32 SRC_STRIDE; // 0x218
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volatile u32 DST_STRIDE; // 0x21C
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} dma_seq_regs_t;
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#define DMA_SEQ ((volatile dma_seq_regs_t*)(CDMA_MUX_BASE + 0x200))
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// CTRL 寄存器位定义
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#define CTRL_START_BIT (1 << 0)
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#define CTRL_BURST_SIZE(x) (((x) & 0x7) << 3) // Bits [5:3]: AXI AxSIZE (0=1B, 1=2B, 2=4B, 3=8B)
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@@ -33,5 +46,9 @@ typedef struct {
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#define STATUS_BUSY_BIT (1 << 0)
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#define STATUS_DONE_BIT (1 << 1)
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#define SEQ_START_BIT (1 << 0)
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#define SEQ_BUSY_BIT (1 << 0)
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#define SEQ_DONE_BIT (1 << 1)
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void dma_start_transfer(int ch_id, u32 src, u32 dst, u32 bytes, u32 tag);
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void dma_wait_polling(int ch_id);
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@@ -82,6 +82,7 @@ unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
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#define MATMUL_CTRL (MATMUL_BASE_UNCACHED + 0x000)
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#define MATMUL_STATUS (MATMUL_BASE_UNCACHED + 0x004)
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#define MATMUL_BASE_PHYS_FOR_DMA MATMUL_BASE_PHYS
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#define CTRL_START_B0 0x1
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#define CTRL_START_B1 0x2
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@@ -100,132 +101,26 @@ int main(void)
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if (MATMUL_GROUP_NUM <= 0) return 0;
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/* ── Hot-path local volatile pointers (one-time addr calc) ──────── */
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volatile unsigned int *mat_status = (volatile unsigned int *)MATMUL_STATUS;
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volatile unsigned int *mat_ctrl = (volatile unsigned int *)MATMUL_CTRL;
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volatile unsigned int *mat_crc = (volatile unsigned int *)MATMUL_CRC;
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volatile dma_ch_regs_t *ch0 = DMA_CH(0);
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volatile dma_ch_regs_t *ch1 = DMA_CH(1);
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volatile dma_seq_regs_t *seq = DMA_SEQ;
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unsigned int crc;
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unsigned int cycle_start, cycle_end, cycles, time_us;
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int g, bank;
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unsigned int ctrl_start[2] = {CTRL_START_B0, CTRL_START_B1};
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/* ── Start marker (must be first output) ──────────────────── */
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uart_puts("MATMUL_START\r\n");
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cycle_start = get_clock_count();
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// Reset IP state
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*mat_status = STATUS_DONE | STATUS_ERROR;
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*mat_crc = 0;
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/* ═══════════════════════════════════════════════════════════════
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* PROLOGUE: Load group 0 → Bank 0, start IP, pre-fire group 1
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* ═══════════════════════════════════════════════════════════════ */
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// DMA Ch0: Load group 0 A+B (128 bytes) → IP Bank 0
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ch0->SRC_ADDR = EXTRAM_PHYS_AB(0);
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ch0->DST_ADDR = 0;
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ch0->LENGTH = 128;
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ch0->MODE = DMA_MODE_MEM2EP;
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ch0->EP_CFG = DMA_EP_CFG(MATMUL_EP_ID, 0, 0);
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ch0->CTRL = DMA_CTRL_VAL;
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while (!(ch0->STATUS & STATUS_DONE_BIT)) {}
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ch0->STATUS = STATUS_DONE_BIT;
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// Start IP Bank 0 (group 0)
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*mat_ctrl = ctrl_start[0];
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// Pre-fire: DMA Ch0 load group 1 → Bank 1 (overlaps with IP compute)
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if (MATMUL_GROUP_NUM > 1) {
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ch0->SRC_ADDR = EXTRAM_PHYS_AB(1);
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ch0->DST_ADDR = 0;
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ch0->LENGTH = 128;
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ch0->MODE = DMA_MODE_MEM2EP;
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ch0->EP_CFG = DMA_EP_CFG(MATMUL_EP_ID, 1, 0);
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ch0->CTRL = DMA_CTRL_VAL;
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}
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/* ═══════════════════════════════════════════════════════════════
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* MAIN LOOP: Fully-pipelined — pre-fire DMA load at loop tail
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*
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* At iteration g:
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* IP is computing group (g-1) on prev_bank
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* Ch0 loaded group g to cur_bank (pre-fired in iteration g-1)
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*
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* Pipeline:
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* Ch0: | load g+1 | | load g+2 |
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* Ch1: | store g-1 | | store g |
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* IP : | compute g | | compute g+1 |
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* ═══════════════════════════════════════════════════════════════ */
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bank = 1; // cur_bank for iteration g=1; prev_bank = bank ^ 1
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for (g = 1; g < MATMUL_GROUP_NUM; g++) {
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int cur_bank = bank;
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int prev_bank = bank ^ 1;
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// 1. Wait for previous IP computation (group g-1 on prev_bank)
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while (!(*mat_status & STATUS_DONE)) {}
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*mat_status = STATUS_DONE;
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// 2. Ensure previous DMA Ch1 store is done (group g-2)
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if (g > 1) {
|
||||
while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
|
||||
ch1->STATUS = STATUS_DONE_BIT;
|
||||
}
|
||||
|
||||
// 3. Start DMA Ch1 store: group (g-1) result → ExtRAM
|
||||
ch1->SRC_ADDR = 0;
|
||||
ch1->DST_ADDR = EXTRAM_PHYS_C(g - 1);
|
||||
ch1->LENGTH = 192;
|
||||
ch1->MODE = DMA_MODE_EP2MEM;
|
||||
ch1->EP_CFG = DMA_EP_CFG(MATMUL_EP_ID, prev_bank, 0);
|
||||
ch1->CTRL = DMA_CTRL_VAL;
|
||||
|
||||
// 4. Wait for current DMA Ch0 load (group g → cur_bank, pre-fired in iteration g-1)
|
||||
while (!(ch0->STATUS & STATUS_DONE_BIT)) {}
|
||||
ch0->STATUS = STATUS_DONE_BIT;
|
||||
|
||||
// 5. Start IP computation for current group on cur_bank
|
||||
*mat_ctrl = ctrl_start[cur_bank];
|
||||
|
||||
// ★ 6. PRE-FIRE: DMA Ch0 load next group (g+1) → next_bank
|
||||
// This runs CONCURRENTLY with IP computation started in step 5!
|
||||
if (g < MATMUL_GROUP_NUM - 1) {
|
||||
int next_bank = bank ^ 1;
|
||||
ch0->SRC_ADDR = EXTRAM_PHYS_AB(g + 1);
|
||||
ch0->DST_ADDR = 0;
|
||||
ch0->LENGTH = 128;
|
||||
ch0->MODE = DMA_MODE_MEM2EP;
|
||||
ch0->EP_CFG = DMA_EP_CFG(MATMUL_EP_ID, next_bank, 0);
|
||||
ch0->CTRL = DMA_CTRL_VAL;
|
||||
}
|
||||
|
||||
// Toggle bank for next iteration
|
||||
bank ^= 1;
|
||||
}
|
||||
|
||||
/* ═══════════════════════════════════════════════════════════════
|
||||
* EPILOGUE: Flush the final group
|
||||
* ═══════════════════════════════════════════════════════════════ */
|
||||
|
||||
// Wait for last IP computation
|
||||
while (!(*mat_status & STATUS_DONE)) {}
|
||||
*mat_status = STATUS_DONE;
|
||||
|
||||
// Wait for previous DMA store and start/complete final store
|
||||
while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
|
||||
ch1->STATUS = STATUS_DONE_BIT;
|
||||
|
||||
ch1->SRC_ADDR = 0;
|
||||
ch1->DST_ADDR = EXTRAM_PHYS_C(MATMUL_GROUP_NUM - 1);
|
||||
ch1->LENGTH = 192;
|
||||
ch1->MODE = DMA_MODE_EP2MEM;
|
||||
ch1->EP_CFG = DMA_EP_CFG(MATMUL_EP_ID, (MATMUL_GROUP_NUM - 1) % 2, 0);
|
||||
ch1->CTRL = DMA_CTRL_VAL;
|
||||
while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
|
||||
ch1->STATUS = STATUS_DONE_BIT;
|
||||
seq->STATUS = SEQ_DONE_BIT;
|
||||
seq->SRC_BASE = EXTRAM_PHYS_AB(0);
|
||||
seq->DST_BASE = EXTRAM_PHYS_C(0);
|
||||
seq->GROUPS = MATMUL_GROUP_NUM;
|
||||
seq->MAT_BASE = MATMUL_BASE_PHYS_FOR_DMA;
|
||||
seq->SRC_STRIDE = 128;
|
||||
seq->DST_STRIDE = 192;
|
||||
seq->CTRL = SEQ_START_BIT;
|
||||
while (!(seq->STATUS & SEQ_DONE_BIT)) {}
|
||||
seq->STATUS = SEQ_DONE_BIT;
|
||||
cycle_end = get_clock_count();
|
||||
cycles = cycle_end - cycle_start;
|
||||
time_us = cycles / (CORE_CLOCKS_PER_SEC / 1000000UL);
|
||||
|
||||
Reference in New Issue
Block a user