Pipelined multiplier: 3-stage LUT-based replaces shift_add, FSM simplified to 2-state
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{"_example": "Fill with {\"file\": \"<path>\", \"reason\": \"<why>\"}. Put spec/research files only — no code paths. Run `python3 .trellis/scripts/get_context.py --mode packages` to list available specs. Delete this line once real entries are added."}
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{"_example": "Fill with {\"file\": \"<path>\", \"reason\": \"<why>\"}. Put spec/research files only — no code paths. Run `python3 .trellis/scripts/get_context.py --mode packages` to list available specs. Delete this line once real entries are added."}
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# Pipelined Multiplier for Matmul IP
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## Goal
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Replace 4× shift_add_mult (32 cycle/op) with 4× 3-stage pipelined multipliers (1 result/cycle after fill), reducing compute from 420 cycle/group to ~15 cycle/group.
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## Requirements
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1. **Multiplier**: 32×32→64, 3-stage pipeline, LUT-only (no DSP)
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2. **FSM**: simplified from 4-state (C_IDLE/C_CALC/C_WAIT_MULT/C_ACCUM) to 2-state (C_IDLE/C_RUN)
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3. **Pipeline matching**: 3-entry shift register for calc_idx/cur_bank delay line
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4. **Accumulation**: unchanged (4-way sum registered)
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5. **Interface**: same ports as shift_add_mult (clk, rstn, start, a, b, p, done) for drop-in replacement
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## Acceptance Criteria
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- [ ] Simulation: CRC32 matches (10 groups)
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- [ ] Lint clean
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- [ ] Compile passes
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- [ ] No DSP used
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- [ ] WNS ≥ 0 (timing passes for sys_clk=50MHz)
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- [ ] Expected time improvement: compute ~420 cycle → ~15 cycle
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## Technical Approach
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### Multiplier Design
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```verilog
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(* use_dsp = "no" *)
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module pipelined_mult (
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input clk, rstn, start,
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input [31:0] a, b,
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output [63:0] p,
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output done
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);
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// 3-stage: reg(a,b) → compute product → output
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endmodule
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```
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### FSM Reduction
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```
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Before: C_IDLE → C_CALC(1) → C_WAIT_MULT(32) → C_ACCUM(1)
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←──────── 12 rounds ────────→ = 420 cycles
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After: C_IDLE → C_RUN(12 + 3 pipe delay) → C_IDLE
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Issue 4 mults/cycle for 12 cycles
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Results arrive 3 cycles later → accumulate
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Total: 12 + 3 + 1 = 16 cycles
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```
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## Out of Scope
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- More than 4 multipliers
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- Changes to DMA, CRC32, interrupts
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- FFT integration
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{
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"id": "pipelined-multiplier-for-matmul-ip",
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"name": "pipelined-multiplier-for-matmul-ip",
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"title": "Pipelined multiplier for matmul IP",
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"description": "",
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"status": "in_progress",
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"dev_type": null,
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"scope": null,
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"package": null,
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"priority": "P2",
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"creator": "fallensigh",
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"assignee": "fallensigh",
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"createdAt": "2026-06-25",
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"completedAt": null,
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"branch": null,
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"base_branch": "no-fft",
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"worktree_path": null,
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"commit": null,
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"pr_url": null,
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"subtasks": [],
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"children": [],
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"parent": null,
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"relatedFiles": [],
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"notes": "",
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"meta": {}
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}
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@@ -1,51 +1,27 @@
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// ═══════════════════════════════════════════════════════
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// 基础时序乘法器模块 (无 DSP，移位累加，32个周期)
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// 3-stage pipelined multiplier (LUT-based, no DSP)
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// latency=3, throughput=1 result/cycle
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// ═══════════════════════════════════════════════════════
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module shift_add_mult (
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(* use_dsp = "no" *)
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module pipelined_mult_32x32 (
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input clk,
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input rstn,
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input start,
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input [31:0] a,
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input [31:0] b,
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output reg [63:0] p,
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output reg done
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output reg [63:0] p
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);
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reg [5:0] cnt;
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reg [63:0] a_reg;
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reg [31:0] b_reg;
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reg busy;
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reg [31:0] a_r, b_r;
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reg [63:0] prod;
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always @(posedge clk) begin
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if (!rstn) begin
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busy <= 1'b0;
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done <= 1'b0;
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p <= 64'b0;
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cnt <= 6'd0;
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a_reg<= 64'b0;
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b_reg<= 32'b0;
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a_r <= 32'b0; b_r <= 32'b0;
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prod <= 64'b0; p <= 64'b0;
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end else begin
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if (start && !busy) begin
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a_reg <= {32'b0, a};
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b_reg <= b;
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p <= 64'b0;
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cnt <= 6'd0;
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busy <= 1'b1;
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done <= 1'b0;
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end else if (busy) begin
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if (cnt == 6'd32) begin
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busy <= 1'b0;
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done <= 1'b1;
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end else begin
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if (b_reg[0]) begin
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p <= p + a_reg;
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end
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a_reg <= a_reg << 1;
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b_reg <= b_reg >> 1;
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cnt <= cnt + 6'd1;
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end
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end else begin
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done <= 1'b0;
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end
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a_r <= a; // Stage 1: register inputs
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b_r <= b;
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prod <= a_r * b_r; // Stage 2: LUT-based multiply
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p <= prod; // Stage 3: register output
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end
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end
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endmodule
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@@ -323,9 +299,7 @@ module matmul_axi_slave (
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// 前向声明引擎的状态
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localparam C_IDLE = 2'd0;
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localparam C_CALC = 2'd1;
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localparam C_WAIT_MULT = 2'd2;
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localparam C_ACCUM = 2'd3;
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localparam C_RUN = 2'd1;
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reg [1:0] state;
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reg cur_bank;
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reg calc_done_pulse;
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@@ -344,8 +318,8 @@ module matmul_axi_slave (
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done <= 1'b0;
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error <= 1'b0;
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end else begin
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if (req_0 && state == C_CALC && cur_bank == 1'b0) req_0 <= 1'b0;
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if (req_1 && state == C_CALC && cur_bank == 1'b1) req_1 <= 1'b0;
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if (req_0 && state == C_RUN && cur_bank == 1'b0) req_0 <= 1'b0;
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if (req_1 && state == C_RUN && cur_bank == 1'b1) req_1 <= 1'b0;
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if (calc_done_pulse) begin
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done <= 1'b1;
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@@ -524,102 +498,104 @@ module matmul_axi_slave (
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// ==========================================
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// 计算引擎 (Compute FSM)
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// ==========================================
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reg [3:0] calc_idx;
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wire [1:0] row = calc_idx[3:2];
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wire [1:0] col = calc_idx[1:0];
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reg mult_start;
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wire mult_done [0:3];
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wire [63:0] mult_p [0:3];
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reg [63:0] mult_p_r [0:3];
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reg [31:0] m_in_a [0:3];
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reg [31:0] m_in_b [0:3];
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genvar i;
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generate
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for (i = 0; i < 4; i = i + 1) begin : mult_inst
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shift_add_mult u_mult (
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pipelined_mult_32x32 u_mult (
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.clk (clk),
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.rstn (resetn),
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.start (mult_start),
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.a (m_in_a[i]),
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.b (m_in_b[i]),
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.p (mult_p[i]),
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.done (mult_done[i])
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.p (mult_p[i])
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);
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end
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endgenerate
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// Pipeline delay shift registers for accumulation (4 stages = 3 multiplier pipe + 1)
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reg [3:0] acc_idx_d1, acc_idx_d2, acc_idx_d3, acc_idx_d4;
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reg acc_bank_d1, acc_bank_d2, acc_bank_d3, acc_bank_d4;
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reg [4:0] pipe_cnt;
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always @(posedge clk) begin
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if (!resetn) begin
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state <= C_IDLE;
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busy <= 1'b0;
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cur_bank <= 1'b0;
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calc_idx <= 4'd0;
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mult_start <= 1'b0;
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calc_done_pulse <= 1'b0;
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pipe_cnt <= 5'd0;
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acc_idx_d1 <= 4'd0;
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acc_idx_d2 <= 4'd0;
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acc_idx_d3 <= 4'd0;
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acc_idx_d4 <= 4'd0;
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acc_bank_d1 <= 1'b0;
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acc_bank_d2 <= 1'b0;
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acc_bank_d3 <= 1'b0;
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acc_bank_d4 <= 1'b0;
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end else begin
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calc_done_pulse <= 1'b0;
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// Pipeline shift: issue_idx → d1 → d2 → d3 → d4 (4 cycles total)
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acc_idx_d4 <= acc_idx_d3;
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acc_idx_d3 <= acc_idx_d2;
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acc_idx_d2 <= acc_idx_d1;
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acc_idx_d1 <= pipe_cnt[3:0];
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acc_bank_d4 <= acc_bank_d3;
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acc_bank_d3 <= acc_bank_d2;
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acc_bank_d2 <= acc_bank_d1;
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acc_bank_d1 <= cur_bank;
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case (state)
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C_IDLE: begin
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calc_idx <= 4'd0;
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pipe_cnt <= 5'd0;
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if (req_0) begin
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cur_bank <= 1'b0;
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busy <= 1'b1;
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state <= C_CALC;
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state <= C_RUN;
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end else if (req_1) begin
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cur_bank <= 1'b1;
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busy <= 1'b1;
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state <= C_CALC;
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state <= C_RUN;
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end else begin
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busy <= 1'b0;
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end
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end
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C_CALC: begin
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C_RUN: begin
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// Issue 4 new operands every cycle (pipe_cnt 0-11, 12 rounds)
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if (pipe_cnt < 5'd12) begin
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if (cur_bank == 1'b0) begin
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m_in_a[0] <= b0_a[{row, 2'd0}]; m_in_b[0] <= b0_b[{2'd0, col}];
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m_in_a[1] <= b0_a[{row, 2'd1}]; m_in_b[1] <= b0_b[{2'd1, col}];
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m_in_a[2] <= b0_a[{row, 2'd2}]; m_in_b[2] <= b0_b[{2'd2, col}];
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m_in_a[3] <= b0_a[{row, 2'd3}]; m_in_b[3] <= b0_b[{2'd3, col}];
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m_in_a[0] <= b0_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b0_b[{2'd0, pipe_cnt[1:0]}];
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m_in_a[1] <= b0_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b0_b[{2'd1, pipe_cnt[1:0]}];
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m_in_a[2] <= b0_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b0_b[{2'd2, pipe_cnt[1:0]}];
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m_in_a[3] <= b0_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b0_b[{2'd3, pipe_cnt[1:0]}];
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end else begin
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m_in_a[0] <= b1_a[{row, 2'd0}]; m_in_b[0] <= b1_b[{2'd0, col}];
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m_in_a[1] <= b1_a[{row, 2'd1}]; m_in_b[1] <= b1_b[{2'd1, col}];
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m_in_a[2] <= b1_a[{row, 2'd2}]; m_in_b[2] <= b1_b[{2'd2, col}];
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m_in_a[3] <= b1_a[{row, 2'd3}]; m_in_b[3] <= b1_b[{2'd3, col}];
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end
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mult_start <= 1'b1;
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state <= C_WAIT_MULT;
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end
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C_WAIT_MULT: begin
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mult_start <= 1'b0;
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if (mult_done[0] && mult_done[1] && mult_done[2] && mult_done[3]) begin
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mult_p_r[0] <= mult_p[0];
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mult_p_r[1] <= mult_p[1];
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mult_p_r[2] <= mult_p[2];
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mult_p_r[3] <= mult_p[3];
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state <= C_ACCUM;
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m_in_a[0] <= b1_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b1_b[{2'd0, pipe_cnt[1:0]}];
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m_in_a[1] <= b1_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b1_b[{2'd1, pipe_cnt[1:0]}];
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m_in_a[2] <= b1_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b1_b[{2'd2, pipe_cnt[1:0]}];
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m_in_a[3] <= b1_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b1_b[{2'd3, pipe_cnt[1:0]}];
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end
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end
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C_ACCUM: begin
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if (cur_bank == 1'b0)
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b0_c[calc_idx] <= ({2'b0, mult_p_r[0]} + {2'b0, mult_p_r[1]}) +
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({2'b0, mult_p_r[2]} + {2'b0, mult_p_r[3]});
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// Accumulate results from 4 cycles ago (pipe_cnt 4-15)
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if (pipe_cnt >= 5'd4 && pipe_cnt < 5'd16) begin
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if (acc_bank_d4 == 1'b0)
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b0_c[acc_idx_d4] <= ({2'b0, mult_p[0]} + {2'b0, mult_p[1]}) +
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({2'b0, mult_p[2]} + {2'b0, mult_p[3]});
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else
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b1_c[calc_idx] <= ({2'b0, mult_p_r[0]} + {2'b0, mult_p_r[1]}) +
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({2'b0, mult_p_r[2]} + {2'b0, mult_p_r[3]});
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b1_c[acc_idx_d4] <= ({2'b0, mult_p[0]} + {2'b0, mult_p[1]}) +
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({2'b0, mult_p[2]} + {2'b0, mult_p[3]});
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end
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if (calc_idx == 4'd15) begin
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if (pipe_cnt == 5'd16) begin
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calc_done_pulse <= 1'b1;
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busy <= 1'b0;
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state <= C_IDLE;
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end else begin
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calc_idx <= calc_idx + 4'd1;
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state <= C_CALC;
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pipe_cnt <= pipe_cnt + 5'd1;
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end
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end
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endcase
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