From d72cda97b927d3d4167462641d46f63435f4733b Mon Sep 17 00:00:00 2001
From: FallenSigh <fallensigh@gmail.com>
Date: Wed, 1 Jul 2026 20:34:33 +0800
Subject: [PATCH] Fix CDMA channel start timing

---
 .gitattributes                    | 24 ++++++++++++++++++++++++
 rtl/ip/cdma/snix_axil_cdma_mux.sv | 10 +++++++---
 2 files changed, 31 insertions(+), 3 deletions(-)
 create mode 100644 .gitattributes

diff --git a/.gitattributes b/.gitattributes
new file mode 100644
index 0000000..47351df
--- /dev/null
+++ b/.gitattributes
@@ -0,0 +1,24 @@
+* text=auto eol=lf
+
+# Binary artifacts
+*.bin -text
+*.elf -text
+*.o -text
+*.a -text
+*.so -text
+*.dll -text
+*.exe -text
+
+# Documents and images
+*.pdf -text
+*.png -text
+*.jpg -text
+*.jpeg -text
+*.gif -text
+*.bmp -text
+*.ico -text
+
+# FPGA packaged IP/checkpoints can be binary archives.
+*.xcix -text
+*.dcp -text
+*.bit -text
diff --git a/rtl/ip/cdma/snix_axil_cdma_mux.sv b/rtl/ip/cdma/snix_axil_cdma_mux.sv
index 12255f3..4a4757b 100644
--- a/rtl/ip/cdma/snix_axil_cdma_mux.sv
+++ b/rtl/ip/cdma/snix_axil_cdma_mux.sv
@@ -296,7 +296,7 @@ module snix_axil_cdma_mux #(
     // ==========================================
     // Round-Robin Arbiter & Engine Driver
     // ==========================================
-    typedef enum logic [1:0] {IDLE, RUN} state_t;
+    typedef enum logic [1:0] {IDLE, START, RUN} state_t;
     state_t state;
     
     logic [CH_BITS-1:0] cur_ch;
@@ -465,13 +465,17 @@ module snix_axil_cdma_mux #(
                         if (ch_req[check_ch] && !arb_set_done[check_ch]) begin
                             cur_ch       <= check_ch;
                             rr_ptr       <= (check_ch == (PORTS - 1)) ? '0 : (check_ch + 1);
-                            engine_start <= 1'b1;
-                            state        <= RUN;
+                            state        <= START;
                             break;
                         end
                     end
                 end
 
+                START: begin
+                    engine_start <= 1'b1;
+                    state        <= RUN;
+                end
+
                 RUN: begin
                     if (engine_done) begin
                         arb_set_done[cur_ch] <= 1'b1;