test: add board FFT validation and VCD capture
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@@ -50,11 +50,16 @@ Commands:
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prepare Create evidence directories and Vivado project if absent
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lint Run the project-aware Verilator lint check
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build Build asm, fft, fft_dma, mlkem_test and mlkem_hello
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soc Build all five; simulate all except board-only asm
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soc Build all five; simulate mlkem_test and mlkem_hello
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soc-fft Explicitly run the long fft and fft_dma simulations
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implement Run Vivado implementation and collect PPA/CDC/DRC reports
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refresh Parse collected evidence, regenerate figures and build the PDF
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quick Run lint and refresh only; does not run Vivado implementation
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Set SAVE_VCD=1 for SoC simulations to write evidence/soc/<example>.vcd.
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Set VCD_SCOPE to a Vivado hierarchy glob to limit waveform size.
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Set SIM_RUN_TIME only for bounded waveform diagnostics; regressions use 'all'.
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Board-only tests (matmul official 5000-group timing and reset behavior) are
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listed in REPORT_RERUN_CHECKLIST.md and are intentionally not automated here.
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EOF
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@@ -95,21 +100,31 @@ build() {
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run_soc_case() {
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local example="$1"
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local vcd_path="$EVIDENCE_DIR/soc/$example.vcd"
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require_vivado
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build_example "$example"
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(cd "$ROOT/fpga" && "$VIVADO_BIN" -mode batch \
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if [[ "${SAVE_VCD:-0}" != "0" ]]; then
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echo "VCD output: $vcd_path (scope: ${VCD_SCOPE:-top-level control signals})"
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fi
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(cd "$ROOT/fpga" && SOC_VCD_PATH="$vcd_path" "$VIVADO_BIN" -mode batch \
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-source "$SCRIPT_DIR/run_soc_sim.tcl") 2>&1 | tee "$EVIDENCE_DIR/soc/$example.log"
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}
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soc() {
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prepare
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build_example asm
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run_soc_case fft
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run_soc_case fft_dma
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build_example fft
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build_example fft_dma
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run_soc_case mlkem_test
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run_soc_case mlkem_hello
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}
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soc_fft() {
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prepare
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run_soc_case fft
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run_soc_case fft_dma
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}
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implement() {
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prepare
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require_vivado
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@@ -130,6 +145,7 @@ case "${1:-}" in
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lint) lint ;;
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build) build ;;
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soc) soc ;;
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soc-fft) soc_fft ;;
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implement) implement ;;
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refresh) refresh ;;
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quick) lint; refresh ;;
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