Revert pipeline: restore single-cycle compute

rtl/ip/matmul/matmul_axi_slave.v

@@ -71,8 +71,6 @@ reg        busy;
 reg        done;
 reg        error;
 reg [3:0]  calc_index;
-reg [65:0] partial;       // pipeline register for 2-stage multiplier
-reg        pipe_valid;     // partial has valid data
 
 wire       write_fire;
 wire       start_fire;
@@ -290,28 +288,17 @@ always @(posedge clk) begin
             done       <= 1'b0;
             error      <= 1'b0;
             calc_index <= 4'd0;
-            pipe_valid <= 1'b0;
         end else if (busy) begin
-            if (!pipe_valid) begin
+            c_data[calc_index] <= calc_c_element(calc_index);
-                // Stage 1: compute element, store in partial
-                partial    <= calc_c_element(calc_index);
-                pipe_valid <= 1'b1;
-            end else begin
-                // Stage 2: store partial into c_data, advance
-                c_data[calc_index] <= partial;
-                pipe_valid <= 1'b0;
             if (calc_index == 4'd15) begin
                 busy       <= 1'b0;
                 done       <= 1'b1;
                 calc_index <= 4'd0;
-        partial       <= 66'b0;
-        pipe_valid    <= 1'b0;
             end else begin
                 calc_index <= calc_index + 4'd1;
             end
         end
     end
 end
-end
 
 endmodule