Fix CDMA sequencer declaration order

rtl/ip/cdma/snix_axil_cdma_mux.sv

@@ -489,6 +489,62 @@ module snix_axil_cdma_mux #(
     logic                   seq_arready;
     logic                   seq_rready;
 
+    // Hardware matmul loop sequencer state. Keep these declarations before the
+    // DMA routing logic because Vivado does not allow forward enum references.
+    typedef enum logic [4:0] {
+        SQ_IDLE,
+        SQ_CLEAR_CRC,
+        SQ_LOAD0,
+        SQ_START0,
+        SQ_LOAD1,
+        SQ_WAIT_DONE,
+        SQ_STORE,
+        SQ_CLEAR_DONE,
+        SQ_START_NEXT,
+        SQ_LOAD_NEXT,
+        SQ_DONE
+    } seq_state_t;
+
+    typedef enum logic [3:0] {
+        OP_IDLE,
+        OP_READ_ADDR,
+        OP_READ_DATA,
+        OP_WRITE_ADDR,
+        OP_WRITE_DATA,
+        OP_WRITE_RESP,
+        OP_REG_READ_ADDR,
+        OP_REG_READ_DATA,
+        OP_COPY_START,
+        OP_COPY_WAIT
+    } op_state_t;
+
+    seq_state_t seq_state;
+    op_state_t  op_state;
+
+    logic        op_start_copy;
+    logic        op_start_write;
+    logic        op_start_read;
+    logic        op_done;
+    logic [31:0] op_src_addr;
+    logic [31:0] op_dst_addr;
+    logic [31:0] op_bytes;
+    logic [31:0] op_write_addr;
+    logic [31:0] op_write_data;
+    logic [31:0] op_read_addr;
+    logic [31:0] op_read_data;
+    logic [31:0] op_src_cur;
+    logic [31:0] op_dst_cur;
+    logic [31:0] op_bytes_left;
+    logic [31:0] op_data_buf;
+    logic        op_buf_valid;
+    logic        op_copy_store;
+
+    logic [31:0] seq_group_idx;
+    logic [31:0] seq_load_idx;
+    logic [31:0] seq_store_idx;
+    logic        seq_compute_bank;
+    logic [31:0] seq_status_data;
+
     wire use_ep_engine = (state == RUN) && (engine_mode != MODE_MEM2MEM);
     wire use_seq_engine = seq_busy && (op_state != OP_IDLE) &&
                           (op_state != OP_COPY_START) && (op_state != OP_COPY_WAIT);
@@ -646,60 +702,6 @@ module snix_axil_cdma_mux #(
     // ==========================================
     // Hardware matmul loop sequencer
     // ==========================================
-    typedef enum logic [4:0] {
-        SQ_IDLE,
-        SQ_CLEAR_CRC,
-        SQ_LOAD0,
-        SQ_START0,
-        SQ_LOAD1,
-        SQ_WAIT_DONE,
-        SQ_STORE,
-        SQ_CLEAR_DONE,
-        SQ_START_NEXT,
-        SQ_LOAD_NEXT,
-        SQ_DONE
-    } seq_state_t;
-
-    typedef enum logic [3:0] {
-        OP_IDLE,
-        OP_READ_ADDR,
-        OP_READ_DATA,
-        OP_WRITE_ADDR,
-        OP_WRITE_DATA,
-        OP_WRITE_RESP,
-        OP_REG_READ_ADDR,
-        OP_REG_READ_DATA,
-        OP_COPY_START,
-        OP_COPY_WAIT
-    } op_state_t;
-
-    seq_state_t seq_state;
-    op_state_t  op_state;
-
-    logic        op_start_copy;
-    logic        op_start_write;
-    logic        op_start_read;
-    logic        op_done;
-    logic [31:0] op_src_addr;
-    logic [31:0] op_dst_addr;
-    logic [31:0] op_bytes;
-    logic [31:0] op_write_addr;
-    logic [31:0] op_write_data;
-    logic [31:0] op_read_addr;
-    logic [31:0] op_read_data;
-    logic [31:0] op_src_cur;
-    logic [31:0] op_dst_cur;
-    logic [31:0] op_bytes_left;
-    logic [31:0] op_data_buf;
-    logic        op_buf_valid;
-    logic        op_copy_store;
-
-    logic [31:0] seq_group_idx;
-    logic [31:0] seq_load_idx;
-    logic [31:0] seq_store_idx;
-    logic        seq_compute_bank;
-    logic [31:0] seq_status_data;
-
     wire seq_has_more_load = (seq_load_idx < seq_groups);
     wire [31:0] seq_src_addr_for_load = seq_src_base + (seq_load_idx * seq_src_stride);
     wire [31:0] seq_dst_addr_for_load = seq_mat_base + (seq_load_idx[0] ? MAT_B1_AB_OFF : MAT_B0_AB_OFF);