feat: add ML-KEM accelerator with AXI slave wrapper

Wrap mlkem_top in an AXI4 burst slave (mlkem_axi_slave) mapped to the
freed FFT slot 6 at 0x1f400000 (virtual 0xbf400000). The core runs on
sys_clk/2 (25 MHz); the wrapper handles the clock-domain crossing:
start toggle->pulse, wait-stated byte-preload handshake, busy/done
sync, and direct readback taps (ek/dk/ct/ss). CPU drives it via a
register map (CTRL/STATUS/CONFIG, d/z/msg, preload + readback windows).

Wire into soc_top on the existing axiOut_6 nets (no crossbar change),
add mlkem_intr on intrpt[3]. Add sdk mlkem_test example running a
KeyGen->Encaps->Decaps self-consistency round trip.

rtl/ip/mlkem/storage/s_bram.v

@@ -0,0 +1,31 @@
+// s_bram.v - Single-port behavioral RAM (shared read/write port)
+//
+// One port: either read or write per cycle (+1 cycle read latency).
+// When both rd_en and wr_en are high, write takes priority.
+// Read data is registered (1-cycle latency after rd_en).
+// No valid/ready handshake — pure memory, handshake managed at higher level.
+
+module s_bram #(
+    parameter W = 48,
+    parameter D = 512,
+    parameter A = 9
+) (
+    input  wire          clk,
+    input  wire          rd_en,
+    input  wire [A-1:0]  rd_addr,
+    output reg  [W-1:0]  rd_data,
+    input  wire          wr_en,
+    input  wire [A-1:0]  wr_addr,
+    input  wire [W-1:0]  wr_data
+);
+
+    reg [W-1:0] mem [0:D-1];
+
+    always @(posedge clk) begin
+        if (wr_en)
+            mem[wr_addr] <= wr_data;
+        else if (rd_en)
+            rd_data <= mem[rd_addr];
+    end
+
+endmodule

rtl/ip/mlkem/storage/sd_bram.v

@@ -0,0 +1,32 @@
+// sd_bram.v - Simple dual-port behavioral RAM (1 read + 1 write port)
+//
+// Vivado auto-infers this as BRAM when W >= 12 and D >= 64.
+// Read:  rd_addr sampled at posedge → rd_addr_r → rd_data = mem[rd_addr_r]
+// Write: wr_data written to mem[wr_addr] at posedge when wr_en=1
+// No valid/ready handshake — pure combinational-read / registered-write memory.
+
+module sd_bram #(
+    parameter W = 48,
+    parameter D = 64,
+    parameter A = 6
+) (
+    input  wire          clk,
+    input  wire [A-1:0]  rd_addr,
+    output wire [W-1:0]  rd_data,
+    input  wire          wr_en,
+    input  wire [A-1:0]  wr_addr,
+    input  wire [W-1:0]  wr_data
+);
+
+    reg [W-1:0] mem [0:D-1];
+    reg [A-1:0] rd_addr_r;
+
+    always @(posedge clk) begin
+        rd_addr_r <= rd_addr;
+        if (wr_en)
+            mem[wr_addr] <= wr_data;
+    end
+
+    assign rd_data = mem[rd_addr_r];
+
+endmodule