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Compute matmul CRC before result store

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FallenSigh
2026-07-04 19:45:22 +08:00
parent bf6051c8c6
commit c37f493bcb
5 changed files with 64 additions and 35 deletions
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19
rtl/ip/cdma/cdma_matmul_bridge.sv
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@@ -4,7 +4,7 @@
// the matmul local endpoint/control interface.
//
// AXI-Lite register map, relative to this bridge window:
// 0x00 CTRL bit0 start
// 0x00 CTRL bit0 start, bit1 skip_result_writeback
// 0x04 STATUS bit0 busy, bit1 done (W1C)
// 0x08 SRC_BASE physical ExtRAM input base
// 0x0C DST_BASE physical ExtRAM result base
@@ -102,6 +102,7 @@ module cdma_matmul_bridge #(
logic [31:0] seq_load_idx;
logic [31:0] seq_store_idx;
logic seq_compute_bank;
logic seq_skip_writeback;
wire [7:0] wr_off = s_axil_awaddr[7:0];
wire [7:0] rd_off = s_axil_araddr[7:0];
@@ -221,6 +222,7 @@ module cdma_matmul_bridge #(
seq_load_idx <= 32'd0;
seq_store_idx <= 32'd0;
seq_compute_bank <= 1'b0;
seq_skip_writeback <= 1'b0;
cdma_req_valid <= 1'b0;
cdma_req_mode <= MODE_MEM2EP;
cdma_req_src <= '0;
@@ -251,6 +253,7 @@ module cdma_matmul_bridge #(
seq_load_idx <= 32'd0;
seq_store_idx <= 32'd0;
seq_compute_bank <= 1'b0;
seq_skip_writeback <= s_axil_wstrb[0] && s_axil_wdata[1];
mat_crc_clear <= 1'b1;
mat_done_clear <= 1'b1;
seq_state <= SQ_CLEAR;
@@ -296,7 +299,19 @@ module cdma_matmul_bridge #(
SQ_WAIT_DONE: begin
if (mat_done) begin
mat_done_clear <= 1'b1;
seq_state <= SQ_STORE_START;
if (seq_skip_writeback) begin
seq_store_idx <= seq_store_idx + 32'd1;
seq_compute_bank <= ~seq_compute_bank;
if ((seq_store_idx + 32'd1) >= seq_groups) begin
seq_state <= SQ_DONE;
end else if (seq_load_idx < seq_groups) begin
seq_state <= SQ_LOAD_START;
end else begin
seq_state <= SQ_WAIT_DONE;
end
end else begin
seq_state <= SQ_STORE_START;
end
end
end