Avoid DSP in matmul master path

This commit is contained in:
2026-07-01 23:30:11 +08:00
parent fd03aaaaa1
commit baf3f6f696
3 changed files with 76 additions and 287 deletions

View File

@@ -2,7 +2,7 @@
// 3-stage pipelined multiplier (LUT-based, no DSP)
// latency=3, throughput=1 result/cycle
// ═══════════════════════════════════════════════════════
(* use_dsp = "no" *)
(* use_dsp = "no", use_dsp48 = "no", syn_multstyle = "logic" *)
module pipelined_mult_32x32 (
input clk,
input rstn,
@@ -11,7 +11,23 @@ module pipelined_mult_32x32 (
output reg [63:0] p
);
reg [31:0] a_r, b_r;
(* use_dsp = "no", use_dsp48 = "no", syn_multstyle = "logic" *)
reg [63:0] prod;
function automatic [63:0] lut_mul32;
input [31:0] lhs;
input [31:0] rhs;
integer bit_idx;
reg [63:0] acc;
begin
acc = 64'b0;
for (bit_idx = 0; bit_idx < 32; bit_idx = bit_idx + 1) begin
if (rhs[bit_idx])
acc = acc + ({32'b0, lhs} << bit_idx);
end
lut_mul32 = acc;
end
endfunction
always @(posedge clk) begin
if (!rstn) begin
@@ -20,7 +36,7 @@ module pipelined_mult_32x32 (
end else begin
a_r <= a; // Stage 1: register inputs
b_r <= b;
prod <= a_r * b_r; // Stage 2: LUT-based multiply
prod <= lut_mul32(a_r, b_r); // Stage 2: LUT-based multiply
p <= prod; // Stage 3: register output
end
end
@@ -186,6 +202,8 @@ module matmul_axi_slave (
reg dma_done;
reg [31:0] load_group;
reg [31:0] store_group;
reg [31:0] dma_next_rd_addr;
reg [31:0] dma_next_wr_addr;
reg [31:0] completed_groups;
reg [1:0] bank_loaded;
reg [1:0] bank_store_pending;
@@ -880,6 +898,8 @@ module matmul_axi_slave (
dma_done <= 1'b0;
load_group <= 32'd0;
store_group <= 32'd0;
dma_next_rd_addr <= 32'd0;
dma_next_wr_addr <= 32'd0;
completed_groups <= 32'd0;
bank_loaded <= 2'b00;
bank_store_pending <= 2'b00;
@@ -933,6 +953,8 @@ module matmul_axi_slave (
dma_done <= 1'b0;
load_group <= 32'd0;
store_group <= 32'd0;
dma_next_rd_addr <= dma_src_base;
dma_next_wr_addr <= dma_dst_base;
completed_groups <= 32'd0;
bank_loaded <= 2'b00;
bank_store_pending <= 2'b00;
@@ -978,7 +1000,7 @@ module matmul_axi_slave (
!(state == C_RUN && cur_bank == dma_load_bank)) begin
dma_rd_bank <= dma_load_bank;
dma_rd_count <= 5'd0;
m_axi_araddr <= dma_src_base + (load_group * dma_src_stride);
m_axi_araddr <= dma_next_rd_addr;
m_axi_arlen <= 8'd31;
m_axi_arsize <= 3'd2;
m_axi_arburst <= 2'b01;
@@ -999,6 +1021,7 @@ module matmul_axi_slave (
m_axi_rready <= 1'b0;
bank_loaded[dma_rd_bank] <= 1'b1;
load_group <= load_group + 32'd1;
dma_next_rd_addr <= dma_next_rd_addr + dma_src_stride;
dma_load_bank <= ~dma_load_bank;
dma_rd_state <= DMA_RD_IDLE;
end else begin
@@ -1018,7 +1041,7 @@ module matmul_axi_slave (
dma_wr_count <= 6'd0;
bank_store_pending[dma_store_bank] <= 1'b0;
bank_storing[dma_store_bank] <= 1'b1;
m_axi_awaddr <= dma_dst_base + (store_group * dma_dst_stride);
m_axi_awaddr <= dma_next_wr_addr;
m_axi_awlen <= 8'd47;
m_axi_awsize <= 3'd2;
m_axi_awburst <= 2'b01;
@@ -1055,6 +1078,7 @@ module matmul_axi_slave (
bank_storing[dma_store_bank] <= 1'b0;
dma_store_bank <= ~dma_store_bank;
store_group <= store_group + 32'd1;
dma_next_wr_addr <= dma_next_wr_addr + dma_dst_stride;
completed_groups <= completed_groups + 32'd1;
if ((completed_groups + 32'd1) >= dma_groups) begin
dma_busy <= 1'b0;

View File

@@ -52,11 +52,11 @@
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@@ -64,9 +64,9 @@
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@@ -74,7 +74,7 @@
00000011100000000110010000001100
00000100000001100000000000101100
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@@ -94,7 +94,7 @@
00000000000101010000000000001110
00101001000000000001000110101110
00011100000000000000000000001100
00000010100011010001000110001100
00000010100010100001000110001100
00000100000000000011000000101100
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00000100000000010001000000101101
@@ -142,14 +142,11 @@
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
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00101010000000000011000001101110
@@ -160,56 +157,43 @@
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01011100000000000000101001100000
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00101010000000000011000001101110
@@ -222,25 +206,25 @@
01011111111111111110000110000000
00010101011111100000000000010000
00000010100000000111000000001110
00000010100000000010010000010100
00000010101111111111000000010011
00000010100000000010010000010011
00000010101111111111000000010010
00000011100000000001011000001101
00000011010000000000000000000000
00000000000101111011101000101100
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00000010100000010101110110001111
01101000000000000000101010001100
01101000000000000000101001101100
00000010100000001100000110001111
00101010000000000000000110101100
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01011011111111111111100110000000
00101001000000000000001000001111
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01011111111111111101100111010011
01011111111111111101100111010010
00010101011111100000000000010000
00000010100000000011010000001100
00011100000000000001000000001111
00000010101100010111000111101111
00000010101100100111000111101111
00000011100000000001011000001101
00101001100000000011000001101100
00101010000000000011000001101110
@@ -252,44 +236,12 @@
00101001000000000000001000001110
00101000000000000000000111101100
01011111111111111101110110000000
01010100000000101100100000000000
00010101011111100000000000010000
00000010100000000011010000001100
00011100000000000001000000001111
00000010101100001100000111101111
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00101001100000000011000001101100
00101010000000000011000001101110
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00101010000000000000000110101100
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01011011111111111111100110000000
00101001000000000000001000001110
00101000000000000000000111101100
01011111111111111101110110000000
00000000000101010000001001000100
01010100000000101000010000000000
00010101011111100000000000010000
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00101001100000000011000001101100
00101010000000000011000001101110
00000010100000000000010111101111
00101010000000000000000110101100
00000011010000001000000110001100
01011011111111111111100110000000
00101001000000000000001000001110
00101000000000000000000111101100
01011111111111111110000110000000
00101000100000000111000001100001
00101000100000000110000001110111
00101000100000000101000001111000
00000000000101010000000000000100
00000010100000001000000001100011
00000010100000000100000001100011
01001100000000000000000000100000
00000011010000000000000000000000
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00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
@@ -430,154 +382,6 @@
00000011010000000000000000000000
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01011000000000100001010010000000
00000010100000000010100000001100
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01011100000000000000100110000000
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01011100000000000000100110000000
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01011100000000000000100110000000
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@@ -908,18 +712,10 @@
00000000000000000000000000111101
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00000000000000000000000000000000
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00000000000000000000000000111101
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00000000000000000000000000000000
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00000000000000000000000000000000

View File

@@ -5,7 +5,6 @@
*/
#include <dma.h>
#include <confreg_time.h>
/* ─── UART 16550 direct access (bypasses slow printf/picolibc) ──────── */
#define UART_THR (*(volatile unsigned char *)0xbf000000)
@@ -29,24 +28,6 @@ static void uart_puthex(unsigned int val) {
}
}
static void uart_putdec(unsigned int val) {
char buf[10];
int i = 0;
if (val == 0) {
uart_tx('0');
return;
}
while (val != 0) {
buf[i++] = (char)('0' + (val % 10));
val /= 10;
}
while (i > 0) {
uart_tx((unsigned char)buf[--i]);
}
}
/* ─── Configurable group count (default 5000) ──────────────────────── */
#ifndef MATMUL_GROUP_NUM
#define MATMUL_GROUP_NUM 5000
@@ -54,9 +35,6 @@ static void uart_putdec(unsigned int val) {
/* ─── BSP globals ─────────────────────────────────────────────────── */
unsigned long UART_BASE = 0xbf000000;
unsigned long CONFREG_TIMER_BASE = 0xbf20f100;
unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L;
unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
/* ─── Memory layout ────────────────────────────────────────────────── */
#define EXTRAM_BASE_PHYS 0x1c400000
@@ -107,11 +85,9 @@ int main(void)
volatile unsigned int *mat_crc = (volatile unsigned int *)MATMUL_CRC;
unsigned int crc;
unsigned int cycle_start, cycle_end, cycles, time_us;
/* ── Start marker (must be first output) ──────────────────── */
uart_puts("MATMUL_START\r\n");
cycle_start = get_clock_count();
*(volatile unsigned int *)MATMUL_CRC = 0;
*mat_status = STATUS_DMA_DONE | STATUS_DONE | STATUS_ERROR;
@@ -123,19 +99,12 @@ int main(void)
*mat_ctrl = CTRL_DMA_START;
while (!(*mat_status & STATUS_DMA_DONE)) {}
*mat_status = STATUS_DMA_DONE;
cycle_end = get_clock_count();
cycles = cycle_end - cycle_start;
time_us = cycles / (CORE_CLOCKS_PER_SEC / 1000000UL);
/* ── Read hardware CRC32 ──────────────────────────────────── */
crc = *mat_crc;
uart_puts("MATMUL_CRC32=");
uart_puthex(crc);
uart_puts("\r\nMATMUL_CYCLES=");
uart_putdec(cycles);
uart_puts("\r\nMATMUL_TIME_US=");
uart_putdec(time_us);
uart_puts("\r\nMATMUL_DONE\r\n");
return 0;