Add direct CDMA matmul path
This commit is contained in:
@@ -9,21 +9,46 @@ typedef struct {
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volatile u32 TAG; // 0x0C: software tag (ignored by HW)
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volatile u32 CTRL; // 0x10: control (burst config + start)
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volatile u32 STATUS; // 0x14: status (busy, done)
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volatile u32 RESV[10]; // 0x18 ~ 0x3C: padding to 0x40 bytes
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volatile u32 MODE; // 0x18: 0=mem2mem, 1=mem2ep, 2=ep2mem
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volatile u32 EP_CFG; // 0x1C: [3:0]=bank, [15:8]=word offset, [19:16]=endpoint id
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volatile u32 RESV[8]; // 0x20 ~ 0x3C: padding to 0x40 bytes
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} dma_ch_regs_t;
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// DMA 控制器基地址
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#define CDMA_MUX_BASE 0xbf300000
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#define DMA_CH(i) ((volatile dma_ch_regs_t*)(CDMA_MUX_BASE + (i) * 0x40))
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typedef struct {
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volatile u32 CTRL; // 0x200: bit0 start
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volatile u32 STATUS; // 0x204: bit0 busy, bit1 done (W1C)
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volatile u32 SRC_BASE; // 0x208
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volatile u32 DST_BASE; // 0x20C
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volatile u32 GROUPS; // 0x210
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volatile u32 MAT_BASE; // 0x214: reserved for compatibility
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volatile u32 SRC_STRIDE; // 0x218
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volatile u32 DST_STRIDE; // 0x21C
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} dma_seq_regs_t;
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#define DMA_SEQ ((volatile dma_seq_regs_t*)(CDMA_MUX_BASE + 0x200))
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// CTRL 寄存器位定义
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#define CTRL_START_BIT (1 << 0)
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#define CTRL_BURST_SIZE(x) (((x) & 0x7) << 3) // Bits [5:3]: AXI AxSIZE (0=1B, 1=2B, 2=4B, 3=8B)
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#define CTRL_BURST_LEN(x) (((x) & 0xFF) << 6) // Bits [13:6]: AXI AxLEN (0=1 beat, 15=16 beats)
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#define DMA_MODE_MEM2MEM 0
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#define DMA_MODE_MEM2EP 1
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#define DMA_MODE_EP2MEM 2
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#define DMA_EP_CFG(id, bank, word_off) \
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((((id) & 0xF) << 16) | (((word_off) & 0xFF) << 8) | ((bank) & 0xF))
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// STATUS 寄存器位定义
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#define STATUS_BUSY_BIT (1 << 0)
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#define STATUS_DONE_BIT (1 << 1)
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#define SEQ_START_BIT (1 << 0)
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#define SEQ_BUSY_BIT (1 << 0)
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#define SEQ_DONE_BIT (1 << 1)
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void dma_start_transfer(int ch_id, u32 src, u32 dst, u32 bytes, u32 tag);
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void dma_wait_polling(int ch_id);
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void dma_wait_polling(int ch_id);
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@@ -1,213 +1,85 @@
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/**
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* user-sample - CIC-IEC 2026 Stage 3 Evaluation Program
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* user-sample - CICIEC 2026 Stage 3 evaluation program
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*
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* (ULTIMATE PERFORMANCE DMA + PING-PONG BUFFER ARCHITECTURE v2)
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*
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* Optimizations over v1:
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* 1. Pre-fire DMA Ch0 load at loop tail → fully overlaps with IP compute
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* 2. Inlined wait loops → zero function-call overhead in hot path
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* 3. Inlined DMA start → skips redundant STATUS_BUSY_BIT check
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* 4. XOR bank toggle → avoids g%2 recomputation per iteration
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* The CDMA/matmul direct sequencer reads 5000 A/B groups from ExtRAM, writes
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* the complete C result region, and accumulates the required IEEE CRC32 in
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* hardware while the C words are streamed out of matmul.
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*/
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#include <dma.h>
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/* ─── UART 16550 direct access (bypasses slow printf/picolibc) ──────── */
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#define UART_THR (*(volatile unsigned char *)0xbf000000)
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#define UART_LSR (*(volatile unsigned char *)0xbf000005)
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#define LSR_THRE 0x20
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static inline void uart_tx(unsigned char c) {
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while (!(UART_LSR & LSR_THRE)) {}
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static inline void uart_tx(unsigned char c)
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{
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while ((UART_LSR & LSR_THRE) == 0) {
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}
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UART_THR = c;
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}
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static void uart_puts(const char *s) {
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while (*s) uart_tx(*s++);
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}
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static void uart_puthex(unsigned int val) {
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int i;
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for (i = 28; i >= 0; i -= 4) {
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unsigned char nibble = (val >> i) & 0xF;
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uart_tx(nibble < 10 ? '0' + nibble : 'a' + nibble - 10);
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static void uart_puts(const char *s)
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{
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while (*s) {
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uart_tx((unsigned char)*s++);
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}
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}
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static void uart_puthex(unsigned int val)
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{
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int i;
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for (i = 28; i >= 0; i -= 4) {
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unsigned char nibble = (unsigned char)((val >> i) & 0xf);
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uart_tx((unsigned char)(nibble < 10 ? ('0' + nibble) : ('a' + nibble - 10)));
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}
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}
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/* ─── Configurable group count (default 5000) ──────────────────────── */
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#ifndef MATMUL_GROUP_NUM
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#define MATMUL_GROUP_NUM 5000
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#endif
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/* ─── BSP globals ─────────────────────────────────────────────────── */
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unsigned long UART_BASE = 0xbf000000;
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unsigned long CONFREG_TIMER_BASE = 0xbf20f100;
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unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L;
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unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
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unsigned long UART_BASE = 0xbf000000;
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/* ─── Memory layout ────────────────────────────────────────────────── */
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#define EXTRAM_BASE_PHYS 0x1c400000
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#define EXTRAM_BASE_UNCACHED (0xA0000000 | (EXTRAM_BASE_PHYS & 0x1FFFFFFF))
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#define EXTRAM_BASE_PHYS 0x1c400000u
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#define SRC_BASE_WORDS 0u
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#define DST_BASE_WORDS (SRC_BASE_WORDS + MATMUL_GROUP_NUM * 32u)
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#define SRC_BASE_WORDS 0
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#define DST_BASE_WORDS (SRC_BASE_WORDS + MATMUL_GROUP_NUM * 32)
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#define RESULT_WORDS (MATMUL_GROUP_NUM * 48)
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#define EXTRAM_PHYS_AB(g) (EXTRAM_BASE_PHYS + (SRC_BASE_WORDS * 4u) + (unsigned int)(g) * 128u)
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#define EXTRAM_PHYS_C(g) (EXTRAM_BASE_PHYS + (DST_BASE_WORDS * 4u) + (unsigned int)(g) * 192u)
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/* ExtRAM Physical Addresses for DMA */
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#define EXTRAM_PHYS_AB(g) (EXTRAM_BASE_PHYS + (SRC_BASE_WORDS * 4) + (g) * 128)
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#define EXTRAM_PHYS_C(g) (EXTRAM_BASE_PHYS + (DST_BASE_WORDS * 4) + (g) * 192)
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#define MATMUL_BASE_UNCACHED 0xbf500000u
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#define MATMUL_CRC (*(volatile unsigned int *)(MATMUL_BASE_UNCACHED + 0x010u))
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/* ─── MATMUL IP registers (Ping-Pong Memory Map) ──────────────────── */
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#define MATMUL_BASE_PHYS 0x1f500000
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#define MATMUL_BASE_UNCACHED 0xbf500000
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#define MATMUL_CTRL (MATMUL_BASE_UNCACHED + 0x000)
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#define MATMUL_STATUS (MATMUL_BASE_UNCACHED + 0x004)
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#define MATMUL_PHYS_B0_AB (MATMUL_BASE_PHYS + 0x100)
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#define MATMUL_PHYS_B0_C (MATMUL_BASE_PHYS + 0x180)
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#define MATMUL_PHYS_B1_AB (MATMUL_BASE_PHYS + 0x300)
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#define MATMUL_PHYS_B1_C (MATMUL_BASE_PHYS + 0x380)
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#define CTRL_START_B0 0x1
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#define CTRL_START_B1 0x2
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#define STATUS_DONE 0x2
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#define STATUS_ERROR 0x4
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#define MATMUL_CRC (MATMUL_BASE_UNCACHED + 0x010)
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/* ─── Pre-computed DMA burst control word ──────────────────────────── */
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#define DMA_CTRL_VAL (CTRL_BURST_SIZE(2) | CTRL_BURST_LEN(63) | CTRL_START_BIT)
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/* ═══════════════════════════════════════════════════════════════════ */
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int main(void)
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{
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if (MATMUL_GROUP_NUM <= 0) return 0;
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/* ── Hot-path local volatile pointers (one-time addr calc) ──────── */
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volatile unsigned int *mat_status = (volatile unsigned int *)MATMUL_STATUS;
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volatile unsigned int *mat_ctrl = (volatile unsigned int *)MATMUL_CTRL;
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volatile unsigned int *mat_crc = (volatile unsigned int *)MATMUL_CRC;
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volatile dma_ch_regs_t *ch0 = DMA_CH(0);
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volatile dma_ch_regs_t *ch1 = DMA_CH(1);
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unsigned int crc;
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int g, bank;
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// Ping-Pong Register Address Arrays (Physical for DMA)
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unsigned int phys_bank_AB[2] = {MATMUL_PHYS_B0_AB, MATMUL_PHYS_B1_AB};
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unsigned int phys_bank_C[2] = {MATMUL_PHYS_B0_C, MATMUL_PHYS_B1_C};
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unsigned int ctrl_start[2] = {CTRL_START_B0, CTRL_START_B1};
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/* ── Start marker (must be first output) ──────────────────── */
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uart_puts("MATMUL_START\r\n");
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// Reset IP state
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*mat_status = STATUS_DONE | STATUS_ERROR;
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*mat_crc = 0;
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/* ═══════════════════════════════════════════════════════════════
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* PROLOGUE: Load group 0 → Bank 0, start IP, pre-fire group 1
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* ═══════════════════════════════════════════════════════════════ */
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// DMA Ch0: Load group 0 A+B (128 bytes) → IP Bank 0
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ch0->SRC_ADDR = EXTRAM_PHYS_AB(0);
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ch0->DST_ADDR = phys_bank_AB[0];
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ch0->LENGTH = 128;
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ch0->CTRL = DMA_CTRL_VAL;
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while (!(ch0->STATUS & STATUS_DONE_BIT)) {}
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ch0->STATUS = STATUS_DONE_BIT;
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// Start IP Bank 0 (group 0)
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*mat_ctrl = ctrl_start[0];
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// Pre-fire: DMA Ch0 load group 1 → Bank 1 (overlaps with IP compute)
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if (MATMUL_GROUP_NUM > 1) {
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ch0->SRC_ADDR = EXTRAM_PHYS_AB(1);
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ch0->DST_ADDR = phys_bank_AB[1];
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ch0->LENGTH = 128;
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ch0->CTRL = DMA_CTRL_VAL;
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if (MATMUL_GROUP_NUM <= 0) {
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return 0;
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}
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/* ═══════════════════════════════════════════════════════════════
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* MAIN LOOP: Fully-pipelined — pre-fire DMA load at loop tail
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*
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* At iteration g:
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* IP is computing group (g-1) on prev_bank
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* Ch0 loaded group g to cur_bank (pre-fired in iteration g-1)
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*
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* Pipeline:
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* Ch0: | load g+1 | | load g+2 |
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* Ch1: | store g-1 | | store g |
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* IP : | compute g | | compute g+1 |
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* ═══════════════════════════════════════════════════════════════ */
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bank = 1; // cur_bank for iteration g=1; prev_bank = bank ^ 1
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uart_puts("MATMUL_START\n");
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for (g = 1; g < MATMUL_GROUP_NUM; g++) {
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int cur_bank = bank;
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int prev_bank = bank ^ 1;
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DMA_SEQ->STATUS = SEQ_DONE_BIT;
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DMA_SEQ->SRC_BASE = EXTRAM_PHYS_AB(0);
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DMA_SEQ->DST_BASE = EXTRAM_PHYS_C(0);
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DMA_SEQ->GROUPS = MATMUL_GROUP_NUM;
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DMA_SEQ->MAT_BASE = 0x1f500000u;
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DMA_SEQ->SRC_STRIDE = 128u;
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DMA_SEQ->DST_STRIDE = 192u;
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DMA_SEQ->CTRL = SEQ_START_BIT;
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// 1. Wait for previous IP computation (group g-1 on prev_bank)
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while (!(*mat_status & STATUS_DONE)) {}
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*mat_status = STATUS_DONE;
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// 2. Ensure previous DMA Ch1 store is done (group g-2)
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if (g > 1) {
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while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
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ch1->STATUS = STATUS_DONE_BIT;
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}
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// 3. Start DMA Ch1 store: group (g-1) result → ExtRAM
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ch1->SRC_ADDR = phys_bank_C[prev_bank];
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ch1->DST_ADDR = EXTRAM_PHYS_C(g - 1);
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ch1->LENGTH = 192;
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ch1->CTRL = DMA_CTRL_VAL;
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// 4. Wait for current DMA Ch0 load (group g → cur_bank, pre-fired in iteration g-1)
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while (!(ch0->STATUS & STATUS_DONE_BIT)) {}
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ch0->STATUS = STATUS_DONE_BIT;
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// 5. Start IP computation for current group on cur_bank
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*mat_ctrl = ctrl_start[cur_bank];
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// ★ 6. PRE-FIRE: DMA Ch0 load next group (g+1) → next_bank
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// This runs CONCURRENTLY with IP computation started in step 5!
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if (g < MATMUL_GROUP_NUM - 1) {
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int next_bank = bank ^ 1;
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ch0->SRC_ADDR = EXTRAM_PHYS_AB(g + 1);
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ch0->DST_ADDR = phys_bank_AB[next_bank];
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ch0->LENGTH = 128;
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ch0->CTRL = DMA_CTRL_VAL;
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}
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// Toggle bank for next iteration
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bank ^= 1;
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while ((DMA_SEQ->STATUS & SEQ_DONE_BIT) == 0u) {
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}
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DMA_SEQ->STATUS = SEQ_DONE_BIT;
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/* ═══════════════════════════════════════════════════════════════
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* EPILOGUE: Flush the final group
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* ═══════════════════════════════════════════════════════════════ */
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// Wait for last IP computation
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while (!(*mat_status & STATUS_DONE)) {}
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*mat_status = STATUS_DONE;
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// Wait for previous DMA store and start/complete final store
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while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
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ch1->STATUS = STATUS_DONE_BIT;
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ch1->SRC_ADDR = phys_bank_C[(MATMUL_GROUP_NUM - 1) % 2];
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ch1->DST_ADDR = EXTRAM_PHYS_C(MATMUL_GROUP_NUM - 1);
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ch1->LENGTH = 192;
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ch1->CTRL = DMA_CTRL_VAL;
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while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
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ch1->STATUS = STATUS_DONE_BIT;
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/* ── Read hardware CRC32 ──────────────────────────────────── */
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crc = *mat_crc;
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crc = MATMUL_CRC;
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uart_puts("MATMUL_CRC32=");
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uart_puthex(crc);
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uart_puts("\r\nMATMUL_DONE\r\n");
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uart_puts("\nMATMUL_DONE\n");
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return 0;
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}
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@@ -1,197 +1,88 @@
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/**
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* matmul_test - CIC-IEC 2026 Stage 3 Evaluation Program
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*
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* Reads 5000 groups of 4x4 unsigned matrix multiplications from ExtRAM,
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* computes C = A x B via the hardware matmul IP, writes results back,
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* computes CRC32 over the result region, and outputs the required identifiers.
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*
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* Data layout:
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* Input: ExtRAM word offset 0x00000000, 5000 * 32 = 160000 words
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* Result: ExtRAM word offset 0x0009C400, 5000 * 48 = 240000 words
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* CRC32 over result region byte stream (960000 bytes, little-endian)
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* Uses the CDMA-to-matmul direct endpoint sequencer. The CDMA still owns the
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* external-memory traffic, while matmul A/B/C transfers use local wires instead
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* of the AXI crossbar.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <dma.h>
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/* ─── BSP globals ─────────────────────────────────────────────────── */
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unsigned long UART_BASE = 0xbf000000;
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unsigned long CONFREG_TIMER_BASE = 0xbf20f100;
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unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L;
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unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
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/* UART 16550 direct access avoids the printf/newlib overhead on the hot path. */
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#define UART_THR (*(volatile unsigned char *)0xbf000000)
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#define UART_LSR (*(volatile unsigned char *)0xbf000005)
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#define LSR_THRE 0x20
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/* ─── Memory layout ────────────────────────────────────────────────── */
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#define EXTRAM_BASE_PHYS 0x1c400000
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#define EXTRAM_BASE (0xA0000000 | (EXTRAM_BASE_PHYS & 0x1FFFFFFF))
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#define SRC_BASE 0
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#define N_GROUPS 5000
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#define DST_BASE (SRC_BASE + N_GROUPS * 32) /* word offset 160000 */
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#define RESULT_WORDS (N_GROUPS * 48) /* 240000 words */
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#define RESULT_BYTES (RESULT_WORDS * 4) /* 960000 bytes */
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/* ─── MATMUL IP registers ─────────────────────────────────────────── */
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#define MATMUL_BASE 0xbf500000
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#define MATMUL_CTRL (MATMUL_BASE + 0x000)
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#define MATMUL_STATUS (MATMUL_BASE + 0x004)
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#define MATMUL_A_BASE (MATMUL_BASE + 0x020)
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#define MATMUL_B_BASE (MATMUL_BASE + 0x060)
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#define MATMUL_C_BASE (MATMUL_BASE + 0x0a0)
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#define CTRL_START 0x1
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#define STATUS_BUSY 0x1
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#define STATUS_DONE 0x2
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#define STATUS_ERROR 0x4
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/* ─── Convenience macros ──────────────────────────────────────────── */
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#define REG_WR(addr, val) (*(volatile uint32_t *)(addr) = (uint32_t)(val))
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#define REG_RD(addr) (*(volatile uint32_t *)(addr))
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/* ─── CRC32 table (IEEE 802.3, polynomial 0xEDB88320) ─────────────── */
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static const uint32_t crc32_table[256] = {
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0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
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0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
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0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
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0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
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0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
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0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
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0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
|
||||
0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
|
||||
0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
|
||||
0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
|
||||
0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
|
||||
0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
|
||||
0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
|
||||
0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
|
||||
0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
|
||||
0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
|
||||
0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
|
||||
0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
|
||||
0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
|
||||
0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
|
||||
0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
|
||||
0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
|
||||
0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
|
||||
0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
|
||||
0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
|
||||
0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
|
||||
0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
|
||||
0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
|
||||
0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
|
||||
0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
|
||||
0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
|
||||
0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
|
||||
0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
|
||||
0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
|
||||
0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
|
||||
0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
|
||||
0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
|
||||
0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
|
||||
0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
|
||||
0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
|
||||
0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
|
||||
0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
|
||||
0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
|
||||
0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
|
||||
0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
|
||||
0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
|
||||
0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB30A04,
|
||||
0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
|
||||
0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
|
||||
0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
|
||||
0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
|
||||
0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
|
||||
0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
|
||||
0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
|
||||
0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
|
||||
0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
|
||||
0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
|
||||
0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
|
||||
0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
|
||||
0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
|
||||
0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
|
||||
0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
|
||||
0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
|
||||
0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
|
||||
};
|
||||
|
||||
/* ─── Read N words from IP register space ─────────────────────────── */
|
||||
static void read_ip(uint32_t base, volatile uint32_t *dst, int n)
|
||||
static inline void uart_tx(unsigned char c)
|
||||
{
|
||||
for (int i = 0; i < n; i++)
|
||||
dst[i] = REG_RD(base + i * 4);
|
||||
}
|
||||
|
||||
/* ─── Write N words to IP register space ──────────────────────────── */
|
||||
static void write_ip(uint32_t base, const volatile uint32_t *src, int n)
|
||||
{
|
||||
for (int i = 0; i < n; i++)
|
||||
REG_WR(base + i * 4, src[i]);
|
||||
}
|
||||
|
||||
/* ─── Poll IP STATUS until done or error ──────────────────────────── */
|
||||
static void wait_done(void)
|
||||
{
|
||||
uint32_t status;
|
||||
do {
|
||||
status = REG_RD(MATMUL_STATUS);
|
||||
} while (!(status & (STATUS_DONE | STATUS_ERROR)));
|
||||
}
|
||||
|
||||
/* ─── CRC32 over ExtRAM result region (little-endian word → byte stream) ─ */
|
||||
static uint32_t compute_crc32(volatile uint32_t *extram)
|
||||
{
|
||||
uint32_t crc = 0xFFFFFFFF;
|
||||
uint32_t i, w;
|
||||
|
||||
for (i = 0; i < RESULT_WORDS; i++) {
|
||||
w = extram[DST_BASE + i];
|
||||
crc = crc32_table[(crc ^ (w & 0xFF)) & 0xFF] ^ (crc >> 8);
|
||||
crc = crc32_table[(crc ^ ((w >> 8) & 0xFF)) & 0xFF] ^ (crc >> 8);
|
||||
crc = crc32_table[(crc ^ ((w >> 16) & 0xFF)) & 0xFF] ^ (crc >> 8);
|
||||
crc = crc32_table[(crc ^ (w >> 24) ) & 0xFF] ^ (crc >> 8);
|
||||
while (!(UART_LSR & LSR_THRE)) {
|
||||
}
|
||||
return crc ^ 0xFFFFFFFF;
|
||||
UART_THR = c;
|
||||
}
|
||||
|
||||
/* ═══════════════════════════════════════════════════════════════════ */
|
||||
static void uart_puts(const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
uart_tx((unsigned char)*s++);
|
||||
}
|
||||
}
|
||||
|
||||
static void uart_puthex(uint32_t val)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 28; i >= 0; i -= 4) {
|
||||
unsigned char nibble = (unsigned char)((val >> i) & 0xF);
|
||||
uart_tx((unsigned char)(nibble < 10 ? ('0' + nibble) : ('a' + nibble - 10)));
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef MATMUL_GROUP_NUM
|
||||
#define MATMUL_GROUP_NUM 5000
|
||||
#endif
|
||||
|
||||
unsigned long UART_BASE = 0xbf000000;
|
||||
|
||||
#define EXTRAM_BASE_PHYS 0x1c400000u
|
||||
|
||||
#define SRC_BASE_WORDS 0u
|
||||
#define DST_BASE_WORDS (SRC_BASE_WORDS + MATMUL_GROUP_NUM * 32u)
|
||||
|
||||
#define EXTRAM_PHYS_AB(g) (EXTRAM_BASE_PHYS + (SRC_BASE_WORDS * 4u) + (uint32_t)(g) * 128u)
|
||||
#define EXTRAM_PHYS_C(g) (EXTRAM_BASE_PHYS + (DST_BASE_WORDS * 4u) + (uint32_t)(g) * 192u)
|
||||
|
||||
#define MATMUL_BASE_UNCACHED 0xbf500000u
|
||||
#define MATMUL_CRC (*(volatile uint32_t *)(MATMUL_BASE_UNCACHED + 0x010u))
|
||||
|
||||
int main(void)
|
||||
{
|
||||
volatile uint32_t *extram = (volatile uint32_t *)EXTRAM_BASE;
|
||||
uint32_t a_buf[16], b_buf[16], c_buf[48];
|
||||
uint32_t crc;
|
||||
int g, i;
|
||||
|
||||
/* ── Start marker (must be first output) ──────────────────── */
|
||||
printf("MATMUL_START\n");
|
||||
|
||||
/* ── Process all 5000 groups ──────────────────────────────── */
|
||||
for (g = 0; g < N_GROUPS; g++) {
|
||||
/* Read A[16] + B[16] from ExtRAM */
|
||||
for (i = 0; i < 16; i++) {
|
||||
a_buf[i] = extram[SRC_BASE + g * 32 + i];
|
||||
b_buf[i] = extram[SRC_BASE + g * 32 + 16 + i];
|
||||
}
|
||||
/* Load into IP registers */
|
||||
write_ip(MATMUL_A_BASE, a_buf, 16);
|
||||
write_ip(MATMUL_B_BASE, b_buf, 16);
|
||||
/* Clear status flags, start computation */
|
||||
REG_WR(MATMUL_STATUS, STATUS_DONE | STATUS_ERROR);
|
||||
REG_WR(MATMUL_CTRL, CTRL_START);
|
||||
/* Wait for hardware to finish */
|
||||
wait_done();
|
||||
/* Read C[48] from IP, write to ExtRAM result region */
|
||||
read_ip(MATMUL_C_BASE, c_buf, 48);
|
||||
for (i = 0; i < 48; i++)
|
||||
extram[DST_BASE + g * 48 + i] = c_buf[i];
|
||||
if (MATMUL_GROUP_NUM <= 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ── CRC32 over result region ─────────────────────────────── */
|
||||
crc = compute_crc32(extram);
|
||||
uart_puts("MATMUL_START\n");
|
||||
|
||||
/* ── Final markers ────────────────────────────────────────── */
|
||||
printf("MATMUL_CRC32=%08lx\n", (unsigned long)crc);
|
||||
printf("MATMUL_DONE\n");
|
||||
DMA_SEQ->STATUS = SEQ_DONE_BIT;
|
||||
DMA_SEQ->SRC_BASE = EXTRAM_PHYS_AB(0);
|
||||
DMA_SEQ->DST_BASE = EXTRAM_PHYS_C(0);
|
||||
DMA_SEQ->GROUPS = MATMUL_GROUP_NUM;
|
||||
DMA_SEQ->MAT_BASE = 0x1f500000u;
|
||||
DMA_SEQ->SRC_STRIDE = 128u;
|
||||
DMA_SEQ->DST_STRIDE = 192u;
|
||||
DMA_SEQ->CTRL = SEQ_START_BIT;
|
||||
|
||||
while ((DMA_SEQ->STATUS & SEQ_DONE_BIT) == 0u) {
|
||||
}
|
||||
DMA_SEQ->STATUS = SEQ_DONE_BIT;
|
||||
|
||||
crc = MATMUL_CRC;
|
||||
|
||||
uart_puts("MATMUL_CRC32=");
|
||||
uart_puthex(crc);
|
||||
uart_puts("\nMATMUL_DONE\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user