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Add direct CDMA matmul path

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FallenSigh
2026-07-04 19:15:34 +08:00
parent 3f7c9b7a37
commit b7553418fa
9 changed files with 966 additions and 10112 deletions
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92
rtl/soc_top.v
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@@ -603,7 +603,24 @@ wire axiOut_7_bvalid ;
wire axiOut_7_bready ;
wire confreg_int;
wire matmul_intr;
wire matmul_intr;
wire matmul_ep_wr_valid;
wire [3:0] matmul_ep_wr_id;
wire [3:0] matmul_ep_wr_bank;
wire [7:0] matmul_ep_wr_word_addr;
wire [31:0] matmul_ep_wr_data;
wire matmul_ep_wr_ready;
wire matmul_ep_rd_valid;
wire [3:0] matmul_ep_rd_id;
wire [3:0] matmul_ep_rd_bank;
wire [7:0] matmul_ep_rd_word_addr;
wire [31:0] matmul_ep_rd_data;
wire matmul_ep_rd_ready;
wire matmul_direct_start_valid;
wire matmul_direct_start_bank;
wire matmul_direct_done_clear;
wire matmul_direct_crc_clear;
wire matmul_direct_done;
wire mlkem_intr;
AxiCrossbar_2x8 u_AxiCrossbar_2x8 (
@@ -1513,14 +1530,35 @@ matmul_axi_slave u_matmul_axi_slave (
.s_axi_arvalid (axiOut_7_arvalid),
.s_axi_arready (axiOut_7_arready),
.s_axi_rid (axiOut_7_rid ),
.s_axi_rdata (axiOut_7_rdata ),
.s_axi_rresp (axiOut_7_rresp ),
.s_axi_rlast (axiOut_7_rlast ),
.s_axi_rvalid (axiOut_7_rvalid),
.s_axi_rready (axiOut_7_rready),
.intr (matmul_intr)
);
.s_axi_rid (axiOut_7_rid ),
.s_axi_rdata (axiOut_7_rdata ),
.s_axi_rresp (axiOut_7_rresp ),
.s_axi_rlast (axiOut_7_rlast ),
.s_axi_rvalid (axiOut_7_rvalid),
.s_axi_rready (axiOut_7_rready),
.ep_wr_valid (matmul_ep_wr_valid),
.ep_wr_id (matmul_ep_wr_id),
.ep_wr_bank (matmul_ep_wr_bank),
.ep_wr_word_addr(matmul_ep_wr_word_addr),
.ep_wr_data (matmul_ep_wr_data),
.ep_wr_ready (matmul_ep_wr_ready),
.ep_rd_valid (matmul_ep_rd_valid),
.ep_rd_id (matmul_ep_rd_id),
.ep_rd_bank (matmul_ep_rd_bank),
.ep_rd_word_addr(matmul_ep_rd_word_addr),
.ep_rd_data (matmul_ep_rd_data),
.ep_rd_ready (matmul_ep_rd_ready),
.mat_start_valid(matmul_direct_start_valid),
.mat_start_bank (matmul_direct_start_bank),
.mat_done_clear (matmul_direct_done_clear),
.mat_crc_clear (matmul_direct_crc_clear),
.mat_done (matmul_direct_done),
.intr (matmul_intr)
);
wire [31:0] cdma_s_awaddr;
wire [2:0] cdma_s_awprot;
@@ -1684,11 +1722,31 @@ snix_axil_cdma_mux #(
.mm2mm_rresp (dma_m_rresp),
.mm2mm_rlast (dma_m_rlast),
.mm2mm_ruser (1'b0),
.mm2mm_rvalid (dma_m_rvalid),
.mm2mm_rready (dma_m_rready),
// 全局中断输出
.dma_finish (dma_finish)
);
endmodule
.mm2mm_rvalid (dma_m_rvalid),
.mm2mm_rready (dma_m_rready),
// 本地直连到 matmul，不经过 AXI crossbar
.ep_wr_valid (matmul_ep_wr_valid),
.ep_wr_id (matmul_ep_wr_id),
.ep_wr_bank (matmul_ep_wr_bank),
.ep_wr_word_addr (matmul_ep_wr_word_addr),
.ep_wr_data (matmul_ep_wr_data),
.ep_wr_ready (matmul_ep_wr_ready),
.ep_rd_valid (matmul_ep_rd_valid),
.ep_rd_id (matmul_ep_rd_id),
.ep_rd_bank (matmul_ep_rd_bank),
.ep_rd_word_addr (matmul_ep_rd_word_addr),
.ep_rd_data (matmul_ep_rd_data),
.ep_rd_ready (matmul_ep_rd_ready),
.mat_start_valid (matmul_direct_start_valid),
.mat_start_bank (matmul_direct_start_bank),
.mat_done_clear (matmul_direct_done_clear),
.mat_crc_clear (matmul_direct_crc_clear),
.mat_done (matmul_direct_done),
// 全局中断输出
.dma_finish (dma_finish)
);
endmodule