From acb158a392e98aad7a0245e68b59582851f3f85c Mon Sep 17 00:00:00 2001
From: FallenSigh <fallensigh@gmail.com>
Date: Thu, 25 Jun 2026 00:47:43 +0800
Subject: [PATCH] Update matmul RTL, remove shift_add_mult.v

---
 rtl/ip/matmul/matmul_axi_slave.v | 62 ++++++++++++++++++++++++++++++--
 rtl/ip/matmul/shift_add_mult.v   | 49 -------------------------
 2 files changed, 60 insertions(+), 51 deletions(-)
 delete mode 100644 rtl/ip/matmul/shift_add_mult.v

diff --git a/rtl/ip/matmul/matmul_axi_slave.v b/rtl/ip/matmul/matmul_axi_slave.v
index d4f4b5a..5d8de43 100644
--- a/rtl/ip/matmul/matmul_axi_slave.v
+++ b/rtl/ip/matmul/matmul_axi_slave.v
@@ -1,3 +1,60 @@
+// ═══════════════════════════════════════════════════════
+//  基础时序乘法器模块 (无 DSP，移位累加，32个周期)
+// ═══════════════════════════════════════════════════════
+module shift_add_mult (
+    input             clk,
+    input             rstn,
+    input             start,
+    input      [31:0] a,
+    input      [31:0] b,
+    output reg [63:0] p,
+    output reg        done
+);
+    reg [5:0]  cnt;
+    reg [63:0] a_reg;
+    reg [31:0] b_reg;
+    reg        busy;
+
+    always @(posedge clk) begin
+        if (!rstn) begin
+            busy <= 1'b0;
+            done <= 1'b0;
+            p    <= 64'b0;
+            cnt  <= 6'd0;
+            a_reg<= 64'b0;
+            b_reg<= 32'b0;
+        end else begin
+            if (start && !busy) begin
+                a_reg <= {32'b0, a};
+                b_reg <= b;
+                p     <= 64'b0;
+                cnt   <= 6'd0;
+                busy  <= 1'b1;
+                done  <= 1'b0;
+            end else if (busy) begin
+                if (cnt == 6'd32) begin
+                    busy <= 1'b0;
+                    done <= 1'b1;
+                end else begin
+                    // 如果 b 的当前最低位为 1，则累加 a
+                    if (b_reg[0]) begin
+                        p <= p + a_reg;
+                    end
+                    a_reg <= a_reg << 1;
+                    b_reg <= b_reg >> 1;
+                    cnt   <= cnt + 6'd1;
+                end
+            end else begin
+                done <= 1'b0;
+            end
+        end
+    end
+endmodule
+
+
+// ═══════════════════════════════════════════════════════
+//  矩阵乘法器顶层模块 (AXI Burst Slave + Ping-Pong)
+// ═══════════════════════════════════════════════════════
 module matmul_axi_slave (
     input             clk,
     input             resetn,
@@ -259,12 +316,13 @@ module matmul_axi_slave (
         end
     end
 
+    // 修复：将 wire 声明提取到 always 块外部
+    wire [11:0] current_r_offset = (r_state == R_DATA) ? r_offset : s_axi_araddr[11:0];
+
     // 组合逻辑准备 Read 数据
     always @(*) begin
         s_axi_rdata = 32'b0;
         if (r_state == R_DATA || (r_state == R_IDLE && s_axi_arvalid)) begin
-            wire [11:0] current_r_offset = (r_state == R_DATA) ? r_offset : s_axi_araddr[11:0];
-            
             if (current_r_offset == ADDR_CTRL) 
                 s_axi_rdata = {30'b0, req_1, req_0};
             else if (current_r_offset == ADDR_STATUS)
diff --git a/rtl/ip/matmul/shift_add_mult.v b/rtl/ip/matmul/shift_add_mult.v
deleted file mode 100644
index 79dd8ef..0000000
--- a/rtl/ip/matmul/shift_add_mult.v
+++ /dev/null
@@ -1,49 +0,0 @@
-module shift_add_mult (
-    input             clk,
-    input             rstn,
-    input             start,
-    input      [31:0] a,
-    input      [31:0] b,
-    output reg [63:0] p,
-    output reg        done
-);
-    reg [5:0]  cnt;
-    reg [63:0] a_reg;
-    reg [31:0] b_reg;
-    reg        busy;
-
-    always @(posedge clk) begin
-        if (!rstn) begin
-            busy <= 1'b0;
-            done <= 1'b0;
-            p    <= 64'b0;
-            cnt  <= 6'd0;
-            a_reg<= 64'b0;
-            b_reg<= 32'b0;
-        end else begin
-            if (start && !busy) begin
-                a_reg <= {32'b0, a};
-                b_reg <= b;
-                p     <= 64'b0;
-                cnt   <= 6'd0;
-                busy  <= 1'b1;
-                done  <= 1'b0;
-            end else if (busy) begin
-                if (cnt == 6'd32) begin
-                    busy <= 1'b0;
-                    done <= 1'b1;
-                end else begin
-                    // 如果 b 的当前最低位为 1，则累加 a
-                    if (b_reg[0]) begin
-                        p <= p + a_reg;
-                    end
-                    a_reg <= a_reg << 1;
-                    b_reg <= b_reg >> 1;
-                    cnt   <= cnt + 6'd1;
-                end
-            end else begin
-                done <= 1'b0;
-            end
-        end
-    end
-endmodule
\ No newline at end of file