Restore timing + switch to polling + disable CPU interrupts (IE=0)

sdk/software/bsp/env/start.S

@@ -142,12 +142,12 @@ _start:
     li.w        t1, 0x1
     csrwr       t1, csr_ticlr
 
-    #enable int 
+    #disable int (IE=0, all polling-mode)
     li.w        t1, 0x4
 #ifdef RTThread
     csrxchg     zero, t1, csr_crmd
 #else
-    csrxchg     t1, t1, csr_crmd
+    csrxchg     zero, t1, csr_crmd
 #endif
     csrwr       zero, csr_prmd
     li.w        t1, 0x1fff

sdk/software/bsp/env/trap_handler.S

@@ -153,18 +153,12 @@ handle_hwi0:
 
     b trap_jump_exit
 
-# HWI1 处理程序 - DMA完成
+# HWI1 处理程序
 handle_hwi1:
-
-    bl DMA_IntrHandler
-
     b trap_jump_exit
 
-# HWI2 处理程序 - Matmul完成
+# HWI2 处理程序
 handle_hwi2:
-
-    bl MATMUL_IntrHandler
-
     b trap_jump_exit
 
 # HWI3 处理程序
@@ -192,13 +186,3 @@ handle_hwi7:
 HWI0_IntrHandler:
 1:
   b 1b
-
-.weak DMA_IntrHandler
-DMA_IntrHandler:
-1:
-  b 1b
-
-.weak MATMUL_IntrHandler
-MATMUL_IntrHandler:
-1:
-  b 1b

sdk/software/examples/asm/user-sample.c

@@ -13,6 +13,7 @@
 #include <stdint.h>
 
 #include <common_func.h>
+#include <confreg_time.h>
 #include <dma.h>
 
 /* ─── Configurable group count (default 10 for fast local testing) ─── */
@@ -22,6 +23,8 @@
 
 /* ─── BSP globals ─────────────────────────────────────────────────── */
 unsigned long UART_BASE              = 0xbf000000;
+unsigned long CONFREG_TIMER_BASE     = 0xbf20f100;
+unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L;
 unsigned long CORE_CLOCKS_PER_SEC    = 33000000L;
 
 /* ─── Memory layout ────────────────────────────────────────────────── */
@@ -63,43 +66,16 @@ unsigned long CORE_CLOCKS_PER_SEC    = 33000000L;
 #define REG_WR(addr, val) (*(volatile uint32_t *)(addr) = (uint32_t)(val))
 #define REG_RD(addr)      (*(volatile uint32_t *)(addr))
 
-static volatile int matmul_done_flag = 0;
+static void wait_matmul_done(void)
-static volatile int dma0_done_flag   = 0;
-static volatile int dma1_done_flag   = 0;
-
-void MATMUL_IntrHandler(void)
 {
-    matmul_done_flag = 1;
+    while (!(REG_RD(MATMUL_STATUS) & STATUS_DONE)) { }
-    REG_WR(MATMUL_STATUS, STATUS_DONE);  // W1C: deassert intr
+    REG_WR(MATMUL_STATUS, STATUS_DONE);  // W1C: deassert
 }
 
-void DMA_IntrHandler(void)
+static void wait_dma_done(int ch)
 {
-    if (DMA_CH(0)->STATUS & STATUS_DONE_BIT) {
+    while (!(DMA_CH(ch)->STATUS & STATUS_DONE_BIT)) { }
-        dma0_done_flag = 1;
+    DMA_CH(ch)->STATUS = STATUS_DONE_BIT;  // W1C
-        DMA_CH(0)->STATUS = STATUS_DONE_BIT;
-    }
-    if (DMA_CH(1)->STATUS & STATUS_DONE_BIT) {
-        dma1_done_flag = 1;
-        DMA_CH(1)->STATUS = STATUS_DONE_BIT;
-    }
-}
-
-static void wait_matmul_done_intr(void)
-{
-    while (!matmul_done_flag) { }
-    matmul_done_flag = 0;
-}
-
-static void wait_dma_done_intr(int ch)
-{
-    if (ch == 0) {
-        while (!dma0_done_flag) { }
-        dma0_done_flag = 0;
-    } else {
-        while (!dma1_done_flag) { }
-        dma1_done_flag = 0;
-    }
 }
 
 /* ═══════════════════════════════════════════════════════════════════ */
@@ -108,7 +84,7 @@ int main(void)
     if (MATMUL_GROUP_NUM <= 0) return 0;
 
     volatile uint32_t *extram = (volatile uint32_t *)EXTRAM_BASE_UNCACHED;
-    uint32_t crc;
+    uint32_t crc, t_prologue, t_mainloop, t_epilogue;
     int g;
 
     // Ping-Pong Register Address Arrays (Physical for DMA)
@@ -126,14 +102,17 @@ int main(void)
     REG_WR(MATMUL_CRC, 0);          // 复位硬件 CRC32 为 0xFFFFFFFF 
 
     /* ── Prologue: 第0组数据初始化 ────────────────────────── */
+    t_prologue = get_ns();
     // DMA Ch0: 从 ExtRAM 将 Group 0 的 A、B (128 bytes) 搬入 IP 的 Bank 0
     dma_start_transfer(0, EXTRAM_PHYS_AB(0), phys_bank_AB[0], 128, 10);
-    wait_dma_done_intr(0);
+    wait_dma_done(0);
     
     // 启动 IP Bank 0 计算
     REG_WR(MATMUL_CTRL, ctrl_start[0]);
+    t_prologue = get_ns() - t_prologue;
 
     /* ── Main Loop: 硬件完全流水线 (Overlapped Execution) ──── */
+    t_mainloop = get_ns();
     // 在 g 循环中: 
     // IP 正在计算 prev_bank (g-1)
     // DMA_CH0 正在加载 cur_bank (g)
@@ -146,36 +125,44 @@ int main(void)
         dma_start_transfer(0, EXTRAM_PHYS_AB(g), phys_bank_AB[cur_bank], 128, 10);
 
         // 2. 等待上一组在 IP 中的计算完成
-        wait_matmul_done_intr();
+        wait_matmul_done();
 
         // 3. 确保上一次的结果写回 (Channel 1) 已经空闲
         if (g > 1) {
-            wait_dma_done_intr(1);
+            wait_dma_done(1);
         }
 
         // 4. 发起写回刚才计算完成的结果 (Channel 1: IP -> Memory)
         dma_start_transfer(1, phys_bank_C[prev_bank], EXTRAM_PHYS_C(g - 1), 192, 20);
 
         // 5. 确保当前要计算的输入数据 (Channel 0) 已经加载完毕
-        wait_dma_done_intr(0);
+        wait_dma_done(0);
 
         // 6. 立即启动当前组在 IP 中的计算
         REG_WR(MATMUL_CTRL, ctrl_start[cur_bank]);
     }
+    t_mainloop = get_ns() - t_mainloop;
 
     /* ── Epilogue: 收尾最后一组 ───────────────────────────── */
-    wait_matmul_done_intr(); // 等待最后一次计算完成
+    t_epilogue = get_ns();
-    wait_dma_done_intr(1);   // 确保之前的 DMA CH1 空闲
+    wait_matmul_done(); // 等待最后一次计算完成
+    wait_dma_done(1);   // 确保之前的 DMA CH1 空闲
     
     // DMA CH1 将最后一组结果写回
     dma_start_transfer(1, phys_bank_C[(MATMUL_GROUP_NUM - 1) % 2], EXTRAM_PHYS_C(MATMUL_GROUP_NUM - 1), 192, 20);
-    wait_dma_done_intr(1);
+    wait_dma_done(1);
+    t_epilogue = get_ns() - t_epilogue;
 
     /* ── Read hardware CRC32 result ──────────────────────────── */
     crc = REG_RD(MATMUL_CRC);
 
     /* ── Final markers ────────────────────────────────────────── */
     printf("MATMUL_CRC32=%08lx\n", (unsigned long)crc);
+    printf("TIME_PROLOGUE=%lu\n", (unsigned long)t_prologue);
+    printf("TIME_LOOP=%lu\n", (unsigned long)t_mainloop);
+    printf("TIME_LOOP_PER=%lu\n", (unsigned long)(t_mainloop / MATMUL_GROUP_NUM));
+    printf("TIME_EPILOGUE=%lu\n", (unsigned long)t_epilogue);
+    printf("TIME_TOTAL=%lu\n", (unsigned long)(t_prologue + t_mainloop + t_epilogue));
     printf("MATMUL_DONE\n");
 
     return 0;