fallensigh/ciciec2026
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Restore timing + switch to polling + disable CPU interrupts (IE=0)

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FallenSigh
2026-06-26 01:01:48 +08:00
parent 115466353d
commit a2b496ca8d
3 changed files with 32 additions and 61 deletions
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4
sdk/software/bsp/env/start.S vendored
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@@ -142,12 +142,12 @@ _start:
li.w t1, 0x1
csrwr t1, csr_ticlr
#enable int
#disable int (IE=0, all polling-mode)
li.w t1, 0x4
#ifdef RTThread
csrxchg zero, t1, csr_crmd
#else
csrxchg t1, t1, csr_crmd
csrxchg zero, t1, csr_crmd
#endif
csrwr zero, csr_prmd
li.w t1, 0x1fff

20
sdk/software/bsp/env/trap_handler.S vendored
View File

@@ -153,18 +153,12 @@ handle_hwi0:
b trap_jump_exit
# HWI1 处理程序 - DMA完成
# HWI1 处理程序
handle_hwi1:
bl DMA_IntrHandler
b trap_jump_exit
# HWI2 处理程序 - Matmul完成
# HWI2 处理程序
handle_hwi2:
bl MATMUL_IntrHandler
b trap_jump_exit
# HWI3 处理程序
@@ -192,13 +186,3 @@ handle_hwi7:
HWI0_IntrHandler:
1:
b 1b
.weak DMA_IntrHandler
DMA_IntrHandler:
1:
b 1b
.weak MATMUL_IntrHandler
MATMUL_IntrHandler:
1:
b 1b