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Add in read channel to debug C register readback

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FallenSigh
2026-06-25 03:44:54 +08:00
parent 3fb93131e5
commit 9c6b321d59
1 changed files with 3 additions and 1 deletions
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4
rtl/ip/matmul/matmul_axi_slave.v
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@@ -332,7 +332,7 @@ module matmul_axi_slave (
if (current_r_offset == ADDR_CTRL) if (current_r_offset == ADDR_CTRL)
s_axi_rdata = {30'b0, req_1, req_0}; s_axi_rdata = {30'b0, req_1, req_0};
else if (current_r_offset == ADDR_STATUS) else if (current_r_offset == ADDR_STATUS)
s_axi_rdata = {29'b0, error, done, busy}; // 完美兼容旧 TB s_axi_rdata = {29'b0, error, done, busy};
else if (current_r_offset >= ADDR_B0_A && current_r_offset < ADDR_B0_B) else if (current_r_offset >= ADDR_B0_A && current_r_offset < ADDR_B0_B)
s_axi_rdata = b0_a[(current_r_offset - ADDR_B0_A) >> 2]; s_axi_rdata = b0_a[(current_r_offset - ADDR_B0_A) >> 2];
else if (current_r_offset >= ADDR_B0_B && current_r_offset < ADDR_B0_C) else if (current_r_offset >= ADDR_B0_B && current_r_offset < ADDR_B0_C)
@@ -341,6 +341,8 @@ module matmul_axi_slave (
if (c0_part == 2'd0) s_axi_rdata = target_c0[31:0]; if (c0_part == 2'd0) s_axi_rdata = target_c0[31:0];
else if (c0_part == 2'd1) s_axi_rdata = target_c0[63:32]; else if (c0_part == 2'd1) s_axi_rdata = target_c0[63:32];
else s_axi_rdata = {30'b0, target_c0[65:64]}; else s_axi_rdata = {30'b0, target_c0[65:64]};
$display(\"RCH B0_C off=%h elem=%d part=%d data=%h raw=%h\",
current_r_offset, c0_elem, c0_part, s_axi_rdata, target_c0);
end end
else if (current_r_offset >= ADDR_B1_A && current_r_offset < ADDR_B1_B) else if (current_r_offset >= ADDR_B1_A && current_r_offset < ADDR_B1_B)
s_axi_rdata = b1_a[(current_r_offset - ADDR_B1_A) >> 2]; s_axi_rdata = b1_a[(current_r_offset - ADDR_B1_A) >> 2];