fix: revert UART FIFO batching — caused FIFO overflow + syserr on board

uart_puts(13B) + uart_puthex(8B) = 21 bytes without polling → FIFO overflow.
Board UART IP asserts AXI error → CPU syserr exception.
Simulation UART model is lenient, so sim passed but board failed.

Back to per-byte polling (safe).

sdk/software/examples/asm/user-sample.c

@@ -16,31 +16,21 @@
 #define UART_THR (*(volatile unsigned char *)0xbf000000)
 #define UART_LSR (*(volatile unsigned char *)0xbf000005)
 #define LSR_THRE  0x20
-#define UART_FIFO_DEPTH 16
 
 static inline void uart_tx(unsigned char c) {
     while (!(UART_LSR & LSR_THRE)) {}
     UART_THR = c;
 }
 
-/* Burst-write a null-terminated string — polls only when FIFO may be full */
 static void uart_puts(const char *s) {
-    int n = 0;
-    while (*s) {
-        UART_THR = *s++;
-        if (++n >= UART_FIFO_DEPTH) {
-            while (!(UART_LSR & LSR_THRE)) {}
-            n = 0;
-        }
-    }
+    while (*s) uart_tx(*s++);
 }
 
-/* Write 8 hex digits + suffix in one burst to minimize AXI polls */
 static void uart_puthex(unsigned int val) {
     int i;
     for (i = 28; i >= 0; i -= 4) {
         unsigned char nibble = (val >> i) & 0xF;
-        UART_THR = nibble < 10 ? '0' + nibble : 'a' + nibble - 10;
+        uart_tx(nibble < 10 ? '0' + nibble : 'a' + nibble - 10);
     }
 }