Sync fast SRAM read burst controller

rtl/ip/Bus_interconnects/axi2sram_sp_external.v

@@ -20,7 +20,8 @@
 module axi2sram_sp_external #(
     parameter AXI_ID_WIDTH      = 5,
     parameter AXI_ADDR_WIDTH    = 32,
-    parameter AXI_DATA_WIDTH    = 32
+    parameter AXI_DATA_WIDTH    = 32,
+    parameter FAST_READ_BURST   = 1
 )(
     input                         clk,
     input                         resetn,
@@ -246,7 +247,26 @@ module axi2sram_sp_external #(
                         // we already got everything
                     end
                     else begin
-                        state_d = READ_ADDR;
+                        if (FAST_READ_BURST) begin
+                            // Queue the next async-SRAM address for the clock
+                            // edge after the current read data is sampled.
+                            case (ax_req_q_burst)
+                                FIXED, INCR: req_addr_d = cons_addr;
+                                WRAP: begin
+                                    if (cons_addr == upper_wrap_boundary) begin
+                                        req_addr_d = wrap_boundary;
+                                    end else if (cons_addr > upper_wrap_boundary) begin
+                                        req_addr_d = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES);
+                                    end else begin
+                                        req_addr_d = cons_addr;
+                                    end
+                                end
+                            endcase
+                            cnt_d   = cnt_q + 1;
+                            state_d = READ;
+                        end else begin
+                            state_d = READ_ADDR;
+                        end
                     end
                 end
             end