remove dsp usage

rtl/ip/fft/axi_fft_wrapper.v

@@ -4,7 +4,7 @@
 `define FFT_OUT_RE_BASE 16'ha000
 `define FFT_OUT_IM_BASE 16'hb000
 
-(* use_dsp = "no" *)
+
 module fft_controller #(
     parameter FFT_LEN         = 1024, // FFT处理长度
     parameter BRAM_RD_LATENCY = 1,    // 适配 BRAM 的读延迟 (通常 Block RAM 开启输出寄存器为 1)

rtl/ip/mlkem/comp_decomp/comp_decomp_sync.v

@@ -11,7 +11,7 @@
 
 `include "defines.vh"
 
-(* use_dsp = "yes" *)
+(* use_dsp = "no" *)
 module comp_decomp_sync (
     input         clk,
     input         rst_n,
@@ -45,7 +45,7 @@ module comp_decomp_sync (
     reg        mode_s2;
     reg [4:0]  d_s2;
     reg [23:0] comp_dividend_s2;
-    reg [36:0] comp_qprod_est_s2;
+    (* use_dsp = "no" *) reg [36:0] comp_qprod_est_s2;
     reg [23:0] decomp_rounded_s2;
     reg        valid_s2;
 
@@ -60,7 +60,7 @@ module comp_decomp_sync (
     reg [4:0]  d_s4;
     reg [23:0] comp_dividend_s4;
     reg [12:0] comp_q_est_s4;
-    reg [24:0] comp_q_mul_q_s4;
+    (* use_dsp = "no" *) reg [24:0] comp_q_mul_q_s4;
     reg [11:0] decomp_result_s4;
     reg        valid_s4;
 
@@ -83,7 +83,7 @@ module comp_decomp_sync (
 
     wire [23:0] coeff_ext_s0 = {12'd0, coeff_s0};
     wire [23:0] comp_dividend_next = (coeff_ext_s0 << d_s0) + 24'd1664;
-    wire [23:0] decomp_product_next = coeff_s0 * 12'd`Q;
+    (* use_dsp = "no" *) wire [23:0] decomp_product_next = coeff_s0 * 12'd`Q;
     wire [23:0] decomp_round_next =
         decomp_product_next + ((d_s0 == 5'd0) ? 24'd0 : (24'd1 << (d_s0 - 5'd1)));
 

rtl/ip/mlkem/ntt/barrett_mul.v

@@ -7,6 +7,7 @@
 // All multiplication widths explicitly controlled to avoid Verilog truncation.
 
 
+(* use_dsp = "no" *)
 module barrett_mul (
     input  [11:0] a,
     input  [11:0] b,
@@ -18,7 +19,7 @@ module barrett_mul (
 
     // Full product: a * b (both < 3329, product < 11,082,241 < 2^24)
     // Force 24-bit evaluation by extending operand
-    wire [23:0] p;
+    (* use_dsp = "no" *) wire [23:0] p;
     assign p = {12'd0, a} * b;
 
     // Extend p to 37 bits for multiplication with K
@@ -28,14 +29,14 @@ module barrett_mul (
     // Compute t_shifted = (p * K) >> 24
     // Use explicit wire for the product to control width
     /* verilator lint_off UNUSED */
-    wire [36:0] t_product;
+    (* use_dsp = "no" *) wire [36:0] t_product;
     /* verilator lint_on UNUSED */
     assign t_product = p_ext * K;
     wire [12:0] t_shifted;
     assign t_shifted = t_product[36:R];
 
     // q_approx = t_shifted * Q
-    wire [24:0] q_approx;
+    (* use_dsp = "no" *) wire [24:0] q_approx;
     assign q_approx = t_shifted * Q;
 
     // r = p - q_approx

rtl/ip/mlkem/ntt/barrett_mul_pipe.v

@@ -4,6 +4,7 @@
 // timing-critical NTT paths; the legacy barrett_mul remains combinational for
 // older users.
 
+(* use_dsp = "no" *)
 module barrett_mul_pipe (
     input         clk,
     input         rst_n,
@@ -16,16 +17,16 @@ module barrett_mul_pipe (
     localparam [24:0] Q25 = 25'd3329;
     localparam [12:0] K13 = 13'd5039;
 
-    reg [23:0] p_s1;
+    (* use_dsp = "no" *) reg [23:0] p_s1;
 
     reg [23:0] p_s2;
-    reg [36:0] tk_s2;
+    (* use_dsp = "no" *) reg [36:0] tk_s2;
 
     reg [23:0] p_s3;
     reg [12:0] q_s3;
 
     reg [24:0] p_s4;
-    reg [24:0] qprod_s4;
+    (* use_dsp = "no" *) reg [24:0] qprod_s4;
 
     reg [24:0] r0_s5;
     reg [24:0] r1_s6;

rtl/ip/mlkem/poly_mul/basecase_mul_pipe.v

@@ -4,6 +4,7 @@
 // The shared ntt/barrett_mul remains combinational for NTT users; this module
 // keeps the extra registers local to poly_mul_sync.
 
+(* use_dsp = "no" *)
 module basecase_mul_pipe (
     input         clk,
     input         rst_n,
@@ -21,7 +22,7 @@ module basecase_mul_pipe (
 
     function [12:0] barrett_q;
         input [23:0] p;
-        reg   [36:0] prod;
+        (* use_dsp = "no" *) reg [36:0] prod;
         begin
             prod = {13'd0, p} * K13;
             barrett_q = prod[36:24];
@@ -31,7 +32,7 @@ module basecase_mul_pipe (
     function [11:0] barrett_reduce;
         input [23:0] p;
         input [12:0] qe;
-        reg   [24:0] q_approx;
+        (* use_dsp = "no" *) reg [24:0] q_approx;
         reg   [24:0] r0;
         reg   [24:0] r1;
         reg   [24:0] r2;
@@ -55,7 +56,7 @@ module basecase_mul_pipe (
     endfunction
 
     // Stage 1: first-level scalar products.
-    reg [23:0] p10, p11, p12, p13;
+    (* use_dsp = "no" *) reg [23:0] p10, p11, p12, p13;
     reg [11:0] zeta_s1;
 
     // Stage 2: Barrett quotient estimates for first-level products.
@@ -69,7 +70,7 @@ module basecase_mul_pipe (
 
     // Stage 4: zeta product for c0's second Barrett multiply.
     reg [11:0] t1_s4, t3_s4, t4_s4;
-    reg [23:0] pz_s4;
+    (* use_dsp = "no" *) reg [23:0] pz_s4;
 
     // Stage 5: Barrett quotient estimate for zeta product.
     reg [11:0] t1_s5, t3_s5, t4_s5;

rtl/ip/mlkem/top/mlkem_axi_slave.v

@@ -25,7 +25,7 @@
 //   0x2000..0x2FFF DK  W: preload dk_in, R: read generated full dk
 //   0x3000..0x3FFF CT  W: preload c_in,  R: read generated ciphertext
 
-(* use_dsp = "no" *)
+
 module mlkem_axi_slave (
     input             clk,        // mlkem_clk AXI-side clock after Axi_CDC
     input             resetn,     // mlkem_resetn, active low

rtl/ip/mlkem/top/mlkem_top.v

@@ -22,7 +22,7 @@
 
 `include "defines.vh"
 
-(* use_dsp = "no" *)
+
 module mlkem_top #(
     parameter KMAX = 4               // storage sizing (worst case = ML-KEM-1024)
 ) (