remove dsp usage
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@@ -7,6 +7,7 @@
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// All multiplication widths explicitly controlled to avoid Verilog truncation.
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(* use_dsp = "no" *)
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module barrett_mul (
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input [11:0] a,
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input [11:0] b,
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@@ -18,7 +19,7 @@ module barrett_mul (
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// Full product: a * b (both < 3329, product < 11,082,241 < 2^24)
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// Force 24-bit evaluation by extending operand
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wire [23:0] p;
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(* use_dsp = "no" *) wire [23:0] p;
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assign p = {12'd0, a} * b;
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// Extend p to 37 bits for multiplication with K
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@@ -28,14 +29,14 @@ module barrett_mul (
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// Compute t_shifted = (p * K) >> 24
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// Use explicit wire for the product to control width
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/* verilator lint_off UNUSED */
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wire [36:0] t_product;
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(* use_dsp = "no" *) wire [36:0] t_product;
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/* verilator lint_on UNUSED */
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assign t_product = p_ext * K;
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wire [12:0] t_shifted;
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assign t_shifted = t_product[36:R];
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// q_approx = t_shifted * Q
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wire [24:0] q_approx;
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(* use_dsp = "no" *) wire [24:0] q_approx;
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assign q_approx = t_shifted * Q;
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// r = p - q_approx
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