remove dsp usage

rtl/ip/mlkem/ntt/barrett_mul.v

@@ -7,6 +7,7 @@
 // All multiplication widths explicitly controlled to avoid Verilog truncation.
 
 
+(* use_dsp = "no" *)
 module barrett_mul (
     input  [11:0] a,
     input  [11:0] b,
@@ -18,7 +19,7 @@ module barrett_mul (
 
     // Full product: a * b (both < 3329, product < 11,082,241 < 2^24)
     // Force 24-bit evaluation by extending operand
-    wire [23:0] p;
+    (* use_dsp = "no" *) wire [23:0] p;
     assign p = {12'd0, a} * b;
 
     // Extend p to 37 bits for multiplication with K
@@ -28,14 +29,14 @@ module barrett_mul (
     // Compute t_shifted = (p * K) >> 24
     // Use explicit wire for the product to control width
     /* verilator lint_off UNUSED */
-    wire [36:0] t_product;
+    (* use_dsp = "no" *) wire [36:0] t_product;
     /* verilator lint_on UNUSED */
     assign t_product = p_ext * K;
     wire [12:0] t_shifted;
     assign t_shifted = t_product[36:R];
 
     // q_approx = t_shifted * Q
-    wire [24:0] q_approx;
+    (* use_dsp = "no" *) wire [24:0] q_approx;
     assign q_approx = t_shifted * Q;
 
     // r = p - q_approx

rtl/ip/mlkem/ntt/barrett_mul_pipe.v

@@ -4,6 +4,7 @@
 // timing-critical NTT paths; the legacy barrett_mul remains combinational for
 // older users.
 
+(* use_dsp = "no" *)
 module barrett_mul_pipe (
     input         clk,
     input         rst_n,
@@ -16,16 +17,16 @@ module barrett_mul_pipe (
     localparam [24:0] Q25 = 25'd3329;
     localparam [12:0] K13 = 13'd5039;
 
-    reg [23:0] p_s1;
+    (* use_dsp = "no" *) reg [23:0] p_s1;
 
     reg [23:0] p_s2;
-    reg [36:0] tk_s2;
+    (* use_dsp = "no" *) reg [36:0] tk_s2;
 
     reg [23:0] p_s3;
     reg [12:0] q_s3;
 
     reg [24:0] p_s4;
-    reg [24:0] qprod_s4;
+    (* use_dsp = "no" *) reg [24:0] qprod_s4;
 
     reg [24:0] r0_s5;
     reg [24:0] r1_s6;