fallensigh/ciciec2026
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remove dsp usage

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FallenSigh
2026-07-08 03:18:10 +08:00
parent 0c85a20b4e
commit 83473b66aa
7 changed files with 20 additions and 17 deletions
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8
rtl/ip/mlkem/comp_decomp/comp_decomp_sync.v
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@@ -11,7 +11,7 @@
`include "defines.vh"
(* use_dsp = "yes" *)
(* use_dsp = "no" *)
module comp_decomp_sync (
input clk,
input rst_n,
@@ -45,7 +45,7 @@ module comp_decomp_sync (
reg mode_s2;
reg [4:0] d_s2;
reg [23:0] comp_dividend_s2;
reg [36:0] comp_qprod_est_s2;
(* use_dsp = "no" *) reg [36:0] comp_qprod_est_s2;
reg [23:0] decomp_rounded_s2;
reg valid_s2;
@@ -60,7 +60,7 @@ module comp_decomp_sync (
reg [4:0] d_s4;
reg [23:0] comp_dividend_s4;
reg [12:0] comp_q_est_s4;
reg [24:0] comp_q_mul_q_s4;
(* use_dsp = "no" *) reg [24:0] comp_q_mul_q_s4;
reg [11:0] decomp_result_s4;
reg valid_s4;
@@ -83,7 +83,7 @@ module comp_decomp_sync (
wire [23:0] coeff_ext_s0 = {12'd0, coeff_s0};
wire [23:0] comp_dividend_next = (coeff_ext_s0 << d_s0) + 24'd1664;
wire [23:0] decomp_product_next = coeff_s0 * 12'd`Q;
(* use_dsp = "no" *) wire [23:0] decomp_product_next = coeff_s0 * 12'd`Q;
wire [23:0] decomp_round_next =
decomp_product_next + ((d_s0 == 5'd0) ? 24'd0 : (24'd1 << (d_s0 - 5'd1)));