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perf(matmul): pre-fire DMA Ch0 load + inline wait/DMA start + XOR bank toggle

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user-sample.c v2 optimizations:
- Pre-fire DMA Ch0 load at loop tail to overlap fully with IP compute
- Inline wait_matmul_done/wait_dma_done to eliminate function call overhead
- Inline DMA register writes, skip redundant STATUS_BUSY_BIT check
- Replace g%2 with XOR bank toggle (bank ^= 1)
- Cache volatile pointers in locals (ch0, ch1, mat_status, mat_ctrl)

Makefile: bump -O2 to -O3
This commit is contained in:
FallenSigh
2026-06-26 03:39:32 +08:00
parent a2b496ca8d
commit 81c636fb56
4 changed files with 508 additions and 471 deletions
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2
sdk/software/examples/asm/Makefile
View File

@@ -1,7 +1,7 @@
TARGET = user-sample
MATMUL_GROUP_NUM ?= 5000
CFLAGS += -O2 -g -DMATMUL_GROUP_NUM=$(MATMUL_GROUP_NUM)
CFLAGS += -O3 -g -DMATMUL_GROUP_NUM=$(MATMUL_GROUP_NUM)
C_SRCS := $(wildcard ./*.c )

183
sdk/software/examples/asm/user-sample.c
View File

@@ -1,14 +1,19 @@
/**
* user-sample - CIC-IEC 2026 Stage 3 Evaluation Program
*
* (ULTIMATE PERFORMANCE DMA + PING-PONG BUFFER ARCHITECTURE)
* (ULTIMATE PERFORMANCE DMA + PING-PONG BUFFER ARCHITECTURE v2)
*
* Utilizes true DMA transfers (Channel 0 for memory->IP, Channel 1 for IP->memory)
* Optimizations over v1:
* 1. Pre-fire DMA Ch0 load at loop tail → fully overlaps with IP compute
* 2. Inlined wait loops → zero function-call overhead in hot path
* 3. Inlined DMA start → skips redundant STATUS_BUSY_BIT check
* 4. XOR bank toggle → avoids g%2 recomputation per iteration
*
* Utilizes true DMA transfers (Channel 0 for memory→IP, Channel 1 for IP→memory)
* perfectly overlapped with Hardware IP computation to achieve Zero-Wait execution.
*/
#include <stdio.h>
#include <string.h>
#include <stdbool.h>
#include <stdint.h>
@@ -16,7 +21,7 @@
#include <confreg_time.h>
#include <dma.h>
/* ─── Configurable group count (default 10 for fast local testing) ─── */
/* ─── Configurable group count (default 5000) ──────────────────────── */
#ifndef MATMUL_GROUP_NUM
#define MATMUL_GROUP_NUM 5000
#endif
@@ -49,7 +54,7 @@ unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
// DMA Physical Addresses for IP Space
// (A and B are contiguous: A is 0x100~0x13F, B is 0x140~0x17F. Total 128 bytes)
#define MATMUL_PHYS_B0_AB (MATMUL_BASE_PHYS + 0x100)
#define MATMUL_PHYS_B0_AB (MATMUL_BASE_PHYS + 0x100)
#define MATMUL_PHYS_B0_C (MATMUL_BASE_PHYS + 0x180) // 192 bytes
#define MATMUL_PHYS_B1_AB (MATMUL_BASE_PHYS + 0x300)
#define MATMUL_PHYS_B1_C (MATMUL_BASE_PHYS + 0x380)
@@ -62,99 +67,151 @@ unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
// Hardware CRC register (offset 0x010 in matmul IP)
#define MATMUL_CRC (MATMUL_BASE_UNCACHED + 0x010)
/* ─── Convenience macros ──────────────────────────────────────────── */
#define REG_WR(addr, val) (*(volatile uint32_t *)(addr) = (uint32_t)(val))
#define REG_RD(addr) (*(volatile uint32_t *)(addr))
static void wait_matmul_done(void)
{
while (!(REG_RD(MATMUL_STATUS) & STATUS_DONE)) { }
REG_WR(MATMUL_STATUS, STATUS_DONE); // W1C: deassert
}
static void wait_dma_done(int ch)
{
while (!(DMA_CH(ch)->STATUS & STATUS_DONE_BIT)) { }
DMA_CH(ch)->STATUS = STATUS_DONE_BIT; // W1C
}
/* ─── Pre-computed DMA burst control word ──────────────────────────── */
#define DMA_CTRL_VAL (CTRL_BURST_SIZE(2) | CTRL_BURST_LEN(63) | CTRL_START_BIT)
/* ═══════════════════════════════════════════════════════════════════ */
int main(void)
{
if (MATMUL_GROUP_NUM <= 0) return 0;
volatile uint32_t *extram = (volatile uint32_t *)EXTRAM_BASE_UNCACHED;
/* ── Hot-path local volatile pointers (one-time addr calc) ──────── */
volatile uint32_t *extram = (volatile uint32_t *)EXTRAM_BASE_UNCACHED;
volatile uint32_t *mat_status = (volatile uint32_t *)MATMUL_STATUS;
volatile uint32_t *mat_ctrl = (volatile uint32_t *)MATMUL_CTRL;
volatile uint32_t *mat_crc = (volatile uint32_t *)MATMUL_CRC;
volatile dma_ch_regs_t *ch0 = DMA_CH(0);
volatile dma_ch_regs_t *ch1 = DMA_CH(1);
uint32_t crc, t_prologue, t_mainloop, t_epilogue;
int g;
int g, bank;
// Ping-Pong Register Address Arrays (Physical for DMA)
uint32_t phys_bank_AB[2] = {MATMUL_PHYS_B0_AB, MATMUL_PHYS_B1_AB};
uint32_t phys_bank_C[2] = {MATMUL_PHYS_B0_C, MATMUL_PHYS_B1_C};
// IP Control Command Arrays
uint32_t ctrl_start[2] = {CTRL_START_B0, CTRL_START_B1};
/* ── Start marker (must be first output) ──────────────────── */
printf("MATMUL_START\n");
// 清理寄存器状态
REG_WR(MATMUL_STATUS, STATUS_DONE | STATUS_ERROR);
REG_WR(MATMUL_CRC, 0); // 复位硬件 CRC32 为 0xFFFFFFFF
// Reset IP state
*mat_status = STATUS_DONE | STATUS_ERROR;
*mat_crc = 0; // Reset hardware CRC32 to 0xFFFFFFFF
/* ── Prologue: 第0组数据初始化 ────────────────────────── */
/* ═══════════════════════════════════════════════════════════════
* PROLOGUE: Load group 0 → Bank 0, start IP, pre-fire group 1
* ═══════════════════════════════════════════════════════════════ */
t_prologue = get_ns();
// DMA Ch0: 从 ExtRAM 将 Group 0 的 A、B (128 bytes) 搬入 IP 的 Bank 0
dma_start_transfer(0, EXTRAM_PHYS_AB(0), phys_bank_AB[0], 128, 10);
wait_dma_done(0);
// 启动 IP Bank 0 计算
REG_WR(MATMUL_CTRL, ctrl_start[0]);
// DMA Ch0: Load group 0 A+B (128 bytes) from ExtRAM → IP Bank 0
ch0->SRC_ADDR = EXTRAM_PHYS_AB(0);
ch0->DST_ADDR = phys_bank_AB[0];
ch0->LENGTH = 128;
ch0->TAG = 10;
ch0->CTRL = DMA_CTRL_VAL;
while (!(ch0->STATUS & STATUS_DONE_BIT)) {}
ch0->STATUS = STATUS_DONE_BIT;
// Start IP Bank 0 (group 0)
*mat_ctrl = ctrl_start[0];
// Pre-fire: DMA Ch0 load group 1 → Bank 1 (overlaps with IP compute of group 0!)
if (MATMUL_GROUP_NUM > 1) {
ch0->SRC_ADDR = EXTRAM_PHYS_AB(1);
ch0->DST_ADDR = phys_bank_AB[1];
ch0->LENGTH = 128;
ch0->TAG = 10;
ch0->CTRL = DMA_CTRL_VAL;
}
t_prologue = get_ns() - t_prologue;
/* ── Main Loop: 硬件完全流水线 (Overlapped Execution) ──── */
/* ═══════════════════════════════════════════════════════════════
* MAIN LOOP: Fully-pipelined — pre-fire DMA load at loop tail
*
* At iteration g:
* IP is computing group (g-1) on prev_bank
* Ch0 loaded group g to cur_bank (pre-fired in iteration g-1)
*
* Pipeline:
* Ch0: | load g+1 | | load g+2 |
* Ch1: | store g-1 | | store g |
* IP : | compute g | | compute g+1 |
* ═══════════════════════════════════════════════════════════════ */
t_mainloop = get_ns();
// 在 g 循环中:
// IP 正在计算 prev_bank (g-1)
// DMA_CH0 正在加载 cur_bank (g)
// DMA_CH1 正在写回 prev_prev_bank (g-2)
bank = 1; // cur_bank for iteration g=1; prev_bank = bank ^ 1
for (g = 1; g < MATMUL_GROUP_NUM; g++) {
int cur_bank = g % 2;
int prev_bank = (g - 1) % 2;
int cur_bank = bank;
int prev_bank = bank ^ 1;
// 1. 发起加载下一组数据的 DMA 传输 (Channel 0: Memory -> IP)
dma_start_transfer(0, EXTRAM_PHYS_AB(g), phys_bank_AB[cur_bank], 128, 10);
// 1. Wait for previous IP computation (group g-1 on prev_bank)
while (!(*mat_status & STATUS_DONE)) {}
*mat_status = STATUS_DONE;
// 2. 等待上一组在 IP 中的计算完成
wait_matmul_done();
// 3. 确保上一次的结果写回 (Channel 1) 已经空闲
// 2. Ensure previous DMA Ch1 store is done (group g-2)
if (g > 1) {
wait_dma_done(1);
while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
ch1->STATUS = STATUS_DONE_BIT;
}
// 4. 发起写回刚才计算完成的结果 (Channel 1: IP -> Memory)
dma_start_transfer(1, phys_bank_C[prev_bank], EXTRAM_PHYS_C(g - 1), 192, 20);
// 3. Start DMA Ch1 store: group (g-1) result → ExtRAM
ch1->SRC_ADDR = phys_bank_C[prev_bank];
ch1->DST_ADDR = EXTRAM_PHYS_C(g - 1);
ch1->LENGTH = 192;
ch1->TAG = 20;
ch1->CTRL = DMA_CTRL_VAL;
// 5. 确保当前要计算的输入数据 (Channel 0) 已经加载完毕
wait_dma_done(0);
// 4. Wait for current DMA Ch0 load (group g → cur_bank, pre-fired in iteration g-1)
while (!(ch0->STATUS & STATUS_DONE_BIT)) {}
ch0->STATUS = STATUS_DONE_BIT;
// 6. 立即启动当前组在 IP 中的计算
REG_WR(MATMUL_CTRL, ctrl_start[cur_bank]);
// 5. Start IP computation for current group on cur_bank
*mat_ctrl = ctrl_start[cur_bank];
// ★ 6. PRE-FIRE: DMA Ch0 load next group (g+1) → next_bank
// This runs CONCURRENTLY with IP computation started in step 5!
if (g < MATMUL_GROUP_NUM - 1) {
int next_bank = bank ^ 1;
ch0->SRC_ADDR = EXTRAM_PHYS_AB(g + 1);
ch0->DST_ADDR = phys_bank_AB[next_bank];
ch0->LENGTH = 128;
ch0->TAG = 10;
ch0->CTRL = DMA_CTRL_VAL;
}
// Toggle bank for next iteration
bank ^= 1;
}
t_mainloop = get_ns() - t_mainloop;
/* ── Epilogue: 收尾最后一组 ───────────────────────────── */
/* ═══════════════════════════════════════════════════════════════
* EPILOGUE: Flush the final group
* ═══════════════════════════════════════════════════════════════ */
t_epilogue = get_ns();
wait_matmul_done(); // 等待最后一次计算完成
wait_dma_done(1); // 确保之前的 DMA CH1 空闲
// DMA CH1 将最后一组结果写回
dma_start_transfer(1, phys_bank_C[(MATMUL_GROUP_NUM - 1) % 2], EXTRAM_PHYS_C(MATMUL_GROUP_NUM - 1), 192, 20);
wait_dma_done(1);
// Wait for last IP computation to finish
while (!(*mat_status & STATUS_DONE)) {}
*mat_status = STATUS_DONE;
// Wait for last DMA Ch1 store (group MATMUL_GROUP_NUM-2) and then store final group
while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
ch1->STATUS = STATUS_DONE_BIT;
ch1->SRC_ADDR = phys_bank_C[(MATMUL_GROUP_NUM - 1) % 2];
ch1->DST_ADDR = EXTRAM_PHYS_C(MATMUL_GROUP_NUM - 1);
ch1->LENGTH = 192;
ch1->TAG = 20;
ch1->CTRL = DMA_CTRL_VAL;
while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
ch1->STATUS = STATUS_DONE_BIT;
t_epilogue = get_ns() - t_epilogue;
/* ── Read hardware CRC32 result ──────────────────────────── */
crc = REG_RD(MATMUL_CRC);
crc = *mat_crc;
/* ── Final markers ────────────────────────────────────────── */
printf("MATMUL_CRC32=%08lx\n", (unsigned long)crc);
@@ -166,4 +223,4 @@ int main(void)
printf("MATMUL_DONE\n");
return 0;
}
}