optimize
This commit is contained in:
421
rtl/soc_top.v
421
rtl/soc_top.v
@@ -44,39 +44,38 @@ module soc_top #(parameter SIMULATION=1'b0)
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input clk,
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input reset,
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//图像输出信号
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output [2:0] video_red, //红色像素，3位
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output [2:0] video_green, //绿色像素，3位
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output [1:0] video_blue, //蓝色像素，2位
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output video_hsync, //行同步（水平同步）信号
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output video_vsync, //场同步（垂直同步）信号
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output video_clk, //像素时钟输出
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output video_de, //行数据有效信号，用于区分消隐区
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output [2:0] video_red,
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output [2:0] video_green,
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output [1:0] video_blue,
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output video_hsync,
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output video_vsync,
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output video_clk,
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output video_de,
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input [3:0] touch_btn, //BTN1~BTN4，按钮开关，按下时为1
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input [31:0] dip_sw, //32位拨码开关，拨到“ON”时为1
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output [15:0] leds, //16位LED，输出时1点亮
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output [7:0] dpy0, //数码管低位信号，包括小数点，输出1点亮
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output [7:0] dpy1, //数码管高位信号，包括小数点，输出1点亮
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input [3:0] touch_btn,
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input [31:0] dip_sw,
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output [15:0] leds,
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output [7:0] dpy0,
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output [7:0] dpy1,
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//BaseRAM信号
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inout [31:0] base_ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享
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output [19:0] base_ram_addr, //BaseRAM地址
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output [ 3:0] base_ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0
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output base_ram_ce_n, //BaseRAM片选，低有效
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output base_ram_oe_n, //BaseRAM读使能，低有效
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output base_ram_we_n, //BaseRAM写使能，低有效
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//ExtRAM信号
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inout [31:0] ext_ram_data, //ExtRAM数据
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output [19:0] ext_ram_addr, //ExtRAM地址
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output [ 3:0] ext_ram_be_n, //ExtRAM字节使能，低有效。如果不使用字节使能，请保持为0
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output ext_ram_ce_n, //ExtRAM片选，低有效
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output ext_ram_oe_n, //ExtRAM读使能，低有效
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output ext_ram_we_n, //ExtRAM写使能，低有效
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// BaseRAM signals
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inout [31:0] base_ram_data,
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output [19:0] base_ram_addr,
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output [ 3:0] base_ram_be_n,
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output base_ram_ce_n,
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output base_ram_oe_n,
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output base_ram_we_n,
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// ExtRAM signals
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inout [31:0] ext_ram_data,
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output [19:0] ext_ram_addr,
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output [ 3:0] ext_ram_be_n,
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output ext_ram_ce_n,
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output ext_ram_oe_n,
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output ext_ram_we_n,
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//------uart-------
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inout UART_RX, //串口RX接收
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inout UART_TX //串口TX发送
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inout UART_RX,
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inout UART_TX
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);
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wire cpu_clk;
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@@ -360,44 +359,6 @@ wire [3 :0] dma_m_bid ;
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wire [1 :0] dma_m_bresp ;
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wire dma_m_bvalid ;
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wire dma_m_bready ;
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wire [3 :0] cdma_m_arid ;
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wire [31:0] cdma_m_araddr ;
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wire [7 :0] cdma_m_arlen ;
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wire [2 :0] cdma_m_arsize ;
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wire [1 :0] cdma_m_arburst;
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wire cdma_m_arlock ;
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wire [3 :0] cdma_m_arcache;
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wire [2 :0] cdma_m_arprot ;
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wire cdma_m_arvalid;
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wire cdma_m_arready = 1'b0;
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wire [3 :0] cdma_m_rid = 4'd0;
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wire [31:0] cdma_m_rdata = 32'd0;
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wire [1 :0] cdma_m_rresp = 2'd0;
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wire cdma_m_rlast = 1'b0;
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wire cdma_m_rvalid = 1'b0;
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wire cdma_m_rready ;
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wire [3 :0] cdma_m_awid ;
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wire [31:0] cdma_m_awaddr ;
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wire [7 :0] cdma_m_awlen ;
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wire [2 :0] cdma_m_awsize ;
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wire [1 :0] cdma_m_awburst;
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wire cdma_m_awlock ;
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wire [3 :0] cdma_m_awcache;
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wire [2 :0] cdma_m_awprot ;
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wire cdma_m_awvalid;
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wire cdma_m_awready = 1'b0;
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wire [3 :0] cdma_m_wid ;
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wire [31:0] cdma_m_wdata ;
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wire [3 :0] cdma_m_wstrb ;
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wire cdma_m_wlast ;
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wire cdma_m_wvalid ;
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wire cdma_m_wready = 1'b0;
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wire [3 :0] cdma_m_bid = 4'd0;
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wire [1 :0] cdma_m_bresp = 2'd0;
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wire cdma_m_bvalid = 1'b0;
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wire cdma_m_bready ;
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wire [4 :0] dma_s_arid ;
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wire [31:0] dma_s_araddr ;
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wire [7 :0] dma_s_arlen ;
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@@ -433,7 +394,7 @@ wire [4 :0] dma_s_bid ;
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wire [1 :0] dma_s_bresp ;
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wire dma_s_bvalid ;
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wire dma_s_bready ;
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wire dma_finish ;
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wire dma_finish = 1'b0;
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// reserved
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wire [4 :0] axiOut_1_arid ;
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@@ -641,7 +602,6 @@ wire axiOut_7_bready ;
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wire confreg_int;
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wire matmul_intr;
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wire mlkem_intr;
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AxiCrossbar_2x8 u_AxiCrossbar_2x8 (
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.clk ( sys_clk ),
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@@ -1073,8 +1033,8 @@ AxiCrossbar_2x8 u_AxiCrossbar_2x8 (
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core_top u_cpu(
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.intrpt ({4'd0, mlkem_intr, matmul_intr, dma_finish, confreg_int}), //high active
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// intrpt[3]=mlkem, intrpt[2]=matmul, intrpt[1]=dma, intrpt[0]=confreg
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.intrpt ({4'd0, 1'b0, matmul_intr, dma_finish, confreg_int}), //high active
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// intrpt[2]=matmul, intrpt[1]=dma, intrpt[0]=confreg
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.aclk (cpu_clk ),
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.aresetn (cpu_resetn ), //low active
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@@ -1349,13 +1309,12 @@ axi_uart_controller u_axi_uart_controller
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confreg #(
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.SIMULATION(SIMULATION)
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) u_confreg (
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// 时钟与复位
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.aclk (sys_clk), // AXI总线时钟
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.aresetn (sys_resetn), // AXI总线复位
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.cpu_clk (cpu_clk), // CPU时钟
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.cpu_resetn (cpu_resetn), // CPU复位
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.aclk (sys_clk),
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.aresetn (sys_resetn),
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.cpu_clk (cpu_clk),
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.cpu_resetn (cpu_resetn),
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// AXI写地址通道
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// AXI Write Address
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.s_awid (confreg_awid),
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.s_awaddr (confreg_awaddr),
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.s_awlen (confreg_awlen),
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@@ -1367,7 +1326,7 @@ confreg #(
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.s_awvalid (confreg_awvalid),
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.s_awready (confreg_awready),
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// AXI写数据通道
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// AXI Write Data
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.s_wid (confreg_wid),
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.s_wdata (confreg_wdata),
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.s_wstrb (confreg_wstrb),
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@@ -1375,13 +1334,13 @@ confreg #(
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.s_wvalid (confreg_wvalid),
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.s_wready (confreg_wready),
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// AXI写响应通道
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// AXI Write Response
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.s_bid (confreg_bid),
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.s_bresp (confreg_bresp),
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.s_bvalid (confreg_bvalid),
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.s_bready (confreg_bready),
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// AXI读地址通道
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// AXI Read Address
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.s_arid (confreg_arid),
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.s_araddr (confreg_araddr),
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.s_arlen (confreg_arlen),
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@@ -1393,7 +1352,7 @@ confreg #(
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.s_arvalid (confreg_arvalid),
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.s_arready (confreg_arready),
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// AXI读数据通道
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// AXI Read Data
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.s_rid (confreg_rid),
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.s_rdata (confreg_rdata),
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.s_rresp (confreg_rresp),
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@@ -1401,19 +1360,17 @@ confreg #(
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.s_rvalid (confreg_rvalid),
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.s_rready (confreg_rready),
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// IO外设接口 (与soc_top顶层引脚相连)
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.led (leds), // 顶层引脚名称为
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.dpy0 (dpy0), // 低位数码管
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.dpy1 (dpy1), // 高位数码管
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.switch (dip_sw), // 拨码开关，顶层名称为 dip_sw
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.touch_btn (touch_btn), // 触摸按钮
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// IO
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.led (leds),
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.dpy0 (dpy0),
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.dpy1 (dpy1),
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.switch (dip_sw),
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.touch_btn (touch_btn),
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// 中断与状态信号
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.uart0_int (uart0_int), // UART0中断
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.fft_finish (fft_finish), // FFT完成信号
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.confreg_int(confreg_int) // 输出中断给CPU
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.uart0_int (uart0_int),
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.fft_finish (fft_finish),
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.confreg_int(confreg_int)
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);
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axi_dvi u_axi_dvi (
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.s_awvalid ( dvi_awvalid ),
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.s_awaddr ( dvi_awaddr ),
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@@ -1462,69 +1419,20 @@ axi_dvi u_axi_dvi (
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.video_blue ( video_blue )
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);
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// slave 6 - ML-KEM accelerator (0x1f400000, virtual 0xbf400000)
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// Bus runs at sys_clk; the core is internally clocked at sys_clk/2 (25 MHz).
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mlkem_axi_slave u_mlkem_axi_slave (
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.clk (sys_clk),
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.resetn (sys_resetn),
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.s_axi_awid (fft_awid ),
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.s_axi_awaddr (fft_awaddr ),
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.s_axi_awlen (fft_awlen ),
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.s_axi_awsize (fft_awsize ),
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.s_axi_awburst (fft_awburst),
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.s_axi_awlock (fft_awlock ),
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.s_axi_awcache (fft_awcache),
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.s_axi_awprot (fft_awprot ),
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.s_axi_awvalid (fft_awvalid),
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.s_axi_awready (fft_awready),
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.s_axi_wid (fft_wid ),
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.s_axi_wdata (fft_wdata ),
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.s_axi_wstrb (fft_wstrb ),
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.s_axi_wlast (fft_wlast ),
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.s_axi_wvalid (fft_wvalid),
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.s_axi_wready (fft_wready),
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.s_axi_bid (fft_bid ),
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.s_axi_bresp (fft_bresp ),
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.s_axi_bvalid (fft_bvalid),
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.s_axi_bready (fft_bready),
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.s_axi_arid (fft_arid ),
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.s_axi_araddr (fft_araddr ),
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.s_axi_arlen (fft_arlen ),
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.s_axi_arsize (fft_arsize ),
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.s_axi_arburst (fft_arburst),
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.s_axi_arlock (fft_arlock ),
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.s_axi_arcache (fft_arcache),
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.s_axi_arprot (fft_arprot ),
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.s_axi_arvalid (fft_arvalid),
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.s_axi_arready (fft_arready),
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.s_axi_rid (fft_rid ),
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.s_axi_rdata (fft_rdata ),
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.s_axi_rresp (fft_rresp ),
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.s_axi_rlast (fft_rlast ),
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.s_axi_rvalid (fft_rvalid),
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.s_axi_rready (fft_rready),
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.intr (mlkem_intr)
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);
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// slave 6 reserved (mlkem removed)
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assign fft_arready = 1'b1;
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assign fft_rid = 5'b0;
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assign fft_rdata = 32'b0;
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assign fft_rresp = 2'b0;
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assign fft_rlast = 1'b0;
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assign fft_rvalid = 1'b0;
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assign fft_awready = 1'b1;
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assign fft_wready = 1'b1;
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assign fft_bid = 5'b0;
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assign fft_bresp = 2'b0;
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assign fft_bvalid = 1'b0;
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//slave 7 - matmul accelerator
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wire dma_ep_wr_valid;
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wire [3:0] dma_ep_wr_id;
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wire [3:0] dma_ep_wr_bank;
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wire [7:0] dma_ep_wr_word_addr;
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wire [31:0] dma_ep_wr_data;
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wire dma_ep_wr_ready;
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wire dma_ep_rd_valid;
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wire [3:0] dma_ep_rd_id;
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wire [3:0] dma_ep_rd_bank;
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wire [7:0] dma_ep_rd_word_addr;
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wire [31:0] dma_ep_rd_data;
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wire dma_ep_rd_ready;
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matmul_axi_slave u_matmul_axi_slave (
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.clk (sys_clk),
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.resetn (sys_resetn),
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@@ -1570,19 +1478,6 @@ matmul_axi_slave u_matmul_axi_slave (
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.s_axi_rvalid (axiOut_7_rvalid),
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.s_axi_rready (axiOut_7_rready),
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.ep_wr_valid (dma_ep_wr_valid),
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.ep_wr_id (dma_ep_wr_id),
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.ep_wr_bank (dma_ep_wr_bank),
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.ep_wr_word_addr(dma_ep_wr_word_addr),
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.ep_wr_data (dma_ep_wr_data),
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.ep_wr_ready (dma_ep_wr_ready),
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.ep_rd_valid (dma_ep_rd_valid),
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.ep_rd_id (dma_ep_rd_id),
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.ep_rd_bank (dma_ep_rd_bank),
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.ep_rd_word_addr(dma_ep_rd_word_addr),
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.ep_rd_data (dma_ep_rd_data),
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.ep_rd_ready (dma_ep_rd_ready),
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.m_axi_awid (dma_m_awid),
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.m_axi_awaddr (dma_m_awaddr),
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.m_axi_awlen (dma_m_awlen),
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@@ -1622,186 +1517,16 @@ matmul_axi_slave u_matmul_axi_slave (
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.intr (matmul_intr)
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);
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wire [31:0] cdma_s_awaddr;
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wire [2:0] cdma_s_awprot;
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wire cdma_s_awvalid;
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wire cdma_s_awready;
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wire [31:0] cdma_s_wdata;
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wire [3:0] cdma_s_wstrb;
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wire cdma_s_wvalid;
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wire cdma_s_wready;
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wire [1:0] cdma_s_bresp;
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wire cdma_s_bvalid;
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wire cdma_s_bready;
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wire [31:0] cdma_s_araddr;
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wire [2:0] cdma_s_arprot;
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wire cdma_s_arvalid;
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wire cdma_s_arready;
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wire [31:0] cdma_s_rdata;
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wire [1:0] cdma_s_rresp;
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wire cdma_s_rvalid;
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wire cdma_s_rready;
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axi_axil_adapter #(
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.ADDR_WIDTH(32),
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.AXI_DATA_WIDTH(32),
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.AXI_ID_WIDTH(5),
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.AXIL_DATA_WIDTH(32),
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.CONVERT_BURST(1),
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.CONVERT_NARROW_BURST(0)
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)
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u_axi_axil_adapter(
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.clk(sys_clk),
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.rst(~sys_resetn),
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.s_axi_awid(dma_s_awid),
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.s_axi_awaddr(dma_s_awaddr),
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.s_axi_awlen(dma_s_awlen),
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.s_axi_awsize(dma_s_awsize),
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.s_axi_awburst(dma_s_awburst),
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.s_axi_awlock(dma_s_awlock),
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.s_axi_awcache(dma_s_awcache),
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.s_axi_awprot(dma_s_awprot),
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.s_axi_awvalid(dma_s_awvalid),
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.s_axi_awready(dma_s_awready),
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.s_axi_wdata(dma_s_wdata),
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.s_axi_wstrb(dma_s_wstrb),
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.s_axi_wlast(dma_s_wlast),
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.s_axi_wvalid(dma_s_wvalid),
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.s_axi_wready(dma_s_wready),
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.s_axi_bid(dma_s_bid),
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.s_axi_bresp(dma_s_bresp),
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.s_axi_bvalid(dma_s_bvalid),
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.s_axi_bready(dma_s_bready),
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.s_axi_arid(dma_s_arid),
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.s_axi_araddr(dma_s_araddr),
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.s_axi_arlen(dma_s_arlen),
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.s_axi_arsize(dma_s_arsize),
|
||||
.s_axi_arburst(dma_s_arburst),
|
||||
.s_axi_arlock(dma_s_arlock),
|
||||
.s_axi_arcache(dma_s_arcache),
|
||||
.s_axi_arprot(dma_s_arprot),
|
||||
.s_axi_arvalid(dma_s_arvalid),
|
||||
.s_axi_arready(dma_s_arready),
|
||||
.s_axi_rid(dma_s_rid),
|
||||
.s_axi_rdata(dma_s_rdata),
|
||||
.s_axi_rresp(dma_s_rresp),
|
||||
.s_axi_rlast(dma_s_rlast),
|
||||
.s_axi_rvalid(dma_s_rvalid),
|
||||
.s_axi_rready(dma_s_rready),
|
||||
|
||||
.m_axil_awaddr(cdma_s_awaddr),
|
||||
.m_axil_awprot(cdma_s_awprot),
|
||||
.m_axil_awvalid(cdma_s_awvalid),
|
||||
.m_axil_awready(cdma_s_awready),
|
||||
.m_axil_wdata(cdma_s_wdata),
|
||||
.m_axil_wstrb(cdma_s_wstrb),
|
||||
.m_axil_wvalid(cdma_s_wvalid),
|
||||
.m_axil_wready(cdma_s_wready),
|
||||
.m_axil_bresp(cdma_s_bresp),
|
||||
.m_axil_bvalid(cdma_s_bvalid),
|
||||
.m_axil_bready(cdma_s_bready),
|
||||
.m_axil_araddr(cdma_s_araddr),
|
||||
.m_axil_arprot(cdma_s_arprot),
|
||||
.m_axil_arvalid(cdma_s_arvalid),
|
||||
.m_axil_arready(cdma_s_arready),
|
||||
.m_axil_rdata(cdma_s_rdata),
|
||||
.m_axil_rresp(cdma_s_rresp),
|
||||
.m_axil_rvalid(cdma_s_rvalid),
|
||||
.m_axil_rready(cdma_s_rready)
|
||||
);
|
||||
|
||||
// 8 通道 DMA
|
||||
snix_axil_cdma_mux #(
|
||||
.ADDR_WIDTH (32),
|
||||
.DATA_WIDTH (32), // 适配你的 32-bit 总线
|
||||
.AXIL_ADDR_WIDTH (32),
|
||||
.AXIL_DATA_WIDTH (32),
|
||||
.ID_WIDTH (4), // 匹配 Crossbar 的 Master ID 宽度
|
||||
.USER_WIDTH (1),
|
||||
.PORTS (4), // 8 个通道
|
||||
.FIFO_DEPTH (64)
|
||||
) u_snix_axil_cdma_mux_8ch (
|
||||
.clk (sys_clk),
|
||||
.rst_n (sys_resetn), // 低电平复位
|
||||
|
||||
// AXI-Lite 从机接口 (接 CPU 发来的配置请求)
|
||||
.s_axil_awaddr (cdma_s_awaddr),
|
||||
.s_axil_awvalid (cdma_s_awvalid),
|
||||
.s_axil_awready (cdma_s_awready),
|
||||
.s_axil_wdata (cdma_s_wdata),
|
||||
.s_axil_wstrb (cdma_s_wstrb),
|
||||
.s_axil_wvalid (cdma_s_wvalid),
|
||||
.s_axil_wready (cdma_s_wready),
|
||||
.s_axil_bresp (cdma_s_bresp),
|
||||
.s_axil_bvalid (cdma_s_bvalid),
|
||||
.s_axil_bready (cdma_s_bready),
|
||||
.s_axil_araddr (cdma_s_araddr),
|
||||
.s_axil_arvalid (cdma_s_arvalid),
|
||||
.s_axil_arready (cdma_s_arready),
|
||||
.s_axil_rdata (cdma_s_rdata),
|
||||
.s_axil_rresp (cdma_s_rresp),
|
||||
.s_axil_rvalid (cdma_s_rvalid),
|
||||
.s_axil_rready (cdma_s_rready),
|
||||
|
||||
// AXI4 主机接口 (接 Crossbar 去搬运数据)
|
||||
.mm2mm_awid (cdma_m_awid),
|
||||
.mm2mm_awaddr (cdma_m_awaddr),
|
||||
.mm2mm_awlen (cdma_m_awlen),
|
||||
.mm2mm_awsize (cdma_m_awsize),
|
||||
.mm2mm_awburst (cdma_m_awburst),
|
||||
.mm2mm_awlock (cdma_m_awlock),
|
||||
.mm2mm_awcache (cdma_m_awcache),
|
||||
.mm2mm_awprot (cdma_m_awprot),
|
||||
.mm2mm_awqos (), // 悬空即可
|
||||
.mm2mm_awuser (), // 悬空即可
|
||||
.mm2mm_awvalid (cdma_m_awvalid),
|
||||
.mm2mm_awready (cdma_m_awready),
|
||||
.mm2mm_wdata (cdma_m_wdata),
|
||||
.mm2mm_wstrb (cdma_m_wstrb),
|
||||
.mm2mm_wlast (cdma_m_wlast),
|
||||
.mm2mm_wuser (), // 悬空即可
|
||||
.mm2mm_wvalid (cdma_m_wvalid),
|
||||
.mm2mm_wready (cdma_m_wready),
|
||||
.mm2mm_bid (cdma_m_bid),
|
||||
.mm2mm_bresp (cdma_m_bresp),
|
||||
.mm2mm_buser (1'b0),
|
||||
.mm2mm_bvalid (cdma_m_bvalid),
|
||||
.mm2mm_bready (cdma_m_bready),
|
||||
.mm2mm_arid (cdma_m_arid),
|
||||
.mm2mm_araddr (cdma_m_araddr),
|
||||
.mm2mm_arlen (cdma_m_arlen),
|
||||
.mm2mm_arsize (cdma_m_arsize),
|
||||
.mm2mm_arburst (cdma_m_arburst),
|
||||
.mm2mm_arlock (cdma_m_arlock),
|
||||
.mm2mm_arcache (cdma_m_arcache),
|
||||
.mm2mm_arprot (cdma_m_arprot),
|
||||
.mm2mm_arqos (), // 悬空即可
|
||||
.mm2mm_aruser (), // 悬空即可
|
||||
.mm2mm_arvalid (cdma_m_arvalid),
|
||||
.mm2mm_arready (cdma_m_arready),
|
||||
.mm2mm_rid (cdma_m_rid),
|
||||
.mm2mm_rdata (cdma_m_rdata),
|
||||
.mm2mm_rresp (cdma_m_rresp),
|
||||
.mm2mm_rlast (cdma_m_rlast),
|
||||
.mm2mm_ruser (1'b0),
|
||||
.mm2mm_rvalid (cdma_m_rvalid),
|
||||
.mm2mm_rready (cdma_m_rready),
|
||||
|
||||
.ep_wr_valid (dma_ep_wr_valid),
|
||||
.ep_wr_id (dma_ep_wr_id),
|
||||
.ep_wr_bank (dma_ep_wr_bank),
|
||||
.ep_wr_word_addr (dma_ep_wr_word_addr),
|
||||
.ep_wr_data (dma_ep_wr_data),
|
||||
.ep_wr_ready (dma_ep_wr_ready),
|
||||
.ep_rd_valid (dma_ep_rd_valid),
|
||||
.ep_rd_id (dma_ep_rd_id),
|
||||
.ep_rd_bank (dma_ep_rd_bank),
|
||||
.ep_rd_word_addr (dma_ep_rd_word_addr),
|
||||
.ep_rd_data (dma_ep_rd_data),
|
||||
.ep_rd_ready (dma_ep_rd_ready),
|
||||
|
||||
// 全局中断输出
|
||||
.dma_finish (dma_finish)
|
||||
);
|
||||
|
||||
//slave 5 reserved (cdma adapter removed)
|
||||
assign dma_s_arready = 1'b1;
|
||||
assign dma_s_rid = 5'b0;
|
||||
assign dma_s_rdata = 32'b0;
|
||||
assign dma_s_rresp = 2'b0;
|
||||
assign dma_s_rlast = 1'b0;
|
||||
assign dma_s_rvalid = 1'b0;
|
||||
assign dma_s_awready = 1'b1;
|
||||
assign dma_s_wready = 1'b1;
|
||||
assign dma_s_bid = 5'b0;
|
||||
assign dma_s_bresp = 2'b0;
|
||||
assign dma_s_bvalid = 1'b0;
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user