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FallenSigh
2026-07-13 07:10:30 +08:00
parent 886ae8ad3f
commit 7c60da78cb
4 changed files with 286 additions and 579 deletions
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31
rtl/ip/ram_wrap/axi_wrap_ram_sp_external.v
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@@ -75,21 +75,17 @@ module axi_wrap_ram_sp_external (
output axi_bvalid ,
input axi_bready ,
//BaseRAM信号
inout [31:0] base_ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享
output [19:0] base_ram_addr, //BaseRAM地址
output [ 3:0] base_ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0
output base_ram_ce_n, //BaseRAM片选，低有效
output base_ram_oe_n, //BaseRAM读使能，低有效
output base_ram_we_n, //BaseRAM写使能，低有效
//BaseRAM\Uffffffff\Uffffffff\Uffffffff inout [31:0] base_ram_data, //BaseRAM\Uffffffff\Uffffffff\u0763\Uffffffff\Uffffffff\Uffffffff\u03bb\UffffffffCPLD\Uffffffff\Uffffffff\Uffffffff\u06bf\Uffffffff\Uffffffff\Uffffffff\Uffffffff output [19:0] base_ram_addr, //BaseRAM\Uffffffff\Uffffffff\Uffffffff
output [ 3:0] base_ram_be_n, //BaseRAM\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff0
output base_ram_ce_n, //BaseRAM\u01ac\u0461\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff
output base_ram_oe_n, //BaseRAM\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff
output base_ram_we_n, //BaseRAM\u0434\u02b9\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff
//ExtRAM信号
inout [31:0] ext_ram_data, //ExtRAM数据
output [19:0] ext_ram_addr, //ExtRAM地址
output [ 3:0] ext_ram_be_n, //ExtRAM字节使能，低有效。如果不使用字节使能，请保持为0
output ext_ram_ce_n, //ExtRAM片选，低有效
output ext_ram_oe_n, //ExtRAM读使能，低有效
output ext_ram_we_n //ExtRAM写使能，低有效
//ExtRAM\Uffffffff\Uffffffff\Uffffffff inout [31:0] ext_ram_data, //ExtRAM\Uffffffff\Uffffffff\Uffffffff output [19:0] ext_ram_addr, //ExtRAM\Uffffffff\Uffffffff\Uffffffff
output [ 3:0] ext_ram_be_n, //ExtRAM\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff0
output ext_ram_ce_n, //ExtRAM\u01ac\u0461\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff
output ext_ram_oe_n, //ExtRAM\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff
output ext_ram_we_n //ExtRAM\u0434\u02b9\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff
);
@@ -139,6 +135,7 @@ wire ram_bready ;
wire [31:0] soc_sram_addr;
wire soc_sram_cs;
wire soc_sram_we;
wire soc_sram_bank;
wire [3:0] soc_sram_be;
wire [31:0] soc_sram_wdata;
wire [31:0] soc_sram_rdata;
@@ -188,7 +185,8 @@ assign ram_bready = axi_bready ;
axi2sram_sp_external #(
.AXI_ID_WIDTH ( 5 ),
.AXI_ADDR_WIDTH ( 32 ),
.AXI_DATA_WIDTH ( 32 ))
.AXI_DATA_WIDTH ( 32 ),
.FAST_READ_BURST( 1 ))
u_axi_sram_sp (
.clk ( aclk ),
.resetn ( aresetn ),
@@ -232,12 +230,13 @@ axi2sram_sp_external #(
.req_o ( soc_sram_cs ),
.we_o ( soc_sram_we ),
.addr_o ( soc_sram_addr ),
.bank_o ( soc_sram_bank ),
.be_o ( soc_sram_be ),
.data_o ( soc_sram_wdata ),
.data_i ( soc_sram_rdata )
);
wire choose_sram = soc_sram_addr[22];//1:ExtRAM 0:BaseRAM
wire choose_sram = soc_sram_bank;//1:ExtRAM 0:BaseRAM
wire [3:0] be_out = soc_sram_we ? soc_sram_be : 4'b1111;
assign base_ram_addr = soc_sram_addr[21:2];