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FallenSigh
2026-07-13 07:10:30 +08:00
parent 886ae8ad3f
commit 7c60da78cb
4 changed files with 286 additions and 579 deletions
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268
rtl/ip/matmul/matmul_axi_slave.v
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@@ -1,7 +1,5 @@
// ═══════════════════════════════════════════════════════
// 3-stage pipelined multiplier (LUT-based, no DSP)
// latency=3, throughput=1 result/cycle
// ═══════════════════════════════════════════════════════
// 3-stage pipelined multiplier (LUT-based, no DSP)
// latency=3, throughput=1 result/cycle
(* use_dsp = "no", use_dsp48 = "no", syn_multstyle = "logic" *)
module pipelined_mult_32x32 (
input clk,
@@ -43,9 +41,7 @@ module pipelined_mult_32x32 (
endmodule
// ═══════════════════════════════════════════════════════
// 矩阵乘法器顶层模块 (AXI Burst Slave + Ping-Pong + Stream CRC32)
// ═══════════════════════════════════════════════════════
// AXI Burst Slave + Ping-Pong + Stream CRC32
module matmul_axi_slave (
input clk,
input resetn,
@@ -96,21 +92,6 @@ module matmul_axi_slave (
output reg s_axi_rvalid,
input s_axi_rready,
// CDMA local endpoint port
input ep_wr_valid,
input [3:0] ep_wr_id,
input [3:0] ep_wr_bank,
input [7:0] ep_wr_word_addr,
input [31:0] ep_wr_data,
output ep_wr_ready,
input ep_rd_valid,
input [3:0] ep_rd_id,
input [3:0] ep_rd_bank,
input [7:0] ep_rd_word_addr,
output reg [31:0] ep_rd_data,
output ep_rd_ready,
// AXI master port for autonomous matrix stream load/store
output reg [3:0] m_axi_awid,
output reg [31:0] m_axi_awaddr,
@@ -157,7 +138,7 @@ module matmul_axi_slave (
);
// ==========================================
// 内存地址映射 (Memory Map)
// Memory Map
// ==========================================
localparam ADDR_CTRL = 12'h000;
localparam ADDR_STATUS = 12'h004;
@@ -177,7 +158,7 @@ module matmul_axi_slave (
localparam ADDR_B1_C = 12'h380;
// ==========================================
// 寄存器与数据缓冲
// Registers and data buffers
// ==========================================
reg req_0, req_1;
reg busy;
@@ -258,31 +239,6 @@ module matmul_axi_slave (
end
endfunction
assign ep_wr_ready = 1'b1;
assign ep_rd_ready = 1'b1;
wire [3:0] ep_wr_lo_idx = ep_wr_word_addr[3:0];
wire [3:0] ep_wr_hi_idx = ep_wr_word_addr[3:0];
wire [3:0] ep_rd_elem = c_elem_from_word(ep_rd_word_addr[5:0]);
wire [1:0] ep_rd_part = c_part_from_word(ep_rd_word_addr[5:0]);
wire [65:0] ep_rd_c0 = b0_c[ep_rd_elem];
wire [65:0] ep_rd_c1 = b1_c[ep_rd_elem];
always @(*) begin
ep_rd_data = 32'b0;
if (ep_rd_word_addr < 8'd48) begin
if (ep_rd_bank[0] == 1'b0) begin
if (ep_rd_part == 2'd0) ep_rd_data = ep_rd_c0[31:0];
else if (ep_rd_part == 2'd1) ep_rd_data = ep_rd_c0[63:32];
else ep_rd_data = {30'b0, ep_rd_c0[65:64]};
end else begin
if (ep_rd_part == 2'd0) ep_rd_data = ep_rd_c1[31:0];
else if (ep_rd_part == 2'd1) ep_rd_data = ep_rd_c1[63:32];
else ep_rd_data = {30'b0, ep_rd_c1[65:64]};
end
end
end
function [31:0] apply_wstrb;
input [31:0] old_value;
input [31:0] new_value;
@@ -298,16 +254,24 @@ module matmul_axi_slave (
// ==========================================
// CRC32 Engine (IEEE 802.3, polynomial 0xEDB88320)
//
// AXI-stream: single-cycle crc32_update_word (4 LUT lookup depth, ok for
// AXI timing—the bus runs at or below internal compute rate).
// DMA-calc: 2-stage pipelined word engine (2 bytes/stage) + 6-cycle
// serial FSM for 66-bit C-elements, with 16-deep FIFO to absorb the
// compute pipeline burst. Critical path: 2 table lookups + 1 XOR per
// stage vs 12 table lookups in the original single-cycle design.
// ==========================================
reg [31:0] crc32_table [0:255];
reg [31:0] crc_reg;
wire [31:0] crc_stream_data = ep_rd_valid ? ep_rd_data : s_axi_rdata;
// ---- AXI-stream CRC (single-cycle) ----------------------------------
wire [31:0] crc_stream_data = s_axi_rdata;
wire crc_axi_valid = (r_state == R_DATA) && s_axi_rvalid && s_axi_rready &&
((r_offset >= ADDR_B0_C && r_offset < (ADDR_B0_C + 12'h0C0)) ||
(r_offset >= ADDR_B1_C && r_offset < (ADDR_B1_C + 12'h0C0)));
wire crc_ep_valid = ep_rd_valid && ep_rd_ready && (ep_rd_word_addr < 8'd48);
wire crc_stream_valid = crc_axi_valid || crc_ep_valid;
wire crc_stream_valid = crc_axi_valid;
wire [31:0] crc_next = crc32_update_word(crc_reg, crc_stream_data);
function [31:0] crc32_update_word;
input [31:0] crc_in;
@@ -323,19 +287,23 @@ module matmul_axi_slave (
end
endfunction
function [31:0] crc32_update_c66;
input [31:0] crc_in;
input [65:0] c_in;
reg [31:0] crc_mid0;
reg [31:0] crc_mid1;
begin
crc_mid0 = crc32_update_word(crc_in, c_in[31:0]);
crc_mid1 = crc32_update_word(crc_mid0, c_in[63:32]);
crc32_update_c66 = crc32_update_word(crc_mid1, {30'b0, c_in[65:64]});
end
endfunction
// ---- DMA-calc 3-stage shift register pipeline -----------------------
// Stage 0: capture acc_result, compute word0 CRC.
// Stage 1: shift, compute word1 CRC.
// Final: crc_reg updated when stage 1 valid (word2 CRC).
// Latency 3 cycles; compute FSM inserts issue gaps so result spacing
// is ≥3 cycles, ensuring crc_reg is committed before the next capture.
reg crc_c66_s0_valid, crc_c66_s1_valid;
reg [31:0] crc_c66_s0_crc, crc_c66_s1_crc;
reg [31:0] crc_c66_s0_word1, crc_c66_s1_word2;
reg [31:0] crc_c66_s0_word2;
reg crc_c66_s0_last, crc_c66_s1_last;
wire [31:0] crc_next = crc32_update_word(crc_reg, crc_stream_data);
wire [31:0] crc_c66_s0_next = crc32_update_word(crc_reg, acc_result[31:0]);
wire [31:0] crc_c66_s1_next = crc32_update_word(crc_c66_s0_crc, crc_c66_s0_word1);
wire [31:0] crc_c66_final_next = crc32_update_word(crc_c66_s1_crc, crc_c66_s1_word2);
wire crc_c66_busy = crc_c66_s0_valid || crc_c66_s1_valid;
initial begin
crc32_table[0 ] = 32'h00000000; crc32_table[1 ] = 32'h77073096;
@@ -469,7 +437,7 @@ module matmul_axi_slave (
end
// ==========================================
// AXI Write 通道逻辑 (支持 INCR Burst)
// AXI Write (INCR Burst)
// ==========================================
localparam W_IDLE = 2'd0;
localparam W_DATA = 2'd1;
@@ -485,7 +453,6 @@ module matmul_axi_slave (
assign s_axi_bid = w_id;
assign s_axi_bresp = 2'b00;
// 前向声明引擎的状态
localparam C_IDLE = 2'd0;
localparam C_RUN = 2'd1;
reg [1:0] state;
@@ -508,7 +475,6 @@ module matmul_axi_slave (
reg [1:0] dma_wr_state;
reg [5:0] dma_wr_count;
// 【修改点 1】单独引出一个写脉冲信号给 CRC 清零用
wire crc_clear_pulse = (w_state == W_DATA) && s_axi_wvalid && s_axi_wready && (w_offset == ADDR_CRC);
wire done_clear_pulse = (w_state == W_DATA) && s_axi_wvalid && s_axi_wready &&
(w_offset == ADDR_STATUS) && s_axi_wdata[1];
@@ -534,24 +500,6 @@ module matmul_axi_slave (
dma_start_pulse <= 1'b0;
dma_done_clear_pulse <= 1'b0;
if (ep_wr_valid && ep_wr_ready) begin
if (ep_wr_bank[0] == 1'b0) begin
if (ep_wr_word_addr < 8'd16)
b0_a[ep_wr_lo_idx] <= ep_wr_data;
else if (ep_wr_word_addr < 8'd32)
b0_b[ep_wr_hi_idx] <= ep_wr_data;
else
error <= 1'b1;
end else begin
if (ep_wr_word_addr < 8'd16)
b1_a[ep_wr_lo_idx] <= ep_wr_data;
else if (ep_wr_word_addr < 8'd32)
b1_b[ep_wr_hi_idx] <= ep_wr_data;
else
error <= 1'b1;
end
end
if (dma_rd_commit) begin
if (dma_rd_bank == 1'b0) begin
if (dma_rd_count < 5'd16)
@@ -604,7 +552,7 @@ module matmul_axi_slave (
dma_src_stride <= apply_wstrb(dma_src_stride, s_axi_wdata, s_axi_wstrb);
else if (w_offset == ADDR_DMA_DST_STRIDE)
dma_dst_stride <= apply_wstrb(dma_dst_stride, s_axi_wdata, s_axi_wstrb);
// 【修改点 2】删除 else if (w_offset == ADDR_CRC) { crc_reg <= ... } 防止多重驱动
// CRC register is now managed by the pipelined CRC engine
else if (w_offset >= ADDR_B0_A && w_offset < ADDR_B0_B)
b0_a[(w_offset - ADDR_B0_A) >> 2] <= apply_wstrb(b0_a[(w_offset - ADDR_B0_A) >> 2], s_axi_wdata, s_axi_wstrb);
else if (w_offset >= ADDR_B0_B && w_offset < ADDR_B0_C)
@@ -645,7 +593,7 @@ module matmul_axi_slave (
end
// ==========================================
// AXI Read 通道逻辑 (支持 INCR Burst)
// AXI Read (INCR Burst)
// ==========================================
localparam R_IDLE = 2'd0;
localparam R_DATA = 2'd1;
@@ -697,7 +645,6 @@ module matmul_axi_slave (
end
R_DATA: begin
if (s_axi_rvalid && s_axi_rready) begin
// 【修改点 3】删掉直接赋值 crc_stream_valid 的逻辑，移至专用 Pipeline 块
if (r_cnt == r_len) begin
s_axi_rvalid <= 1'b0;
s_axi_rlast <= 1'b0;
@@ -725,7 +672,7 @@ module matmul_axi_slave (
else if (current_r_offset == ADDR_CRC)
s_axi_rdata = crc_reg ^ 32'hFFFFFFFF;
else if (current_r_offset == ADDR_STATUS)
s_axi_rdata = {27'b0, dma_done, dma_busy, error, done, busy};
s_axi_rdata = {26'b0, crc_c66_busy, dma_done, dma_busy, error, done, busy};
else if (current_r_offset == ADDR_DMA_SRC_BASE)
s_axi_rdata = dma_src_base;
else if (current_r_offset == ADDR_DMA_DST_BASE)
@@ -758,7 +705,7 @@ module matmul_axi_slave (
end
// ==========================================
// 计算引擎 (Compute FSM)
// Compute FSM
// ==========================================
wire [63:0] mult_p [0:3];
reg [31:0] m_in_a [0:3];
@@ -785,19 +732,66 @@ module matmul_axi_slave (
wire [65:0] acc_result = ({2'b0, mult_p[0]} + {2'b0, mult_p[1]}) +
({2'b0, mult_p[2]} + {2'b0, mult_p[3]});
wire crc_calc_valid = dma_busy && acc_valid_d4;
wire [31:0] crc_calc_next = crc32_update_c66(crc_reg, acc_result);
// CRC register: software/EP reads keep the legacy 32-bit path; autonomous DMA
// folds each 66-bit C element directly as low/mid/high words.
// DMA CRC issue spacing: compute FSM stalls via this counter to ensure
// ≥3 cycles between consecutive acc_result captures, matching the 3-stage
// CRC pipeline latency so crc_reg is committed before the next element.
reg [1:0] dma_crc_issue_gap;
wire dma_crc_issue_ready = !dma_busy || ((dma_crc_issue_gap == 2'd0) && !crc_c66_busy);
// CRC register update: DMA calc result (pipelined, 3-cycle latency)
// takes priority over AXI-stream (single-cycle). The stream path is
// only permitted when the DMA pipeline is idle (!crc_c66_busy).
always @(posedge clk) begin
if (!resetn) begin
crc_reg <= 32'hFFFFFFFF;
crc_reg <= 32'hFFFFFFFF;
crc_c66_s0_valid <= 1'b0;
crc_c66_s0_crc <= 32'b0;
crc_c66_s0_word1 <= 32'b0;
crc_c66_s0_word2 <= 32'b0;
crc_c66_s0_last <= 1'b0;
crc_c66_s1_valid <= 1'b0;
crc_c66_s1_crc <= 32'b0;
crc_c66_s1_word2 <= 32'b0;
crc_c66_s1_last <= 1'b0;
end else if (crc_clear_pulse) begin
crc_reg <= 32'hFFFFFFFF;
end else if (crc_calc_valid) begin
crc_reg <= crc_calc_next;
end else if (crc_stream_valid) begin
crc_reg <= crc_next;
crc_reg <= 32'hFFFFFFFF;
crc_c66_s0_valid <= 1'b0;
crc_c66_s0_crc <= 32'b0;
crc_c66_s0_word1 <= 32'b0;
crc_c66_s0_word2 <= 32'b0;
crc_c66_s0_last <= 1'b0;
crc_c66_s1_valid <= 1'b0;
crc_c66_s1_crc <= 32'b0;
crc_c66_s1_word2 <= 32'b0;
crc_c66_s1_last <= 1'b0;
end else begin
// Stage 1 → crc_reg finalize (word2 CRC)
if (crc_c66_s1_valid)
crc_reg <= crc_c66_final_next;
else if (crc_stream_valid && !crc_c66_busy)
crc_reg <= crc_next;
// Stage 0 → Stage 1 shift
crc_c66_s1_valid <= crc_c66_s0_valid;
if (crc_c66_s0_valid) begin
crc_c66_s1_crc <= crc_c66_s1_next;
crc_c66_s1_word2 <= crc_c66_s0_word2;
crc_c66_s1_last <= crc_c66_s0_last;
end else begin
crc_c66_s1_last <= 1'b0;
end
// Capture → Stage 0
crc_c66_s0_valid <= crc_calc_valid;
if (crc_calc_valid) begin
crc_c66_s0_crc <= crc_c66_s0_next;
crc_c66_s0_word1 <= acc_result[63:32];
crc_c66_s0_word2 <= {30'b0, acc_result[65:64]};
crc_c66_s0_last <= (acc_idx_d4 == 4'd15);
end else begin
crc_c66_s0_last <= 1'b0;
end
end
end
@@ -808,6 +802,7 @@ module matmul_axi_slave (
busy <= 1'b1;
state <= C_RUN;
pipe_cnt <= 5'd1;
dma_crc_issue_gap <= dma_busy ? 2'd2 : 2'd0;
acc_idx_d1 <= 4'd0;
acc_bank_d1 <= bank;
acc_valid_d1 <= 1'b1;
@@ -832,6 +827,7 @@ module matmul_axi_slave (
cur_bank <= 1'b0;
calc_done_pulse <= 1'b0;
pipe_cnt <= 5'd0;
dma_crc_issue_gap <= 2'd0;
acc_idx_d1 <= 4'd0;
acc_idx_d2 <= 4'd0;
acc_idx_d3 <= 4'd0;
@@ -846,8 +842,10 @@ module matmul_axi_slave (
acc_valid_d4 <= 1'b0;
end else begin
calc_done_pulse <= 1'b0;
if (dma_crc_issue_gap != 2'd0)
dma_crc_issue_gap <= dma_crc_issue_gap - 2'd1;
// Pipeline shift: issue_idx → d1 → d2 → d3 → d4 (4 cycles total)
// Pipeline shift (4 cycles total)
acc_idx_d4 <= acc_idx_d3;
acc_idx_d3 <= acc_idx_d2;
acc_idx_d2 <= acc_idx_d1;
@@ -874,21 +872,28 @@ module matmul_axi_slave (
end
C_RUN: begin
// Issue 4 new operands every cycle (pipe_cnt 0-15, 16 rounds)
// Issue 4 new operands per round. DMA mode inserts gap
// so the 3-stage CRC pipeline can commit before the next
// C-element capture.
if (pipe_cnt < 5'd16) begin
acc_idx_d1 <= pipe_cnt[3:0];
acc_bank_d1 <= cur_bank;
acc_valid_d1 <= 1'b1;
if (cur_bank == 1'b0) begin
m_in_a[0] <= b0_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b0_b[{2'd0, pipe_cnt[1:0]}];
m_in_a[1] <= b0_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b0_b[{2'd1, pipe_cnt[1:0]}];
m_in_a[2] <= b0_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b0_b[{2'd2, pipe_cnt[1:0]}];
m_in_a[3] <= b0_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b0_b[{2'd3, pipe_cnt[1:0]}];
end else begin
m_in_a[0] <= b1_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b1_b[{2'd0, pipe_cnt[1:0]}];
m_in_a[1] <= b1_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b1_b[{2'd1, pipe_cnt[1:0]}];
m_in_a[2] <= b1_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b1_b[{2'd2, pipe_cnt[1:0]}];
m_in_a[3] <= b1_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b1_b[{2'd3, pipe_cnt[1:0]}];
if (dma_crc_issue_ready) begin
acc_idx_d1 <= pipe_cnt[3:0];
acc_bank_d1 <= cur_bank;
acc_valid_d1 <= 1'b1;
if (cur_bank == 1'b0) begin
m_in_a[0] <= b0_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b0_b[{2'd0, pipe_cnt[1:0]}];
m_in_a[1] <= b0_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b0_b[{2'd1, pipe_cnt[1:0]}];
m_in_a[2] <= b0_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b0_b[{2'd2, pipe_cnt[1:0]}];
m_in_a[3] <= b0_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b0_b[{2'd3, pipe_cnt[1:0]}];
end else begin
m_in_a[0] <= b1_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b1_b[{2'd0, pipe_cnt[1:0]}];
m_in_a[1] <= b1_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b1_b[{2'd1, pipe_cnt[1:0]}];
m_in_a[2] <= b1_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b1_b[{2'd2, pipe_cnt[1:0]}];
m_in_a[3] <= b1_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b1_b[{2'd3, pipe_cnt[1:0]}];
end
if (dma_busy)
dma_crc_issue_gap <= 2'd2;
pipe_cnt <= pipe_cnt + 5'd1;
end
end
@@ -904,17 +909,30 @@ module matmul_axi_slave (
calc_done_pulse <= 1'b1;
end
if (pipe_cnt < 5'd16) begin
pipe_cnt <= pipe_cnt + 5'd1;
end else if (cur_bank == 1'b0 && req_1) begin
start_calc_bank(1'b1);
end else if (cur_bank == 1'b1 && req_0) begin
start_calc_bank(1'b0);
end else if (acc_valid_d4 && acc_idx_d4 == 4'd15) begin
busy <= 1'b0;
state <= C_IDLE;
end else begin
pipe_cnt <= pipe_cnt + 5'd1;
if (pipe_cnt >= 5'd16) begin
if (dma_busy) begin
if (acc_valid_d4 && acc_idx_d4 == 4'd15) begin
if (cur_bank == 1'b0 && req_1)
start_calc_bank(1'b1);
else if (cur_bank == 1'b1 && req_0)
start_calc_bank(1'b0);
else begin
busy <= 1'b0;
state <= C_IDLE;
end
end else begin
pipe_cnt <= pipe_cnt + 5'd1;
end
end else if (cur_bank == 1'b0 && req_1) begin
start_calc_bank(1'b1);
end else if (cur_bank == 1'b1 && req_0) begin
start_calc_bank(1'b0);
end else if (acc_valid_d4 && acc_idx_d4 == 4'd15) begin
busy <= 1'b0;
state <= C_IDLE;
end else begin
pipe_cnt <= pipe_cnt + 5'd1;
end
end
end
endcase