diff --git a/rtl/ip/PLL_2019_2/clk_pll.xci b/rtl/ip/PLL_2019_2/clk_pll.xci
index 67b47a7..113f373 100644
--- a/rtl/ip/PLL_2019_2/clk_pll.xci
+++ b/rtl/ip/PLL_2019_2/clk_pll.xci
@@ -119,7 +119,7 @@
1
0000
0000
- 25.00000
+ 50.00000
BUFG
50.0
false
@@ -136,10 +136,10 @@
BUFG
50.0
false
- 25.00000
+ 50.00000
0.000
50.000
- 25
+ 50
0.000
1
1
@@ -210,7 +210,7 @@
0000
1
0.66
- 1.32
+ 0.66
0.33
0.33
0.33
@@ -265,7 +265,7 @@
0.500
0.000
FALSE
- 62
+ 31
0.500
0.000
FALSE
@@ -300,7 +300,7 @@
Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
_cpu_clk__32.97872______0.000______50.0______130.093____123.600
_sys_clk__50.00000______0.000______50.0______122.035____123.600
- mlkem_clk__25.00000______0.000______50.0______135.799____123.600
+ mlkem_clk__50.00000______0.000______50.0______122.035____123.600
no_CLK_OUT4_output
no_CLK_OUT5_output
no_CLK_OUT6_output
@@ -438,11 +438,11 @@
1
true
BUFG
- 135.799
+ 122.035
false
123.600
50.000
- 25
+ 50
0.000
1
true
@@ -544,7 +544,7 @@
0.500
0.000
false
- 62
+ 31
0.500
0.000
false