feat: add prng
This commit is contained in:
@@ -4,7 +4,9 @@
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// maps do not overlap:
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// ML-KEM: 0x0000..0x3fff
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// FFT: 0x8000..0xcfff
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// Route the low ML-KEM block to ML-KEM and the high FFT block to FFT.
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// PRNG: 0xd000..0xd0ff
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// Route the low ML-KEM block to ML-KEM, the high FFT block to FFT, and the
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// following 0xdxxx block to PRNG.
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module fft_mlkem_axi_slave (
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input clk,
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input resetn,
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@@ -54,12 +56,23 @@ module fft_mlkem_axi_slave (
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output mlkem_intr
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);
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wire aw_to_mlkem = (s_axi_awaddr[15:12] <= 4'h3);
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wire ar_to_mlkem = (s_axi_araddr[15:12] <= 4'h3);
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localparam SEL_MLKEM = 2'd0;
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localparam SEL_FFT = 2'd1;
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localparam SEL_PRNG = 2'd2;
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reg write_sel_mlkem;
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wire aw_to_mlkem = (s_axi_awaddr[15:12] <= 4'h3);
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wire aw_to_prng = (s_axi_awaddr[15:12] == 4'hd);
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wire ar_to_mlkem = (s_axi_araddr[15:12] <= 4'h3);
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wire ar_to_prng = (s_axi_araddr[15:12] == 4'hd);
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wire [1:0] aw_sel = aw_to_mlkem ? SEL_MLKEM :
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aw_to_prng ? SEL_PRNG : SEL_FFT;
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wire [1:0] ar_sel = ar_to_mlkem ? SEL_MLKEM :
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ar_to_prng ? SEL_PRNG : SEL_FFT;
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reg [1:0] write_sel;
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reg write_active;
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reg read_sel_mlkem;
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reg [1:0] read_sel;
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reg read_active;
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wire mlkem_awready, mlkem_wready, mlkem_bvalid;
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@@ -78,39 +91,71 @@ module fft_mlkem_axi_slave (
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wire [31:0] fft_rdata;
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wire [1:0] fft_rresp;
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wire sel_w_mlkem = write_active ? write_sel_mlkem : aw_to_mlkem;
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wire sel_r_mlkem = read_active ? read_sel_mlkem : ar_to_mlkem;
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wire prng_awready, prng_wready, prng_bvalid;
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wire [4:0] prng_bid;
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wire [1:0] prng_bresp;
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wire prng_arready, prng_rvalid, prng_rlast;
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wire [4:0] prng_rid;
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wire [31:0] prng_rdata;
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wire [1:0] prng_rresp;
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assign s_axi_awready = !write_active && (aw_to_mlkem ? mlkem_awready : fft_awready);
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assign s_axi_wready = sel_w_mlkem ? mlkem_wready : fft_wready;
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assign s_axi_bvalid = sel_w_mlkem ? mlkem_bvalid : fft_bvalid;
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assign s_axi_bid = sel_w_mlkem ? mlkem_bid : fft_bid;
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assign s_axi_bresp = sel_w_mlkem ? mlkem_bresp : fft_bresp;
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wire [1:0] sel_w = write_active ? write_sel : aw_sel;
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wire [1:0] sel_r = read_active ? read_sel : ar_sel;
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assign s_axi_arready = !read_active && (ar_to_mlkem ? mlkem_arready : fft_arready);
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assign s_axi_rvalid = sel_r_mlkem ? mlkem_rvalid : fft_rvalid;
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assign s_axi_rlast = sel_r_mlkem ? mlkem_rlast : fft_rlast;
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assign s_axi_rid = sel_r_mlkem ? mlkem_rid : fft_rid;
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assign s_axi_rdata = sel_r_mlkem ? mlkem_rdata : fft_rdata;
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assign s_axi_rresp = sel_r_mlkem ? mlkem_rresp : fft_rresp;
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assign s_axi_awready = !write_active && (
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(aw_sel == SEL_MLKEM) ? mlkem_awready :
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(aw_sel == SEL_PRNG) ? prng_awready :
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fft_awready);
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assign s_axi_wready = (sel_w == SEL_MLKEM) ? mlkem_wready :
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(sel_w == SEL_PRNG) ? prng_wready :
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fft_wready;
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assign s_axi_bvalid = (sel_w == SEL_MLKEM) ? mlkem_bvalid :
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(sel_w == SEL_PRNG) ? prng_bvalid :
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fft_bvalid;
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assign s_axi_bid = (sel_w == SEL_MLKEM) ? mlkem_bid :
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(sel_w == SEL_PRNG) ? prng_bid :
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fft_bid;
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assign s_axi_bresp = (sel_w == SEL_MLKEM) ? mlkem_bresp :
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(sel_w == SEL_PRNG) ? prng_bresp :
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fft_bresp;
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assign s_axi_arready = !read_active && (
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(ar_sel == SEL_MLKEM) ? mlkem_arready :
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(ar_sel == SEL_PRNG) ? prng_arready :
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fft_arready);
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assign s_axi_rvalid = (sel_r == SEL_MLKEM) ? mlkem_rvalid :
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(sel_r == SEL_PRNG) ? prng_rvalid :
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fft_rvalid;
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assign s_axi_rlast = (sel_r == SEL_MLKEM) ? mlkem_rlast :
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(sel_r == SEL_PRNG) ? prng_rlast :
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fft_rlast;
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assign s_axi_rid = (sel_r == SEL_MLKEM) ? mlkem_rid :
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(sel_r == SEL_PRNG) ? prng_rid :
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fft_rid;
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assign s_axi_rdata = (sel_r == SEL_MLKEM) ? mlkem_rdata :
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(sel_r == SEL_PRNG) ? prng_rdata :
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fft_rdata;
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assign s_axi_rresp = (sel_r == SEL_MLKEM) ? mlkem_rresp :
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(sel_r == SEL_PRNG) ? prng_rresp :
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fft_rresp;
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always @(posedge clk or negedge resetn) begin
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if (!resetn) begin
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write_active <= 1'b0;
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write_sel_mlkem <= 1'b0;
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write_sel <= SEL_MLKEM;
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read_active <= 1'b0;
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read_sel_mlkem <= 1'b0;
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read_sel <= SEL_MLKEM;
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end else begin
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if (!write_active && s_axi_awvalid && s_axi_awready) begin
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write_active <= 1'b1;
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write_sel_mlkem <= aw_to_mlkem;
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write_sel <= aw_sel;
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end else if (write_active && s_axi_bvalid && s_axi_bready) begin
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write_active <= 1'b0;
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end
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if (!read_active && s_axi_arvalid && s_axi_arready) begin
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read_active <= 1'b1;
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read_sel_mlkem <= ar_to_mlkem;
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read_sel <= ar_sel;
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end else if (read_active && s_axi_rvalid && s_axi_rready && s_axi_rlast) begin
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read_active <= 1'b0;
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end
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@@ -129,20 +174,20 @@ module fft_mlkem_axi_slave (
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.s_axi_awlock (s_axi_awlock),
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.s_axi_awcache (s_axi_awcache),
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.s_axi_awprot (s_axi_awprot),
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.s_axi_awvalid (s_axi_awvalid && !write_active && aw_to_mlkem),
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.s_axi_awvalid (s_axi_awvalid && !write_active && (aw_sel == SEL_MLKEM)),
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.s_axi_awready (mlkem_awready),
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.s_axi_wid (s_axi_wid),
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.s_axi_wdata (s_axi_wdata),
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.s_axi_wstrb (s_axi_wstrb),
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.s_axi_wlast (s_axi_wlast),
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.s_axi_wvalid (s_axi_wvalid && sel_w_mlkem),
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.s_axi_wvalid (s_axi_wvalid && (sel_w == SEL_MLKEM)),
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.s_axi_wready (mlkem_wready),
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.s_axi_bid (mlkem_bid),
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.s_axi_bresp (mlkem_bresp),
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.s_axi_bvalid (mlkem_bvalid),
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.s_axi_bready (s_axi_bready && sel_w_mlkem),
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.s_axi_bready (s_axi_bready && (sel_w == SEL_MLKEM)),
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.s_axi_arid (s_axi_arid),
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.s_axi_araddr (s_axi_araddr),
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@@ -152,7 +197,7 @@ module fft_mlkem_axi_slave (
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.s_axi_arlock (s_axi_arlock),
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.s_axi_arcache (s_axi_arcache),
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.s_axi_arprot (s_axi_arprot),
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.s_axi_arvalid (s_axi_arvalid && !read_active && ar_to_mlkem),
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.s_axi_arvalid (s_axi_arvalid && !read_active && (ar_sel == SEL_MLKEM)),
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.s_axi_arready (mlkem_arready),
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.s_axi_rid (mlkem_rid),
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@@ -160,7 +205,7 @@ module fft_mlkem_axi_slave (
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.s_axi_rresp (mlkem_rresp),
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.s_axi_rlast (mlkem_rlast),
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.s_axi_rvalid (mlkem_rvalid),
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.s_axi_rready (s_axi_rready && sel_r_mlkem),
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.s_axi_rready (s_axi_rready && (sel_r == SEL_MLKEM)),
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.intr (mlkem_intr)
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);
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@@ -177,20 +222,20 @@ module fft_mlkem_axi_slave (
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.s_awlock (s_axi_awlock),
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.s_awcache (s_axi_awcache),
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.s_awprot (s_axi_awprot),
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.s_awvalid (s_axi_awvalid && !write_active && !aw_to_mlkem),
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.s_awvalid (s_axi_awvalid && !write_active && (aw_sel == SEL_FFT)),
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.s_awready (fft_awready),
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.s_wid (s_axi_wid),
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.s_wdata (s_axi_wdata),
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.s_wstrb (s_axi_wstrb),
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.s_wlast (s_axi_wlast),
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.s_wvalid (s_axi_wvalid && !sel_w_mlkem),
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.s_wvalid (s_axi_wvalid && (sel_w == SEL_FFT)),
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.s_wready (fft_wready),
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.s_bid (fft_bid),
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.s_bresp (fft_bresp),
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.s_bvalid (fft_bvalid),
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.s_bready (s_axi_bready && !sel_w_mlkem),
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.s_bready (s_axi_bready && (sel_w == SEL_FFT)),
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.s_arid (s_axi_arid),
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.s_araddr (s_axi_araddr),
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@@ -200,7 +245,7 @@ module fft_mlkem_axi_slave (
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.s_arlock (s_axi_arlock),
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.s_arcache (s_axi_arcache),
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.s_arprot (s_axi_arprot),
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.s_arvalid (s_axi_arvalid && !read_active && !ar_to_mlkem),
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.s_arvalid (s_axi_arvalid && !read_active && (ar_sel == SEL_FFT)),
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.s_arready (fft_arready),
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.s_rid (fft_rid),
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@@ -208,9 +253,55 @@ module fft_mlkem_axi_slave (
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.s_rresp (fft_rresp),
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.s_rlast (fft_rlast),
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.s_rvalid (fft_rvalid),
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.s_rready (s_axi_rready && !sel_r_mlkem),
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.s_rready (s_axi_rready && (sel_r == SEL_FFT)),
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.fft_finish (fft_finish)
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);
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prng_axi_slave u_prng_axi_slave (
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.clk (clk),
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.resetn (resetn),
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.s_axi_awid (s_axi_awid),
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.s_axi_awaddr (s_axi_awaddr),
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.s_axi_awlen (s_axi_awlen),
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.s_axi_awsize (s_axi_awsize),
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.s_axi_awburst (s_axi_awburst),
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.s_axi_awlock (s_axi_awlock),
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.s_axi_awcache (s_axi_awcache),
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.s_axi_awprot (s_axi_awprot),
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.s_axi_awvalid (s_axi_awvalid && !write_active && (aw_sel == SEL_PRNG)),
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.s_axi_awready (prng_awready),
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.s_axi_wid (s_axi_wid),
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.s_axi_wdata (s_axi_wdata),
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.s_axi_wstrb (s_axi_wstrb),
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.s_axi_wlast (s_axi_wlast),
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.s_axi_wvalid (s_axi_wvalid && (sel_w == SEL_PRNG)),
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.s_axi_wready (prng_wready),
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.s_axi_bid (prng_bid),
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.s_axi_bresp (prng_bresp),
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.s_axi_bvalid (prng_bvalid),
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.s_axi_bready (s_axi_bready && (sel_w == SEL_PRNG)),
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.s_axi_arid (s_axi_arid),
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.s_axi_araddr (s_axi_araddr),
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.s_axi_arlen (s_axi_arlen),
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.s_axi_arsize (s_axi_arsize),
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.s_axi_arburst (s_axi_arburst),
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.s_axi_arlock (s_axi_arlock),
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.s_axi_arcache (s_axi_arcache),
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.s_axi_arprot (s_axi_arprot),
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.s_axi_arvalid (s_axi_arvalid && !read_active && (ar_sel == SEL_PRNG)),
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.s_axi_arready (prng_arready),
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.s_axi_rid (prng_rid),
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.s_axi_rdata (prng_rdata),
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.s_axi_rresp (prng_rresp),
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.s_axi_rlast (prng_rlast),
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.s_axi_rvalid (prng_rvalid),
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.s_axi_rready (s_axi_rready && (sel_r == SEL_PRNG))
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);
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endmodule
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218
rtl/ip/prng/prng_axi_slave.v
Normal file
218
rtl/ip/prng/prng_axi_slave.v
Normal file
@@ -0,0 +1,218 @@
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// Lightweight AXI4 register endpoint for a pseudo-random generator.
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//
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// Register map, byte offsets within the shared accelerator window:
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// 0xd000 CTRL W bit0=mix software seed, bit1=clear counters
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// 0xd004 STATUS R bit0=ready
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// 0xd008 DATA R next 32-bit random word
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// 0xd00c COUNT R number of DATA reads
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// 0xd010 SEED W software seed/mix value
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//
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// This block is deterministic unless software mixes in an external seed. It
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// intentionally uses only flops, XORs, shifts, and adders.
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module prng_axi_slave (
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input clk,
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input resetn,
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input [4:0] s_axi_awid,
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input [31:0] s_axi_awaddr,
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input [7:0] s_axi_awlen,
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input [2:0] s_axi_awsize,
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input [1:0] s_axi_awburst,
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input s_axi_awlock,
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input [3:0] s_axi_awcache,
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input [2:0] s_axi_awprot,
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input s_axi_awvalid,
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output s_axi_awready,
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input [4:0] s_axi_wid,
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input [31:0] s_axi_wdata,
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input [3:0] s_axi_wstrb,
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input s_axi_wlast,
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input s_axi_wvalid,
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output s_axi_wready,
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output [4:0] s_axi_bid,
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output [1:0] s_axi_bresp,
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output reg s_axi_bvalid,
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input s_axi_bready,
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input [4:0] s_axi_arid,
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input [31:0] s_axi_araddr,
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input [7:0] s_axi_arlen,
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input [2:0] s_axi_arsize,
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input [1:0] s_axi_arburst,
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input s_axi_arlock,
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input [3:0] s_axi_arcache,
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input [2:0] s_axi_arprot,
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input s_axi_arvalid,
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output s_axi_arready,
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output reg [4:0] s_axi_rid,
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output reg [31:0] s_axi_rdata,
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output [1:0] s_axi_rresp,
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output reg s_axi_rlast,
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output reg s_axi_rvalid,
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input s_axi_rready
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);
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localparam ADDR_CTRL = 12'h000;
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localparam ADDR_STATUS = 12'h004;
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localparam ADDR_DATA = 12'h008;
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localparam ADDR_COUNT = 12'h00c;
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localparam ADDR_SEED = 12'h010;
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assign s_axi_bresp = 2'b00;
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assign s_axi_rresp = 2'b00;
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reg [4:0] awid_reg;
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reg [31:0] awaddr_reg;
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reg [7:0] awleft_reg;
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reg write_active;
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assign s_axi_awready = !write_active && !s_axi_bvalid;
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assign s_axi_wready = write_active && !s_axi_bvalid;
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assign s_axi_bid = awid_reg;
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reg [31:0] araddr_reg;
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reg [7:0] arleft_reg;
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reg read_active;
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assign s_axi_arready = !read_active && !s_axi_rvalid;
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reg [127:0] rng_state;
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reg [63:0] free_counter;
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reg [31:0] seed_mix;
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reg [31:0] data_reads;
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wire lfsr_fb = rng_state[127] ^ rng_state[125] ^ rng_state[100] ^
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rng_state[98] ^ rng_state[27] ^ rng_state[0] ^
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free_counter[0];
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wire [127:0] rng_next = {rng_state[126:0], lfsr_fb} ^
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{free_counter, free_counter ^ {32'h0, seed_mix}};
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wire [31:0] rng_word = rng_state[31:0] ^ rng_state[63:32] ^
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rng_state[95:64] ^ rng_state[127:96] ^
|
||||
free_counter[31:0] ^ free_counter[63:32] ^
|
||||
seed_mix;
|
||||
|
||||
function [31:0] apply_wstrb;
|
||||
input [31:0] old_value;
|
||||
input [31:0] new_value;
|
||||
input [3:0] strobe;
|
||||
begin
|
||||
apply_wstrb = old_value;
|
||||
if (strobe[0]) apply_wstrb[7:0] = new_value[7:0];
|
||||
if (strobe[1]) apply_wstrb[15:8] = new_value[15:8];
|
||||
if (strobe[2]) apply_wstrb[23:16] = new_value[23:16];
|
||||
if (strobe[3]) apply_wstrb[31:24] = new_value[31:24];
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [31:0] read_reg;
|
||||
input [31:0] addr;
|
||||
begin
|
||||
case (addr[11:0])
|
||||
ADDR_STATUS: read_reg = 32'h00000001;
|
||||
ADDR_DATA: read_reg = rng_word;
|
||||
ADDR_COUNT: read_reg = data_reads;
|
||||
ADDR_SEED: read_reg = seed_mix;
|
||||
default: read_reg = 32'h00000000;
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
|
||||
wire write_fire = s_axi_wvalid && s_axi_wready;
|
||||
wire read_fire = s_axi_rvalid && s_axi_rready;
|
||||
wire data_read_fire = read_fire && (araddr_reg[11:0] == ADDR_DATA);
|
||||
wire [31:0] next_araddr = araddr_reg + 32'd4;
|
||||
wire [31:0] next_awaddr = awaddr_reg + 32'd4;
|
||||
|
||||
always @(posedge clk or negedge resetn) begin
|
||||
if (!resetn) begin
|
||||
awid_reg <= 5'b0;
|
||||
awaddr_reg <= 32'b0;
|
||||
awleft_reg <= 8'b0;
|
||||
write_active <= 1'b0;
|
||||
s_axi_bvalid <= 1'b0;
|
||||
|
||||
araddr_reg <= 32'b0;
|
||||
arleft_reg <= 8'b0;
|
||||
read_active <= 1'b0;
|
||||
s_axi_rid <= 5'b0;
|
||||
s_axi_rdata <= 32'b0;
|
||||
s_axi_rlast <= 1'b0;
|
||||
s_axi_rvalid <= 1'b0;
|
||||
|
||||
rng_state <= 128'h6d5a_56c3_9e37_79b9_a5a5_3c3c_c001_c0de;
|
||||
free_counter <= 64'h1;
|
||||
seed_mix <= 32'h31415927;
|
||||
data_reads <= 32'b0;
|
||||
end else begin
|
||||
free_counter <= free_counter + 64'h9e37_79b9_7f4a_7c15;
|
||||
rng_state <= rng_next;
|
||||
|
||||
if (s_axi_awvalid && s_axi_awready) begin
|
||||
awid_reg <= s_axi_awid;
|
||||
awaddr_reg <= s_axi_awaddr;
|
||||
awleft_reg <= s_axi_awlen;
|
||||
write_active <= 1'b1;
|
||||
end
|
||||
|
||||
if (write_fire) begin
|
||||
case (awaddr_reg[11:0])
|
||||
ADDR_CTRL: begin
|
||||
if (s_axi_wdata[0]) begin
|
||||
seed_mix <= seed_mix ^ s_axi_wdata ^ free_counter[31:0];
|
||||
rng_state <= rng_next ^ {4{s_axi_wdata}};
|
||||
end
|
||||
if (s_axi_wdata[1])
|
||||
data_reads <= 32'b0;
|
||||
end
|
||||
ADDR_SEED: begin
|
||||
seed_mix <= apply_wstrb(seed_mix, s_axi_wdata, s_axi_wstrb);
|
||||
rng_state <= rng_next ^ {s_axi_wdata, free_counter, ~s_axi_wdata};
|
||||
end
|
||||
default: begin
|
||||
end
|
||||
endcase
|
||||
|
||||
if (s_axi_wlast || awleft_reg == 8'b0) begin
|
||||
write_active <= 1'b0;
|
||||
s_axi_bvalid <= 1'b1;
|
||||
end else begin
|
||||
awleft_reg <= awleft_reg - 8'd1;
|
||||
awaddr_reg <= next_awaddr;
|
||||
end
|
||||
end
|
||||
|
||||
if (s_axi_bvalid && s_axi_bready)
|
||||
s_axi_bvalid <= 1'b0;
|
||||
|
||||
if (s_axi_arvalid && s_axi_arready) begin
|
||||
read_active <= 1'b1;
|
||||
araddr_reg <= s_axi_araddr;
|
||||
arleft_reg <= s_axi_arlen;
|
||||
s_axi_rid <= s_axi_arid;
|
||||
s_axi_rdata <= read_reg(s_axi_araddr);
|
||||
s_axi_rlast <= (s_axi_arlen == 8'b0);
|
||||
s_axi_rvalid <= 1'b1;
|
||||
end else if (read_fire) begin
|
||||
if (data_read_fire) begin
|
||||
data_reads <= data_reads + 32'd1;
|
||||
rng_state <= rng_next ^ {rng_word, rng_word ^ free_counter[31:0],
|
||||
free_counter[63:32], ~rng_word};
|
||||
end
|
||||
|
||||
if (s_axi_rlast) begin
|
||||
read_active <= 1'b0;
|
||||
s_axi_rvalid <= 1'b0;
|
||||
end else begin
|
||||
araddr_reg <= next_araddr;
|
||||
arleft_reg <= arleft_reg - 8'd1;
|
||||
s_axi_rdata <= read_reg(next_araddr);
|
||||
s_axi_rlast <= (arleft_reg == 8'd1);
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user