From 45731e05b7f3d7ee7ee736f580d2556f61f18c68 Mon Sep 17 00:00:00 2001 From: FallenSigh Date: Fri, 26 Jun 2026 03:54:20 +0800 Subject: [PATCH] perf(matmul): add pipeline timing diagnostics (v2.1) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Measure per-phase wait times and stall counts to identify bottleneck: - PIPE_WAIT_IP / DMA0 / DMA1: aggregate wait time per resource - PIPE_FIRE_DMA / IP: register write overhead - PIPE_STALL_*: iterations where each resource actually blocked Output after standard markers, before MATMUL_DONE. Allows data-driven decision on next optimization target: wait_ip dominant → optimize IP (HW multiplier pipeline) wait_dma0 dominant → pre-fire insufficient (wider bus/faster RAM) wait_dma1 dominant → bank reuse delay (deeper buffering) --- sdk/software/examples/asm/user-sample.c | 127 ++++++++++++++++-------- 1 file changed, 87 insertions(+), 40 deletions(-) diff --git a/sdk/software/examples/asm/user-sample.c b/sdk/software/examples/asm/user-sample.c index 4b8b243..2a09c60 100644 --- a/sdk/software/examples/asm/user-sample.c +++ b/sdk/software/examples/asm/user-sample.c @@ -9,8 +9,8 @@ * 3. Inlined DMA start → skips redundant STATUS_BUSY_BIT check * 4. XOR bank toggle → avoids g%2 recomputation per iteration * - * Utilizes true DMA transfers (Channel 0 for memory→IP, Channel 1 for IP→memory) - * perfectly overlapped with Hardware IP computation to achieve Zero-Wait execution. + * v2.1: Pipeline timing diagnostics — measures per-phase wait times + * and stall counts to identify the real bottleneck (IP vs DMA vs store). */ #include @@ -21,7 +21,7 @@ #include #include -/* ─── Configurable group count (default 5000) ──────────────────────── */ +/* ─── Configurable group count (default 5000 for diagnostics) ──────── */ #ifndef MATMUL_GROUP_NUM #define MATMUL_GROUP_NUM 5000 #endif @@ -48,14 +48,10 @@ unsigned long CORE_CLOCKS_PER_SEC = 33000000L; #define MATMUL_BASE_PHYS 0x1f500000 #define MATMUL_BASE_UNCACHED 0xbf500000 -// CPU Control & Status Registers #define MATMUL_CTRL (MATMUL_BASE_UNCACHED + 0x000) #define MATMUL_STATUS (MATMUL_BASE_UNCACHED + 0x004) - -// DMA Physical Addresses for IP Space -// (A and B are contiguous: A is 0x100~0x13F, B is 0x140~0x17F. Total 128 bytes) #define MATMUL_PHYS_B0_AB (MATMUL_BASE_PHYS + 0x100) -#define MATMUL_PHYS_B0_C (MATMUL_BASE_PHYS + 0x180) // 192 bytes +#define MATMUL_PHYS_B0_C (MATMUL_BASE_PHYS + 0x180) #define MATMUL_PHYS_B1_AB (MATMUL_BASE_PHYS + 0x300) #define MATMUL_PHYS_B1_C (MATMUL_BASE_PHYS + 0x380) @@ -64,7 +60,6 @@ unsigned long CORE_CLOCKS_PER_SEC = 33000000L; #define STATUS_DONE 0x2 #define STATUS_ERROR 0x4 -// Hardware CRC register (offset 0x010 in matmul IP) #define MATMUL_CRC (MATMUL_BASE_UNCACHED + 0x010) /* ─── Pre-computed DMA burst control word ──────────────────────────── */ @@ -89,23 +84,33 @@ int main(void) // Ping-Pong Register Address Arrays (Physical for DMA) uint32_t phys_bank_AB[2] = {MATMUL_PHYS_B0_AB, MATMUL_PHYS_B1_AB}; uint32_t phys_bank_C[2] = {MATMUL_PHYS_B0_C, MATMUL_PHYS_B1_C}; - - // IP Control Command Arrays uint32_t ctrl_start[2] = {CTRL_START_B0, CTRL_START_B1}; + /* ── Pipeline timing diagnostics ──────────────────────────────── */ + uint32_t t_now; + uint32_t t_wait_ip = 0; // total ns waiting for IP done + uint32_t t_wait_dma0 = 0; // total ns waiting for DMA Ch0 done + uint32_t t_wait_dma1 = 0; // total ns waiting for DMA Ch1 done + uint32_t t_fire_dma = 0; // total ns writing DMA registers + uint32_t t_fire_ip = 0; // total ns writing IP ctrl register + int n_loops = 0; // main loop iteration count + int stall_ip = 0; // iterations where wait_ip actually blocked + int stall_dma0 = 0; // iterations where wait_dma0 actually blocked + int stall_dma1 = 0; // iterations where wait_dma1 actually blocked + /* ── Start marker (must be first output) ──────────────────── */ printf("MATMUL_START\n"); // Reset IP state *mat_status = STATUS_DONE | STATUS_ERROR; - *mat_crc = 0; // Reset hardware CRC32 to 0xFFFFFFFF + *mat_crc = 0; /* ═══════════════════════════════════════════════════════════════ * PROLOGUE: Load group 0 → Bank 0, start IP, pre-fire group 1 * ═══════════════════════════════════════════════════════════════ */ t_prologue = get_ns(); - // DMA Ch0: Load group 0 A+B (128 bytes) from ExtRAM → IP Bank 0 + // DMA Ch0: Load group 0 A+B (128 bytes) → IP Bank 0 ch0->SRC_ADDR = EXTRAM_PHYS_AB(0); ch0->DST_ADDR = phys_bank_AB[0]; ch0->LENGTH = 128; @@ -117,7 +122,7 @@ int main(void) // Start IP Bank 0 (group 0) *mat_ctrl = ctrl_start[0]; - // Pre-fire: DMA Ch0 load group 1 → Bank 1 (overlaps with IP compute of group 0!) + // Pre-fire: DMA Ch0 load group 1 → Bank 1 (overlaps with IP compute) if (MATMUL_GROUP_NUM > 1) { ch0->SRC_ADDR = EXTRAM_PHYS_AB(1); ch0->DST_ADDR = phys_bank_AB[1]; @@ -130,60 +135,76 @@ int main(void) /* ═══════════════════════════════════════════════════════════════ * MAIN LOOP: Fully-pipelined — pre-fire DMA load at loop tail - * - * At iteration g: - * IP is computing group (g-1) on prev_bank - * Ch0 loaded group g to cur_bank (pre-fired in iteration g-1) - * - * Pipeline: - * Ch0: | load g+1 | | load g+2 | - * Ch1: | store g-1 | | store g | - * IP : | compute g | | compute g+1 | + * + per-phase timing diagnostics * ═══════════════════════════════════════════════════════════════ */ t_mainloop = get_ns(); - bank = 1; // cur_bank for iteration g=1; prev_bank = bank ^ 1 + bank = 1; + + // Prologue IP start time (for measuring first IP compute duration) + // We can't easily isolate pure IP time, but aggregate wait tells us. for (g = 1; g < MATMUL_GROUP_NUM; g++) { int cur_bank = bank; int prev_bank = bank ^ 1; - // 1. Wait for previous IP computation (group g-1 on prev_bank) + /* ── 1. Wait for previous IP computation ─────────────────── */ + t_now = get_ns(); while (!(*mat_status & STATUS_DONE)) {} *mat_status = STATUS_DONE; - - // 2. Ensure previous DMA Ch1 store is done (group g-2) - if (g > 1) { - while (!(ch1->STATUS & STATUS_DONE_BIT)) {} - ch1->STATUS = STATUS_DONE_BIT; + { + uint32_t dt = get_ns() - t_now; + t_wait_ip += dt; + if (dt > 0) stall_ip++; } - // 3. Start DMA Ch1 store: group (g-1) result → ExtRAM + /* ── 2. Wait for previous DMA Ch1 store ──────────────────── */ + if (g > 1) { + t_now = get_ns(); + while (!(ch1->STATUS & STATUS_DONE_BIT)) {} + ch1->STATUS = STATUS_DONE_BIT; + uint32_t dt = get_ns() - t_now; + t_wait_dma1 += dt; + if (dt > 0) stall_dma1++; + } + + /* ── 3. Start DMA Ch1 store: group (g-1) result → ExtRAM ── */ + t_now = get_ns(); ch1->SRC_ADDR = phys_bank_C[prev_bank]; ch1->DST_ADDR = EXTRAM_PHYS_C(g - 1); ch1->LENGTH = 192; ch1->TAG = 20; ch1->CTRL = DMA_CTRL_VAL; + t_fire_dma += (get_ns() - t_now); - // 4. Wait for current DMA Ch0 load (group g → cur_bank, pre-fired in iteration g-1) + /* ── 4. Wait for DMA Ch0 load (pre-fired in prev iteration) */ + t_now = get_ns(); while (!(ch0->STATUS & STATUS_DONE_BIT)) {} ch0->STATUS = STATUS_DONE_BIT; + { + uint32_t dt = get_ns() - t_now; + t_wait_dma0 += dt; + if (dt > 0) stall_dma0++; + } - // 5. Start IP computation for current group on cur_bank + /* ── 5. Start IP computation ─────────────────────────────── */ + t_now = get_ns(); *mat_ctrl = ctrl_start[cur_bank]; + t_fire_ip += (get_ns() - t_now); - // ★ 6. PRE-FIRE: DMA Ch0 load next group (g+1) → next_bank - // This runs CONCURRENTLY with IP computation started in step 5! + /* ── 6. PRE-FIRE DMA Ch0 load for next group ─────────────── */ if (g < MATMUL_GROUP_NUM - 1) { int next_bank = bank ^ 1; + t_now = get_ns(); ch0->SRC_ADDR = EXTRAM_PHYS_AB(g + 1); ch0->DST_ADDR = phys_bank_AB[next_bank]; ch0->LENGTH = 128; ch0->TAG = 10; ch0->CTRL = DMA_CTRL_VAL; + t_fire_dma += (get_ns() - t_now); } - // Toggle bank for next iteration bank ^= 1; + n_loops++; } t_mainloop = get_ns() - t_mainloop; @@ -192,11 +213,11 @@ int main(void) * ═══════════════════════════════════════════════════════════════ */ t_epilogue = get_ns(); - // Wait for last IP computation to finish + // Wait for last IP computation while (!(*mat_status & STATUS_DONE)) {} *mat_status = STATUS_DONE; - // Wait for last DMA Ch1 store (group MATMUL_GROUP_NUM-2) and then store final group + // Wait for previous DMA store and start/complete final store while (!(ch1->STATUS & STATUS_DONE_BIT)) {} ch1->STATUS = STATUS_DONE_BIT; @@ -210,16 +231,42 @@ int main(void) t_epilogue = get_ns() - t_epilogue; - /* ── Read hardware CRC32 result ──────────────────────────── */ + /* ── Read hardware CRC32 ──────────────────────────────────── */ crc = *mat_crc; - /* ── Final markers ────────────────────────────────────────── */ + /* ── Standard markers (required by test harness) ────────────── */ printf("MATMUL_CRC32=%08lx\n", (unsigned long)crc); printf("TIME_PROLOGUE=%lu\n", (unsigned long)t_prologue); printf("TIME_LOOP=%lu\n", (unsigned long)t_mainloop); printf("TIME_LOOP_PER=%lu\n", (unsigned long)(t_mainloop / MATMUL_GROUP_NUM)); printf("TIME_EPILOGUE=%lu\n", (unsigned long)t_epilogue); printf("TIME_TOTAL=%lu\n", (unsigned long)(t_prologue + t_mainloop + t_epilogue)); + + /* ═══════════════════════════════════════════════════════════════ + * Pipeline Timing Diagnostics + * + * Interpretation guide: + * PIPE_WAIT_DMA0 ≈ 0 → pre-fire working, DMA load never blocks + * PIPE_WAIT_DMA0 > 0 → DMA load is bottleneck (wider bus / faster RAM) + * PIPE_WAIT_IP > 0 → IP compute is bottleneck (optimize multiplier HW) + * PIPE_WAIT_DMA1 > 0 → DMA store is bottleneck (bank reuse delay) + * PIPE_STALL_* = N → that resource blocked EVERY iteration + * + * All times in nanoseconds. Averages over N-1 loop iterations. + * ═══════════════════════════════════════════════════════════════ */ + printf("--- Pipeline Profile (%d loop iterations) ---\n", n_loops); + printf("PIPE_WAIT_IP=%lu\n", (unsigned long)t_wait_ip); + printf("PIPE_WAIT_IP_AVG=%lu\n", (unsigned long)(n_loops ? t_wait_ip / n_loops : 0)); + printf("PIPE_WAIT_DMA0=%lu\n", (unsigned long)t_wait_dma0); + printf("PIPE_WAIT_DMA0_AVG=%lu\n", (unsigned long)(n_loops ? t_wait_dma0 / n_loops : 0)); + printf("PIPE_WAIT_DMA1=%lu\n", (unsigned long)t_wait_dma1); + printf("PIPE_WAIT_DMA1_AVG=%lu\n", (unsigned long)(n_loops ? t_wait_dma1 / n_loops : 0)); + printf("PIPE_FIRE_DMA=%lu\n", (unsigned long)t_fire_dma); + printf("PIPE_FIRE_IP=%lu\n", (unsigned long)t_fire_ip); + printf("PIPE_STALL_IP=%d\n", stall_ip); + printf("PIPE_STALL_DMA0=%d\n", stall_dma0); + printf("PIPE_STALL_DMA1=%d\n", stall_dma1); + printf("PIPE_SUM_WAITS=%lu\n", (unsigned long)(t_wait_ip + t_wait_dma0 + t_wait_dma1 + t_fire_dma + t_fire_ip)); printf("MATMUL_DONE\n"); return 0;