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feat: optimize sram write channel

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FallenSigh
2026-07-04 18:54:05 +08:00
parent 58f99d82ba
commit 3f7c9b7a37
1 changed files with 3 additions and 10 deletions
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13
rtl/ip/Bus_interconnects/axi2sram_sp_external.v
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@@ -95,7 +95,6 @@ module axi2sram_sp_external #(
localparam WRITE = 3'h2; localparam WRITE = 3'h2;
localparam SEND_B = 3'h3; localparam SEND_B = 3'h3;
localparam WAIT_WVALID = 3'h4; localparam WAIT_WVALID = 3'h4;
localparam WRITE_NOP = 3'h5;
localparam READ_ADDR = 3'h6; localparam READ_ADDR = 3'h6;
localparam FIXED = 2'b00; localparam FIXED = 2'b00;
@@ -158,6 +157,7 @@ module axi2sram_sp_external #(
s_arready = 1'b0; s_arready = 1'b0;
// read response channel // read response channel
s_rvalid = 1'b0; s_rvalid = 1'b0;
s_rdata = 'h0;
s_rresp = 'h0; s_rresp = 'h0;
s_rlast = 'h0; s_rlast = 'h0;
s_rid = ax_req_q_id; s_rid = ax_req_q_id;
@@ -208,7 +208,7 @@ module axi2sram_sp_external #(
if (s_wvalid) begin if (s_wvalid) begin
req_o = 1'b1; req_o = 1'b1;
we_o = 1'b1; we_o = 1'b1;
state_d = (s_wlast) ? SEND_B : WRITE_NOP; state_d = (s_wlast) ? SEND_B : WRITE;
cnt_d = 1; cnt_d = 1;
// we still have to wait for the first w_valid to arrive // we still have to wait for the first w_valid to arrive
end else end else
@@ -283,17 +283,11 @@ module axi2sram_sp_external #(
state_d = READ; state_d = READ;
end end
//ext SRAM need nop between continuous write operations
WRITE_NOP: begin
s_wready = 1'b0;
state_d = WRITE;
end
// ~> we already wrote the first word here // ~> we already wrote the first word here
WRITE: begin WRITE: begin
s_wready = 1'b1; s_wready = 1'b1;
state_d = WRITE_NOP; state_d = WRITE;
// consume a word here // consume a word here
if (s_wvalid) begin if (s_wvalid) begin
@@ -377,4 +371,3 @@ module axi2sram_sp_external #(
// end // end
endmodule endmodule