From 5972facc0a5930fcf6201a47161a640eb2e8a09d Mon Sep 17 00:00:00 2001 From: FallenSigh Date: Wed, 24 Jun 2026 21:40:34 +0800 Subject: [PATCH 1/2] Pipeline matmul multiplier: 2-stage to fix WNS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Split compute into stage1 (compute → partial) and stage2 (partial → c_data). Halves CARRY4 chain depth from 16 to ~8 levels. Compute cycles: 16 → 32. --- rtl/ip/matmul/matmul_axi_slave.v | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/rtl/ip/matmul/matmul_axi_slave.v b/rtl/ip/matmul/matmul_axi_slave.v index 70d641a..c69a3a5 100644 --- a/rtl/ip/matmul/matmul_axi_slave.v +++ b/rtl/ip/matmul/matmul_axi_slave.v @@ -71,6 +71,8 @@ reg busy; reg done; reg error; reg [3:0] calc_index; +reg [65:0] partial; // pipeline register for 2-stage multiplier +reg pipe_valid; // partial has valid data wire write_fire; wire start_fire; @@ -288,14 +290,25 @@ always @(posedge clk) begin done <= 1'b0; error <= 1'b0; calc_index <= 4'd0; + pipe_valid <= 1'b0; end else if (busy) begin - c_data[calc_index] <= calc_c_element(calc_index); - if (calc_index == 4'd15) begin - busy <= 1'b0; - done <= 1'b1; - calc_index <= 4'd0; + if (!pipe_valid) begin + // Stage 1: compute element, store in partial + partial <= calc_c_element(calc_index); + pipe_valid <= 1'b1; end else begin - calc_index <= calc_index + 4'd1; + // Stage 2: store partial into c_data, advance + c_data[calc_index] <= partial; + pipe_valid <= 1'b0; + if (calc_index == 4'd15) begin + busy <= 1'b0; + done <= 1'b1; + calc_index <= 4'd0; + partial <= 66'b0; + pipe_valid <= 1'b0; + end else begin + calc_index <= calc_index + 4'd1; + end end end end From bbdc1fd7fe5317f86bc6263fdf1b2ae9bdf7d06d Mon Sep 17 00:00:00 2001 From: FallenSigh Date: Wed, 24 Jun 2026 21:40:59 +0800 Subject: [PATCH 2/2] Fix linter: remove placeholder, fix DVI reg declarations --- rtl/ip/DVI/axi_dvi.v | 14 +++++--------- rtl/soc_top.v | 2 +- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/rtl/ip/DVI/axi_dvi.v b/rtl/ip/DVI/axi_dvi.v index b77b165..0193afd 100644 --- a/rtl/ip/DVI/axi_dvi.v +++ b/rtl/ip/DVI/axi_dvi.v @@ -24,11 +24,11 @@ module axi_dvi # input [3:0] s_awcache, input [2:0] s_awprot, input s_wvalid, - output s_wready, + output reg s_wready, input [31:0] s_wdata, input [3:0] s_wstrb, input s_wlast, - output s_bvalid, + output reg s_bvalid, input s_bready, output [4:0] s_bid, output [1:0] s_bresp, @@ -42,12 +42,12 @@ module axi_dvi # input [0:0] s_arlock, input [3:0] s_arcache, input [2:0] s_arprot, - output s_rvalid, + output reg s_rvalid, input s_rready, - output [31:0] s_rdata, + output reg [31:0] s_rdata, output [4:0] s_rid, output [1:0] s_rresp, - output s_rlast, + output reg s_rlast, output video_clk, // Video clock signal output hsync, // Horizontal sync signal @@ -64,7 +64,6 @@ module axi_dvi # reg [31:0] DVI_RECT_DIR,DVI_RECT_L_W,DVI_SQU_DIR,DVI_SQU_R; reg busy,write,R_or_W; - reg s_wready; wire ar_enter = s_arvalid & s_arready; wire r_retire = s_rvalid & s_rready & s_rlast; @@ -126,8 +125,6 @@ module axi_dvi # else if(w_enter & s_wlast) s_wready <= 1'b0; - reg [31:0] s_rdata; - reg s_rvalid,s_rlast; wire [31:0] rdata_d = buf_addr[15:0] == 16'h0 ? DVI_RECT_DIR : buf_addr[15:0] == 16'h4 ? DVI_RECT_L_W : buf_addr[15:0] == 16'h8 ? DVI_SQU_DIR : @@ -152,7 +149,6 @@ module axi_dvi # end end - reg s_bvalid; always@(posedge aclk) begin if(~aresetn) s_bvalid <= 1'b0; else if(w_enter) s_bvalid <= 1'b1; diff --git a/rtl/soc_top.v b/rtl/soc_top.v index 66f1fb6..eb79757 100644 --- a/rtl/soc_top.v +++ b/rtl/soc_top.v @@ -1078,7 +1078,7 @@ AxiCrossbar_2x8 u_AxiCrossbar_2x8 ( ); -// add your code + core_top u_cpu( .intrpt ({7'b0, confreg_int}), //high active