From 2e4817fea6889f0dafa6395447971de333d335f4 Mon Sep 17 00:00:00 2001 From: FallenSigh Date: Tue, 14 Jul 2026 22:50:44 +0800 Subject: [PATCH] set sysclk to 60Mhz --- rtl/ip/PLL_2019_2/clk_pll.xci | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/rtl/ip/PLL_2019_2/clk_pll.xci b/rtl/ip/PLL_2019_2/clk_pll.xci index 27c681d..6397126 100644 --- a/rtl/ip/PLL_2019_2/clk_pll.xci +++ b/rtl/ip/PLL_2019_2/clk_pll.xci @@ -101,7 +101,7 @@ 32.97872 0000 0000 - 50.00000 + 59.61538 BUFG 50.0 false @@ -117,10 +117,10 @@ BUFG 50.0 false - 50.00000 + 59.61538 0.000 50.000 - 50.000 + 60 0.000 1 1 @@ -203,7 +203,7 @@ din 0000 1 - 0.66 + 0.55 0.33 0.33 0.33 @@ -255,7 +255,7 @@ 0.500 0.000 FALSE - 31 + 26 0.500 0.000 FALSE @@ -293,7 +293,7 @@ Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) _cpu_clk__32.97872______0.000______50.0______130.093____123.600 - _sys_clk__50.00000______0.000______50.0______122.035____123.600 + _sys_clk__59.61538______0.000______50.0______118.808____123.600 no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output @@ -423,11 +423,11 @@ 1 true BUFG - 122.035 + 118.808 false 123.600 50.000 - 50.000 + 60 0.000 1 true @@ -534,7 +534,7 @@ 0.500 0.000 false - 31 + 26 0.500 0.000 false