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Pipeline matmul bank chaining

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FallenSigh
2026-07-01 22:41:31 +08:00
parent ceff12eaf1
commit 2b6e29f761
2 changed files with 85 additions and 37 deletions
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35
rtl/ip/cdma/snix_axil_cdma_mux.sv
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@@ -708,6 +708,8 @@ module snix_axil_cdma_mux #(
wire [31:0] seq_src_addr_for_store = seq_mat_base + (seq_store_idx[0] ? MAT_B1_C_OFF : MAT_B0_C_OFF);
wire [31:0] seq_dst_addr_for_store = seq_dst_base + (seq_store_idx * seq_dst_stride);
wire [31:0] seq_start_value_for_bank = seq_compute_bank ? MAT_CTRL_START_B1 : MAT_CTRL_START_B0;
wire [31:0] seq_start_value_for_loaded_bank =
(seq_load_idx[0] == 1'b0) ? MAT_CTRL_START_B1 : MAT_CTRL_START_B0;
assign seq_awid = '0;
assign seq_awsize = 3'd2;
@@ -925,9 +927,10 @@ module snix_axil_cdma_mux #(
SQ_LOAD1: begin
if (op_done) begin
op_read_addr <= seq_mat_base + MAT_STATUS_OFF;
op_start_read <= 1'b1;
seq_state <= SQ_WAIT_DONE;
op_write_addr <= seq_mat_base + MAT_CTRL_OFF;
op_write_data <= seq_start_value_for_loaded_bank;
op_start_write <= 1'b1;
seq_state <= SQ_START_NEXT;
end
end
@@ -957,7 +960,7 @@ module snix_axil_cdma_mux #(
SQ_STORE: begin
if (op_done) begin
if ((seq_group_idx + 32'd1) >= seq_groups) begin
if ((seq_store_idx + 32'd1) >= seq_groups) begin
seq_state <= SQ_DONE;
end else if (seq_has_more_load) begin
op_src_addr <= seq_src_addr_for_load;
@@ -978,28 +981,28 @@ module snix_axil_cdma_mux #(
if (op_done) begin
seq_group_idx <= seq_group_idx + 32'd1;
seq_compute_bank <= ~seq_compute_bank;
op_write_addr <= seq_mat_base + MAT_CTRL_OFF;
op_write_data <= (~seq_compute_bank) ? MAT_CTRL_START_B1 : MAT_CTRL_START_B0;
op_start_write <= 1'b1;
seq_state <= SQ_START_NEXT;
op_src_addr <= seq_src_addr_for_store;
op_dst_addr <= seq_dst_addr_for_store;
op_bytes <= MAT_C_BYTES;
op_start_copy <= 1'b1;
seq_state <= SQ_STORE;
end
end
SQ_START_NEXT: begin
if (op_done) begin
op_src_addr <= seq_src_addr_for_store;
op_dst_addr <= seq_dst_addr_for_store;
op_bytes <= MAT_C_BYTES;
op_start_copy <= 1'b1;
seq_state <= SQ_STORE;
op_read_addr <= seq_mat_base + MAT_STATUS_OFF;
op_start_read <= 1'b1;
seq_state <= SQ_WAIT_DONE;
end
end
SQ_LOAD_NEXT: begin
if (op_done) begin
op_read_addr <= seq_mat_base + MAT_STATUS_OFF;
op_start_read <= 1'b1;
seq_state <= SQ_WAIT_DONE;
op_write_addr <= seq_mat_base + MAT_CTRL_OFF;
op_write_data <= seq_start_value_for_loaded_bank;
op_start_write <= 1'b1;
seq_state <= SQ_START_NEXT;
end
end