From 297b93b8289f72bfdcd59c0db175f1298e42a58b Mon Sep 17 00:00:00 2001 From: FallenSigh Date: Thu, 2 Jul 2026 00:36:59 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BC=98=E5=8C=96sram=E7=9A=84=E5=86=99?= =?UTF-8?q?=E8=B7=AF=E5=BE=84=EF=BC=8C=E5=BE=85=E9=AA=8C=E8=AF=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../Bus_interconnects/axi2sram_sp_external.v | 80 ++++++++----------- 1 file changed, 35 insertions(+), 45 deletions(-) diff --git a/rtl/ip/Bus_interconnects/axi2sram_sp_external.v b/rtl/ip/Bus_interconnects/axi2sram_sp_external.v index 192b1c1..494f765 100644 --- a/rtl/ip/Bus_interconnects/axi2sram_sp_external.v +++ b/rtl/ip/Bus_interconnects/axi2sram_sp_external.v @@ -95,7 +95,6 @@ module axi2sram_sp_external #( localparam WRITE = 3'h2; localparam SEND_B = 3'h3; localparam WAIT_WVALID = 3'h4; - localparam WRITE_NOP = 3'h5; localparam READ_ADDR = 3'h6; localparam FIXED = 2'b00; @@ -104,10 +103,6 @@ module axi2sram_sp_external #( reg [AXI_ADDR_WIDTH-1:0] req_addr_d, req_addr_q; reg [7:0] cnt_d, cnt_q; - reg [AXI_DATA_WIDTH-1:0] rdata_q; - reg rlast_q; - reg read_capture; - reg read_capture_last; function automatic [AXI_ADDR_WIDTH-1:0] get_wrap_boundary; input [AXI_ADDR_WIDTH-1:0] unaligned_address; @@ -150,8 +145,6 @@ module axi2sram_sp_external #( ax_req_d_burst = ax_req_q_burst; req_addr_d = req_addr_q; cnt_d = cnt_q; - read_capture = 1'b0; - read_capture_last = 1'b0; // Memory default assignments data_o = s_wdata; be_o = s_wstrb; @@ -190,7 +183,7 @@ module axi2sram_sp_external #( ax_req_d_len = s_arlen; ax_req_d_size = s_arsize; ax_req_d_burst = s_arburst; - state_d = READ_ADDR; + state_d = READ; // we can request the first address, this saves us time req_o = 1'b1; addr_o = s_araddr; @@ -215,7 +208,7 @@ module axi2sram_sp_external #( if (s_wvalid) begin req_o = 1'b1; we_o = 1'b1; - state_d = (s_wlast) ? SEND_B : WRITE_NOP; + state_d = (s_wlast) ? SEND_B : WRITE; cnt_d = 1; // we still have to wait for the first w_valid to arrive end else @@ -237,11 +230,14 @@ module axi2sram_sp_external #( end READ: begin + // keep request to memory high + req_o = 1'b1; + addr_o = req_addr_q; // send the response s_rvalid = 1'b1; - s_rdata = rdata_q; + s_rdata = data_i; s_rid = ax_req_q_id; - s_rlast = rlast_q; + s_rlast = (cnt_q == ax_req_q_len + 1); // check that the master is ready, the slave must not wait on this if (s_rready) begin // we sent the last byte -> go back to idle @@ -250,24 +246,7 @@ module axi2sram_sp_external #( // we already got everything end else begin - req_o = 1'b1; - case (ax_req_q_burst) - FIXED, INCR: addr_o = cons_addr; - WRAP: begin - if (cons_addr == upper_wrap_boundary) begin - addr_o = wrap_boundary; - end else if (cons_addr > upper_wrap_boundary) begin - addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES); - end else begin - addr_o = cons_addr; - end - end - endcase - cnt_d = cnt_q + 1; - req_addr_d = addr_o; - read_capture = 1'b1; - read_capture_last = (cnt_d == ax_req_q_len + 1); - state_d = READ; + state_d = READ_ADDR; end end end @@ -275,23 +254,40 @@ module axi2sram_sp_external #( READ_ADDR: begin // keep request to memory high req_o = 1'b1; - addr_o = req_addr_q; - read_capture = 1'b1; - read_capture_last = (cnt_q == ax_req_q_len + 1); + // send the response + s_rvalid = 1'b0; + // ---------------------------- + // Next address generation + // ---------------------------- + // handle the correct burst type + case (ax_req_q_burst) + FIXED, INCR: addr_o = cons_addr; + WRAP: begin + // check if the address reached warp boundary + if (cons_addr == upper_wrap_boundary) begin + addr_o = wrap_boundary; + // address warped beyond boundary + end else if (cons_addr > upper_wrap_boundary) begin + addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES); + // we are still in the incremental regime + end else begin + addr_o = cons_addr; + end + end + endcase + // we need to change the address here for the upcoming request + // we can decrease the counter as the master has consumed the read data + cnt_d = cnt_q + 1; + // save the request address for the next cycle + req_addr_d = addr_o; state_d = READ; end - //ext SRAM need nop between continuous write operations - WRITE_NOP: begin - s_wready = 1'b0; - state_d = WRITE; - end - // ~> we already wrote the first word here WRITE: begin s_wready = 1'b1; - state_d = WRITE_NOP; + state_d = WRITE; // consume a word here if (s_wvalid) begin @@ -350,8 +346,6 @@ module axi2sram_sp_external #( ax_req_q_size <= 3'h0; req_addr_q <= 'h0; cnt_q <= 8'h0; - rdata_q <= 'h0; - rlast_q <= 1'b0; end else begin state_q <= state_d; ax_req_q_addr <= ax_req_d_addr; @@ -361,10 +355,6 @@ module axi2sram_sp_external #( ax_req_q_size <= ax_req_d_size; req_addr_q <= req_addr_d; cnt_q <= cnt_d; - if (read_capture) begin - rdata_q <= data_i; - rlast_q <= read_capture_last; - end end end